Design Verification Tech Lead Engineer, Amazon Leo
Amazon - San Diego, California, USA
Posted Dec 8, 2025
Benefits
- Parental leave
- 6 weeks From the posting source checked Jun 20, 2026
- Non-birth-parent leave
- 6 weeks From the posting source checked Jun 20, 2026
- Family-building benefits
- Mental health support
- Offered From the posting source checked Jun 20, 2026
- Relocation assistance
- Not verified
- Childcare support
- Offered From the posting source checked Jun 20, 2026
- Learning budget
- Not verified
- Verification
- Source-linked checked Jun 7, 2026
- Salary
- $159K-$215K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $66,396 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +3.5% - Average
182% above the BLS role benchmark for design aggregate.
Matched to SOC 27-1024 - Design aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Design Verification Tech Lead Engineer, Amazon Leo San Diego, California, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. The Role: Be part of Amazon Leo's sub-team responsible for defining and implementing the digital chip SOCs for communications via Low Earth Orbit satellites and Amazon gateways. This is a unique opportunity to define a groundbreaking wireless solution with few legacy constraints. The team works with customer requirements and wireless system teams to define modems, high-speed interfaces, embedded processors, and DSP solutions in latest CMOS generation technologies. In this role you will: · Implement a state of the art verification environment for modem IP and subsystem to facilitate testing of the DUT against reference Matlab/C models. · Develop detailed test plans and write tests, run regressions, collect coverage matrices and report progress to the program · Understand and debug system level communication scenarios on pre silicon and post silicon environments. · Work with the design and communication systems team and participate in system level verification using test benches constructed using UVM, SystemC and DPI-C · Develop a highly automated environment to triage regression fails and report issues to stake holders. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S.
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