Design Verification Engineer - technical lead, Annapurna Labs
Amazon - Toronto, Ontario, CAN
Posted Jan 8, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Mental health support
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- Relocation assistance
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Schedule
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- Weekend work
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Application
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Where they hire
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About this role
Design Verification Engineer - technical lead, Annapurna Labs Toronto, Ontario, CAN Amazon Web Services (AWS) is the world's most comprehensive and broadly adopted cloud platform, and our Custom Silicon organization is revolutionizing how we deliver cloud services to our customers. You'll be part of a team that drives innovation in custom chip development, directly impacting the future of cloud computing. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be developing hardware solution for AWS data center including AWS Inferentia,Trainium systems - custom designed machine learning data center accelerator. We are looking for a passionate Design Verification Engineer to join our newly formed team responsible for verifying high-speed I/O and scale-up/out components across the SoC. You will take full ownership of delivering comprehensive verification solutions at a sub-system/chip level, with strong emphasis on system-wide implications and interactions. This role requires developing and implementing verification environments using state-of-the-art simulation methodology. You will create robust test scenarios and collaborate closely with design, architecture, and software teams to ensure thorough coverage of hardware-software interfaces and cross-module functionality. Key job responsibilities - Architect and implement end-to-end verification strategies addressing system-wide implications and cross-module interactions - Drive unified verification plans across multiple environments, tools and methodologies - Provide technical leadership for verification efforts, guiding architectural decisions and methodology choices - Own the technical direction and drive resolution of complex verification challenges at sub-system and chip-level, providing hands-on technical guidance and effective solutions - Guide and mentor team members on best practices, methodology improvements,
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