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FI and Silicon Debug Engineer
Amazon - Haifa, Haifa, ISRIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 171 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedFI and Silicon Debug Engineer Haifa, Haifa, ISR AWS Utility Computing (UC) provides product innovations - from foundational services such as Amazon's Simple Storage Service (S3) and Amazon Elastic Compute Cloud (EC2), to consistently released new product innovations that continue to set AWS's services and features apart in the industry. As a member of the UC organization, you'll support the development and management of Compute, Database, Storage, Internet of Things (Iot), Platform, and Productivity Apps services in AWS. Within AWS UC, Amazon Dedicated Cloud (ADC) roles engage with AWS customers who require specialized security solutions for their cloud services. Annapurna Labs is a semiconductor company established by semiconductor industry veterans and is now part of Amazon Web Services (AWS). We are developing leading edge products, manufactured on leading edge technologies. We offer a dynamic, open, teamwork environment operating at high pace mode. The main scope of this role is to lead AWS silicon debug efforts and provide insights related to complex design issues, open test holes, low yield events and reliability failures, related to our cutting-edge silicon-based products embedded into AWS cloud. Key job responsibilities Your responsibilities will include, but not be limited to: • Utilizing testers and system boards in combination with optical debug and fault isolation (FI) techniques such as: laser stimulation operations (OBIRCH, LADA, etc.), laser probing and emission microscopy. • Root cause failures and performance limitations and drive decision making related to test coverage and yield issues. • Analyzing and diving deep into fundamental aspects of
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Principal ProServe Account Exec, ProServe AWSI Automotive and Manufacturing
Amazon - Chicago, Illinois, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 73 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Teaching Education From the posting source - Principal From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $170K-$230K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedPrincipal ProServe Account Exec, ProServe AWSI Automotive and Manufacturing Chicago, Illinois, USA AWS Professional Services is seeking a world-class sales professional to own, build, and grow a portfolio of multi-million dollar professional services engagements with some of the largest and most complex automotive and manufacturing enterprises in the world. This is a high-visibility, quota-carrying role with full ownership of your book of business - you will hunt, create, and close transformative deals that help customers reinvent their businesses with cloud and Generative AI. The automotive and manufacturing industries are in the midst of a once-in-a-generation transformation. Generative AI, applied machine learning, and cloud-native architectures are fundamentally reshaping how these companies design products, run factories, and deliver customer experiences - and the pace is accelerating. You will be at the center of this transformation, working directly with executives and technology leaders to define bold visions and then close the deals that make them real. As the ProServe Account Executive, you own the customer relationship and the revenue. You are a core member of the sales account team alongside Account Managers, Solutions Architects, and Partner teams - but you are the one who identifies the professional services opportunity, shapes it, prices it, and closes it. You will develop and execute against ambitious revenue targets, build a robust pipeline, and negotiate complex commercial agreements. Following deal close, you stay connected to ensure delivery of agreed Customer Business Outcomes (CBOs) and to identify the next wave of opportunities. If you thrive on complexity, think
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Machine Learning Engineer, WWPS ProServe, Data & Machine Learning (DML)
Amazon - Arlington, Virginia, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 118 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $131K-$178K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported Top Secret clearance US citizenship requiredMachine Learning Engineer, WWPS ProServe, Data & Machine Learning (DML) Arlington, Virginia, USA This position requires that the candidate selected be a US Citizen and must currently possess and maintain an active TS/SCI security clearance. The Amazon Web Services Professional Services (ProServe) team is seeking a skilled Machine Learning Engineer to join our team at Amazon Web Services (AWS). Are you looking to work at the forefront of Machine Learning and AI? Would you be excited to apply Generative AI algorithms to solve real world problems with significant impact? In this role, you'll work directly with customers to design, evangelize, implement, and scale AI/ML solutions that meet their technical requirements and business objectives. You'll be a key player in driving customer success through their AI transformation journey, providing deep expertise in machine learning, generative AI, and best practices throughout the project lifecycle. As a Machine Learning Engineer within the AWS Professional Services organization, you will be proficient in architecting complex, scalable, and secure machine learning solutions tailored to meet the specific needs of each customer. You'll help customers imagine and scope the use cases that will create the greatest value for their businesses, select and train and fine tune the right models, and define paths to navigate technical or business challenges. Working closely with stakeholders, you'll assess current data infrastructure, develop proof-of-concepts, and propose effective strategies for implementing AI and generative AI solutions at scale. You will design and run experiments, research new algorithms, and find new ways of optimizing
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Apprenti(e) Finance Dir Fi
Ecolab - FRA - Nord-Pas-de-Calais - LilleIndexed from Workday Benefit evidence checked Jun 7, 2026posted 62 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Finance From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedApprenti(e) Finance Dir Fi FRA - Nord-Pas-de-Calais - Lille posted: Posted Today
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Silicon DFT Engineer, Cloud Silicon
Google - Bengaluru, Karnataka, IndiaIndexed from Google Custom Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSilicon DFT Engineer, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition,
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Machine Learning Engineer, WWPS ProServe Delivery Team
Amazon - Arlington, Virginia, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 119 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $131K-$178K From the posting source Inferred from posting Adoption assistance Inferred from posting Surrogacy assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reported Top Secret clearanceMachine Learning Engineer, WWPS ProServe Delivery Team Arlington, Virginia, USA The Amazon Web Services Professional Services (ProServe) team is seeking a skilled Machine Learning Engineer to join our team at Amazon Web Services (AWS). Are you looking to work at the forefront of Machine Learning and AI? Would you be excited to apply Generative AI algorithms to solve real world problems with significant impact? In this role, you'll work directly with customers to design, evangelize, implement, and scale AI/ML solutions that meet their technical requirements and business objectives. You'll be a key player in driving customer success through their AI transformation journey, providing deep expertise in machine learning, generative AI, and best practices throughout the project lifecycle. As a Machine Learning Engineer within the AWS Professional Services organization, you will be proficient in architecting complex, scalable, and secure machine learning solutions tailored to meet the specific needs of each customer. You'll help customers imagine and scope the use cases that will create the greatest value for their businesses, select and train and fine tune the right models, and define paths to navigate technical or business challenges. Working closely with stakeholders, you'll assess current data infrastructure, develop proof-of-concepts, and propose effective strategies for implementing AI and generative AI solutions at scale. You will design and run experiments, research new algorithms, and find new ways of optimizing risk, profitability, and customer experience. The AWS Professional Services organization is a global team of experts that help customers realize their desired business outcomes when
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DevOps Engineer - Observability
Adobe Inc. - BucharestIndexed from Workday Benefit evidence checked May 7, 2026posted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 16 wksource Resolvable source Verified non-birth-parent leave: 16 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDevOps Engineer - Observability Bucharest posted: Posted 7 Days Ago
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Silicon SoC DFT Technical Lead, Google Cloud
Google - Bengaluru, Karnataka, IndiaIndexed from Google Custom Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSilicon SoC DFT Technical Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, functional BISTs, Analog components, logic BIST, high-speed I/O loopback, and
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AI/ML Silicon Validation Lead, Google Cloud, TPU
Google - Bengaluru, Karnataka, IndiaIndexed from Google Custom Benefit evidence checked May 7, 2026posted 63 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAI/ML Silicon Validation Lead, Google Cloud, TPU Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The Platform Enablement team is responsible for the development, bring-up and qualification, deployment, sustaining the quality of our AI/ML custom silicon. We plan and integrate hardware and software stacks and operate them on emulation, simulation and post-silicon platforms. We work closely with silicon design, platform hardware, firmware and software teams to enable on-time delivery of high quality silicon products. As a Manager, you will be responsible for growing the team through hiring, developing a psychologically safe environment for the team to succeed, enabling people development through effective career conversations, mentoring and building a strong community. In this role, you will be working on building, managing and leading a team of engineers responsible for post-silicon validation of AI/ML SoC which uses technology, working closely with the architecture, design, verification, firmware, software and platform leads, ensure timely silicon bring-up, enablement and debug closures and driving the preparation of necessary tests and collaterals for effective
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Embedded Firmware Engineer, Digital Signal Processing
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $192K-$279K From the posting source Equity Inferred from posting 401(k) reportedEmbedded Firmware Engineer, Digital Signal Processing Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will architect the control-plane software for the entire high-speed Physical Layer (PHY). You will lead the development of complex state machines for link training and auto-negotiation that allow Google's AI clusters to communicate reliably at next-generation data rates. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking,
- posted 73 days ago
Why we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedBefunder (w/m/d) Birr posted: Posted 11 Days Ago
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Stagiaire Implémentation, test et validation d’une fonction de détection de défaut de non-conduction d’un bras de pont (H/F)
GE Vernova - BelfortIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedStagiaire Implémentation, test et validation d’une fonction de détection de défaut de non-conduction d’un bras de pont (H/F) Belfort posted: Posted 30+ Days Ago
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SoC Input Output Architect, Silicon, Google Cloud
Google - Tel Aviv, Israel; +1 moreIndexed from Google Custom Benefit evidence checked May 7, 2026posted 72 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSoC Input Output Architect, Silicon, Google Cloud Tel Aviv, Israel; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Google's Silicon team is driving the future of cloud data center computing. As a System on Chip Input Output (SoC IO) Architect, you will help define a new generation of Google's products. You will have pivotal responsibilities and serve as the organization Mobile Industry Processor Interface (MIPI) focal point. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of
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SW DevOps Engineer
NXP Semiconductors - BucharestIndexed from Workday Benefit evidence checked May 7, 2026posted 71 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSW DevOps Engineer Bucharest posted: Posted 9 Days Ago
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Silicon Validation Engineering Manager, Cloud
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $192K-$279K From the posting source Equity Inferred from posting 401(k) reportedSilicon Validation Engineering Manager, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Validation Engineering Manager, you will lead the group focused on custom TPU silicon. You will set strategy and co-ordinate resources, planning, and execution for the team. You will strategize, review, and execute test plans for silicon systems and subsystems. You will own silicon bringup, new product introduction (NPI), and sustaining efforts. You will serve as the central co-ordination point between your team and systems teams, including hardware, software, manufacturing, and supply chain. You will also manage relationships with vendors and contract manufacturers. You will verify that silicon meets functional and performance requirements and own qualification, characterization, and deliverables for post-silicon, including interfaces, compute cores, power, and performance. You will debug issues, suggest fixes, and ensure silicon meets quality and reliability requirements throughout the entire product life-cycle (PLC). The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure
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Junior Silicon DFT Engineer, Google Cloud
Google - Tel Aviv, Israel; +1 moreIndexed from Google Custom Benefit evidence checked May 7, 2026posted 66 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Entry From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedJunior Silicon DFT Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG),
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Geospatial Intelligence Analyst
Leidos - Fort Belvoir, VAIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedGeospatial Intelligence Analyst Fort Belvoir, VA posted: Posted 30+ Days Ago
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GridOS Database Modelling Engineer
GE Vernova - BucharestIndexed from Workday Benefit evidence checked May 7, 2026posted 86 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedGridOS Database Modelling Engineer Bucharest posted: Posted 24 Days Ago
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Engineer, Software Infrastructure
Analog Devices - Romania, Cluj-NapocaIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedEngineer, Software Infrastructure Romania, Cluj-Napoca posted: Posted 30+ Days Ago
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Principal Engineer, Embedded Software
Analog Devices - Romania, Cluj-NapocaIndexed from Workday Benefit evidence checked May 7, 2026posted 66 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Engineer, Embedded Software Romania, Cluj-Napoca posted: Posted 4 Days Ago
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Acheteur services (H/F)
GE Vernova - GrenobleIndexed from Workday Benefit evidence checked May 7, 2026posted 93 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedAcheteur services (H/F) Grenoble posted: Posted 30+ Days Ago
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Staff GridOS Integrator - DevOps
GE Vernova - BucharestIndexed from Workday Benefit evidence checked May 7, 2026posted 87 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedStaff GridOS Integrator - DevOps Bucharest posted: Posted 25 Days Ago
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Silicon CAD Engineer, University Graduate, PhD
Google - Sunnyvale, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 69 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $138K-$198K From the posting source Equity Inferred from posting 401(k) reportedSilicon CAD Engineer, University Graduate, PhD Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on chips powering the next generation of Google Cloud systems. You will work well both separately and as part of a team. In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed Electronic Design Automation (EDA) tools, custom tooling, and emergent technologies from GDM and core. The AI and Infrastructure team is redefining what's possible. We empower
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Senior Silicon DFT Lead
Google - Haifa, Israel; +1 moreIndexed from Google Custom Benefit evidence checked May 7, 2026posted 101 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Silicon DFT Lead Haifa, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC). Develop DFT strategy
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