Stmicroelectronics jobs
0 matches, filter-driven and evidence-linked.
Filters
0 active
Remote, hybrid, onsite
State
Shift type
Weekend work
Country
Cover letter
Assessment
Salary type
Equity type
Family-building benefits
Benefit evidence
-
Principal/Sr Principal Engineer Microelectronic Semiconductors
Northrop Grumman - United States-California-Manhattan BeachIndexed from Workday Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 114 days agoWhy we showed this
Title: semantic matchRole: semantic match+2
Unspecified Engineering From the posting source - Principal From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $114K-$171K From the posting source Inferred from posting Childcare support Inferred from posting Relocation assistance Equity Inferred from posting 401(k) reported Secret clearance US citizenship requiredPrincipal/Sr Principal Engineer Microelectronic Semiconductors United States-California-Manhattan Beach RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: None TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. The Northrop Grumman Microelectronics Center (NGMC) has an opening for a Microelectronics Device Engineer to join our team of qualified, diverse individuals at our Space Park Foundry (SPF) location in Redondo Beach, CA. In the NGMC we design, manufacture, and test semiconductor products for internal and commercial production customers as well as emerging technology programs. The SPF semiconductor foundry has unique capabilities supporting a range of production microelectronics technologies (Gallium Arsenide, Indium Phosphide, and Gallium Nitride). SPF provides leading edge technology development in semiconductor materials, processes, devices, and 3D
-
Electrical Engineer - Embedded Systems
Abbott Laboratories - United States - Minnesota - St. PaulIndexed from Workday Benefit evidence checked May 7, 2026posted 123 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 8 wksource Resolvable source Verified non-birth-parent leave: 8 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedElectrical Engineer - Embedded Systems United States - Minnesota - St. Paul posted: Posted 16 Days Ago
-
Senior Principal SoC Physical Implementation/STA Engineer
NXP Semiconductors - 2 LocationsIndexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Principal SoC Physical Implementation/STA Engineer 2 Locations posted: Posted 30+ Days Ago
-
Static Timing Analysis Engineer, Full-Chip STA
Google - Mountain View, CA, USAIndexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in postingposted 114 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $138K-$198K From the posting source Equity Inferred from posting 401(k) reportedStatic Timing Analysis Engineer, Full-Chip STA Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $198000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Deliver system-on-chip (SoC) Static Timing Analysis. Define SoC timing signoff process corners, derates, uncertainties and their tradeoffs. Drive clock tree Jitter and implementation for SoCs to achieve best energy, performance and area. Execute full chip timing constraint validation and timing signoff checklist criteria, perform full chip Static Timing Analysis (STA) and timing Engineering Change Order (ECO) creation, and oversee final timing signoff for SoCs. Minimum qualifications: Bachelor's degree in Electrical Engineering or Computer Science, or equivalent practical experience. 4 years of technical experience in silicon timing closure and chip integration. Experience in one or more static timing tools (e.g., PrimeTime,
-
Sr. Principal Engineer -STA
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr. Principal Engineer -STA Noida posted: Posted 30+ Days Ago
-
Sr. System Electrical Engineer, eero
Amazon - San Francisco, California, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 292 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource $214K-$214K From the posting source Equity Inferred from posting 401(k) reported US citizenship requiredSr. System Electrical Engineer, eero San Francisco, California, USA As a Sr. System Electrical Engineer at eero, you will work with the rest of the Hardware Engineering team to design, implement, debug, and characterize embedded systems for wired and wireless networking applications. You may own one or more electrical sub-systems within a hardware product, ranging from low-speed digital logic circuits to memory and high-speed digital interfaces, as well as the integration of those into the rest of the system. You will collaborate with RF and antenna engineers to integrate these sensitive sub-systems without compromising their performance. You will also work with mechanical engineers to ensure that electronic components are placed at suitable locations within a device, have proper thermal management solutions associated with them, and can meet reliability requirements. Key job responsibilities In this role, you will: • Evaluate and select electronic components based on system requirements • Develop and review board schematics • Review and optimize board layouts for signal and power integrity • Perform bring-up of new board designs • Develop hardware test plans and automation scripts for engineering and manufacturing tests • Participate in the process of taking eero's hardware from the prototype stage to mass production • Provide engineering support to manufacturing during the NPI process Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. About
-
Sr Electrical Engineer - ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr Electrical Engineer - ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Principal Electrical Engineer - ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Electrical Engineer - ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Principal Electrical Engineer - ASIC/FPGA Verification (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Electrical Engineer - ASIC/FPGA Verification (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Senior Electrical Engineer – DSP ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Electrical Engineer – DSP ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Electrical Engineer - ASIC/FPGA Verification (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Principal Electrical Engineer – DSP ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 121 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Electrical Engineer – DSP ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
-
Sr Electrical Engineer – Design Verification - FPGA/ASIC (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121Indexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr Electrical Engineer – Design Verification - FPGA/ASIC (Onsite) US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121 posted: Posted 30+ Days Ago
-
Sr Electrical Engineer (Onsite)
Raytheon Technologies - MX-BCN-MEXICALI-496 ~ Calzada Manuel Gomez Morin #3200 ~ CALZADAIndexed from Workday Benefit evidence checked May 7, 2026posted 137 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr Electrical Engineer (Onsite) MX-BCN-MEXICALI-496 ~ Calzada Manuel Gomez Morin #3200 ~ CALZADA posted: Posted 30 Days Ago
-
SoC Hardware Architect
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 114 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSoC Hardware Architect Austin (Oakhill, Office) posted: Posted 7 Days Ago
-
Sr Electrical Engineer - FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121Indexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr Electrical Engineer - FPGA (Onsite) US-IA-CEDAR RAPIDS-121 ~ 350 Collins Rd NE ~ BLDG 121 posted: Posted 30+ Days Ago
-
Duales Studium Embedded Systems B.Eng. 2026 (m/w/d)
Carrier Global - Viessmann Shared Service GmbH, Viessmannstraße 1, 35107 Allendorf (Eder), GermanyIndexed from Workday Benefit evidence checked May 7, 2026posted 119 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 8 wksource Resolvable source Verified non-birth-parent leave: 8 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedDuales Studium Embedded Systems B.Eng. 2026 (m/w/d) Viessmann Shared Service GmbH, Viessmannstraße 1, 35107 Allendorf (Eder), Germany posted: Posted 12 Days Ago
-
Staff Digital Design Engineer for MEMs ASIC
Analog Devices - Spain, Valencia, Cortes ValencianasIndexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedStaff Digital Design Engineer for MEMs ASIC Spain, Valencia, Cortes Valencianas posted: Posted 30+ Days Ago
-
Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices
Amazon - Shenzhen, CHNIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 124 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies
-
IC SoC Product & Subsystem Architect (f/m/d)
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIC SoC Product & Subsystem Architect (f/m/d) Hamburg posted: Posted 30+ Days Ago
-
Working Student (f/m/d) RF Validation and Lab Automation
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 137 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedWorking Student (f/m/d) RF Validation and Lab Automation Hamburg posted: Posted 30 Days Ago
-
Sr. Principal Electronics Engineer
Northrop Grumman - United States-California-San DiegoIndexed from Workday Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 138 days agoWhy we showed this
Title: semantic matchRole: semantic match+2
Unspecified Engineering From the posting source - Principal From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $142K-$213K From the posting source Inferred from posting Childcare support Inferred from posting Relocation assistance Equity Inferred from posting 401(k) reported Secret clearance US citizenship requiredSr. Principal Electronics Engineer United States-California-San Diego RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: Yes CLEARANCE TYPE: Secret TRAVEL: Yes, 25% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Northrop Grumman Aeronautics Systems is looking to add a Sr Principal Electronics Engineer to join our team in Rancho Bernardo, CA. This position will be in our Avionics Integration Organization. Duties and Responsibilities include, but are not limited to: Research, design, development, integration, and test of a variety of electronic equipment and systems, including RF datalinks, SATCOM and Communications Networks as the Comms Resiliency Lead. Maintaining complex RF communications architectures, systems; circuitry components; analog and digital computers. Reporting comms status to Program Managers and IPT Management. Primary Responsible Engineer for
-
Sr Principal Engineer Electronics
Northrop Grumman - United States-Arizona-ChandlerIndexed from Icims Benefit evidence checked Jun 7, 2026posted 107 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr Principal Engineer Electronics United States-Arizona-Chandler
-
Sr. RF Hardware Systems Engineer
Samsara - San Francisco - SF9Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 109 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 16 wksource Inferred from posting Verified non-birth-parent leave: 16 wk $177K-$240K From the posting source Inferred from posting Childcare support Inferred from posting Mental health support Inferred from posting Learning budget Equity Inferred from posting 401(k) reportedSr. RF Hardware Systems Engineer San Francisco - SF9 Who we are Samsara (NYSE: IOT) is the pioneer of the Connected Operations™ Cloud, which is a platform that enables organizations that depend on physical operations to harness Internet of Things (IoT) data to develop actionable insights and improve their operations. At Samsara, we are helping improve the safety, efficiency and sustainability of the physical operations that power our global economy. Representing more than 40% of global GDP, these industries are the infrastructure of our planet, including agriculture, construction, field services, transportation, and manufacturing - and we are excited to help digitally transform their operations at scale. Working at Samsara means you'll help define the future of physical operations and be on a team that's shaping an exciting array of product solutions, including Video-Based Safety, Vehicle Telematics, Apps and Driver Workflows, and Equipment Monitoring. As part of a recently public company, you'll have the autonomy and support to make an impact as we build for the long term. About the role We're looking for a Senior Hardware Engineer, RF Systems to own critical RF subsystems and help define platform‑level RF architectures that power Samsara's connected hardware portfolio. You'll combine deep RF expertise with strong product instincts, partnering with cross‑functional teams to ship robust, high‑volume hardware. Our hardware team owns end‑to‑end product development for Samsara's AI & Connected devices, from architecture and component selection through validation and ramp to mass production. Within this team, you will lead RF and wireless architectures and
Take this list with you
Download the 0 matching jobs in any format - read offline, archive, or hand to an AI assistant with your resume to find the best fits.
Or email it to me instead
The AI-ready prompt is a pre-written question you can paste into Claude, ChatGPT, Gemini, or Perplexity along with your resume. We never see your resume; this happens in your AI client of choice.
AI agent reading directly? Same data lives at /api/jobs.json?q=STMicroelectronics&quality=all&verified_benefits_only=true.
See /llms.txt and /api/openapi.json for the full schema.