Matik jobs

Sr. Demand Generation Manager San Francisco / Remote About Matik: Matik automates the creation of presentations, documents, and reports directly from your data, powered by AI you can trust. Pull from dashboards, reports, and data in your BI, CRM, data warehouse and other sources to instantly produce on-brand, insight-rich content in formats you already use today. Trusted by teams at Okta, Asana, Autodesk, Samsara, and Zapier, Matik empowers any team to align messaging, scale best practices, and tell consistent data stories that drive action - faster than ever. Founded in 2019 by Nikola Mijic and Zak Stein and headquartered in San Francisco, Matik is backed by Andreessen Horowitz, Menlo Ventures, Box Group, and Oceans Ventures. Matik Mission: - Transforming the way people work by automating the generation of repetitive data-driven narratives Matik Values: Our core values guide the way we interact with each other and are the foundation for how we execute on our mission and vision. - Customer First - we don't want to just build products that we like, but rather our customers find extremely valuable. This doesn't mean we compromise our other values or build whatever a customer wants. Lastly, the security of our customer's data is very important to us and we want to ensure our decision making keeps this in mind. - Trust and Transparency - at the core of every relationship is Trust. It is imperative that we gain and maintain the trust of our colleagues, customers, and investors by being honest, transparent, and

Hardware System Electrical Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. About the Role: We are looking for a Hardware Systems Engineer to join our Hardware Systems team. In this role, you will take full ownership of defining, designing, and validating compute trays, boards, and interconnects for our rack-scale AI data center platform. You will work across control plane, data plane, and management plane functionality, playing a pivotal role in driving power efficiency, scalability, reliability, and system performance at scale What You'll Do Here: - Full ownership of board design, specifications, schematic design, verification and reliability test plan for our AI compute boards - Design and capture schematic and work with layout engineers to release Gerber files - Collaborate with cross-functional teams, such as thermal, mechanical, SIPI, ASIC, platform software and manufacturing diagnostic software teams. - Bring up boards and debug hardware issues in the lab - Support platform and manufacturing tests - Collaborate with JDM Who You Are: - At least 10

ASIC/SOC CAD Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking a Physical Design CAD Engineer to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The ASIC/SOC Physically Design CAD Engineer will be responsible for creating and maintaining our CAD flow and infrastructure to produce performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Develop, maintain, and continuously improve MatX's Physical Design flow, from RTL to GDSII flow, including construction and sign-off - Automate back-end runs, create reports, post-process logs, generate metrics, and extract insights - Evaluate, select, and deploy EDA tools and methodologies to produce best-in-class Performance-Power-Area results - Work with EDA tool vendors to drive issues and enhancements to closure - Train and support flow users and resolve any issues they might face - Manage licenses, compute, and storage and optimize for efficiency and cost - May include some development and support of the front-end CAD flow Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise developing/using industry-standard ASIC tools and methodologies

ASIC/SOC Silicon Physical Design Engineer Mountain View, CA What MatX Is Building MatX's mission is to make the world's best AI models run as efficiently as allowed by physics, bringing the world years ahead in AI quality and availability. MatX is seeking silicon physical design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Silicon Physical Design Engineers will be responsible for developing performant and functionally correct silicon for MatX products across compute, memory management, high-speed connectivity, and other key technologies in leading-edge process nodes. What You'll Do Here - Contribute to MatX's Physical Design methodology to achieve a scalable solution across block, subsystem, and fullchip designs from RTL to GDSII - Own entire subsystems or subsets and/or chip-level Physical Design deliverables including but not limited to: construction (partitioning, floorplanning, synthesis, place & route, clocking) and sign-off (equivalency, extraction, timing, power estimation, EMIR, physical verification) - Plan and drive intermediate and sign-off reviews. Report execution progress towards various silicon milestones including design freeze and tapeout - Work closely with the Design, DFT, and other Physical Design co-owners of the subsystem/block in question to deliver best-in-class Performance-Power-Area results Who You Are - Bachelor of Science in Electrical Engineering or equivalent - Minimum 8 years of industry experience in ASIC Physical Design - Great interpersonal and communication skills - Strong proficiency in programming languages such as Perl, Python, and TCL - Expertise driving Physical Design construction and sign-off for blocks, subsystems, and/or fullchip from early RTL

Hardware System Diagnostic Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. We are looking for a Diagnostic Engineer to join our Hardware System team. The successful candidate will be responsible for defining, designing, and owning the end-to-end diagnostics test suite for manufacturing, debugging and deployment of our rack-scale AI data center product. This role is crucial for collaborating with JDM to ensure high manufacturing yield and robust products from manufacturing to customer deployment. What You'll Do Here - Own the end-to-end diagnostics test suite for accelerator boards and racks - Develop diagnostic tools covering the AI chip, PCIe, HBM, power, and thermal - Define test coverage and pass/fail criteria for manufacturing screening - Enable JDM/ODM partners with documentation, tooling, and hands-on debug support - Support partners technically through NPI and production ramp phases - Triage and root-cause manufacturing test escapes and field failures - Build and maintain CI/CD infrastructure for the diagnostics software stack - Track quality metrics - yield, test coverage, defect

Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. What You'll Do Here - Develop, support, and own hardware architecture throughout the product lifecycle - Deeply understand customer use cases, workload performance, and ML systems research - Produce requirements and architecture specifications - Estimate hardware area, timing, and power to inform architectural trade-offs - Collaborate closely with Research, Software, and Hardware teams - Interface with vendors and customers - Architectural Responsibilities May Include: - Parallel Compute: SIMD, Vector, VLIW, and other parallel execution models - Data Movement: Efficient storage and communication across memory and network fabrics - Distributed Systems: Workload mapping, bottleneck analysis, and scalable distributed systems Who You Are - Expertise in modern high-performance CPU, GPU, or AI accelerator architecture and hardware/software interactions - Experience analyzing and optimizing system performance using diverse tools and methodologies - Proficiency in programming and code optimization - Excellent writing skills - This is a hybrid role that will require you to work from our Mountain View, CA office 3

SOC Intergration Engineer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Drive the evolution of MatX's silicon architecture-to-design methodology by engineering scalable solutions for the seamless integration of all Subsystems into a comprehensive full-chip SOC RTL design. - Partner with SubSystem owners within the Design team to facilitate block integration and spearhead the development of the System-On-Chip (SOC) Top-level RTL. - Implement advanced automation for SOC top-level RTL integration and build processes to enable on-the-fly generation of SOC top-level RTL. - Collaborate closely with the Full Chip owner on the Physical Design team to incorporate necessary RTL modules and feedthroughs/highways, ensuring alignment with chip-level floorplan connectivity requirements within the SOC RTL. - Establish robust clock and reset methodologies through cross-functional collaboration with system, architecture, design, and physical design teams. - Define and support SoC-level timing constraints, ensuring rigorous validation against Subsystem design and physical design requirements. - Provide technical support to package and board teams by defining SOC pin

Technical Hardware/Semiconductor Recruiter Mountain View, CA MatX is on a mission to make the world's best AI models run as efficiently as possible-accelerating global progress in AI quality and accessibility. We are building cutting-edge AI infrastructure at the intersection of hardware and software, and our team is growing quickly. We are seeking a Technical Recruiter with deep experience in technical recruiting and a strong understanding of the Semiconductor, Hardware and AI landscape. This role will play a critical part in scaling our teams by owning key stages of the hiring process, delivering an exceptional candidate experience, and driving performance through reporting key metrics for talent acquisition to senior leadership and hiring teams. This position is ideal for someone who thrives in a fast-paced startup environment, partners effectively with a wide range of stakeholders, and brings both rigor and empathy to recruiting. You will have a direct impact on company growth and will help shape recruiting processes as MatX continues to scale. This is a hybrid role that will require you to work from our Mountain View, CA office 3 days a week on Tuesday through Thursday What You'll Do Here - Hire for specialized Semiconductor and Hardware engineering roles that span product development cycle from architecture to various functional engineering roles, including design, validation, testability, silicon physical design, system hardware design, infrastructure-as-code, customer support, and product deployment - Previous experience recruiting for ASIC, SOC, Silicon Design, Silicon Architecture, Security and Verification highly preferred - Hire for specialized Semiconductor and Hardware

AI Accelerator Silicon Architect Mountain View, CA What MatX Is Building MatX designs hardware tailored for the world's best AI models. Our hardware will make a given level of intelligence available 3-5 years sooner. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the world's largest models. MatX is seeking an Architect to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. The successful candidate for this role will be responsible for delivering performant silicon architecture at the full-chip or subsystem level. MatX is seeking an AI Accelerator Compute Architect to help define the compute architecture for our next-generation GenAI accelerators. What You'll Do - Define the architecture for MatX's AI compute subsystem, including ISA, connectivity, memories, and control.. - Derive architectural requirements from AI use cases. - Conduct analytical and empirical performance analysis. - Collaborate closely with Research, SW, and HW teams to ensure we architect just-right silicon for workloads, programmability, and PPA. - Work through power, area, performance tradeoffs with stakeholders. - Support test plan reviews, first-silicon bring-up, and post-silicon debug. Who You Are - Strong background in computer architecture, especially AI accelerators, GPUs, TPUs, vector processors, SIMD, VLIW, or other parallel compute architectures. - Experience translating workloads into hardware architecture. - Solid microarchitecture fundamentals. - First-principles understanding of latency, throughput, utilization, and scalability. - Familiarity with numeric formats, quantization, rounding, and precision/performance tradeoffs. - Programming, code optimization, or kernel-level performance analysis experience. -

Senior Data Scientist United Arab Emirates, Dubai Dataiku is the Platform for AI Success, the enterprise orchestration layer for building, deploying, and governing AI. In a single environment, teams design and operate analytics, machine learning, and AI agents with the transparency, collaboration, and control enterprises require. Sitting above data platforms, cloud infrastructure, and AI services, Dataiku connects the full enterprise AI stack - empowering organizations to run AI across multi-vendor environments with centralized governance. The world's leading companies rely on Dataiku to operationalize AI and run it as a true business performance engine delivering measurable value. For more, visit the Dataiku blog , LinkedIn , X , and YouTube . The role of a Data Scientist at Dataiku is quite unique. Our Data Scientists not only code up solutions to real-world problems, but also participate in client-facing endeavours throughout the customer journey. This includes supporting their discovery of the platform, helping integrate Dataiku with other tools and technologies, some user training, and co-developing data science projects from design to deployment. Just as non-technical skills are important, so too are technical skills. Our Data Scientists work on the Dataiku platform every day. Aside from the visual tools, our team primarily uses Python and SQL, with occasional work in other languages (e.g., R, PySpark, JavaScript). An ideal candidate is excited to learn complex new technologies and modelling techniques while being able to explain their work to other data scientists and clients. In this role, you'll help the team: - Co-develop production-level data

Silicon Micro-Architect and RTL Designer Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. What You'll Do Here - Contribute to MatX's silicon architecture-to-design methodology with a scalable solution across blocks, subsystems, fullchip design - Own entire subsystem or subsets and/or chip-level silicon design deliverables from micro-architecture to sign-off ready design - Plan and drive intermediate and sign-off reviews on micro-architecture and design specifications, execution progress, area and timing closure towards various silicon milestones including design freeze and tapeout - Work closely with the verification, DFT, and physical design co-owners of the subsystem/block in question and deliver best-in-class performance-power-area results Who You Are - Concept-to-silicon experience in driving silicon design for subsystems and/or top-level functions with ASICs and SOCs from an architecture specification to production silicon - 2 years or more experience with SystemVerilog, Python, C/C++ and similar scripting and programming languages for chip design and related flows - Production-proven experience on silicon micro-architecture and design concepts used in high-performance compute (CPUs, GPUs, accelerators), high-speed

AVP Premier Relationship Manager (Nashik) Pune, Maharashtra, India

Platform Technical Project Manager, Rack-Scale AI Sysytems Mountain View, CA What MatX Is Building MatX is on a mission to be the compute platform for AGI. We are developing vertically integrated full-stack solutions from silicon to systems including hardware and software to train and run the largest ML workloads for AGI. MatX is seeking silicon micro-architects and design engineers to join our team as we create best-in-class silicon for high-performance and sustainable GenAI. Successful candidates for these roles will be responsible for delivering performant and functionally accurate silicon for MatX products across compute, memory management. High-speed connectivity and other key technologies. About the Role MatX is building next-generation AI infrastructure systems for high-performance datacenter workloads. We are looking for a Senior Platform TPM, Rack-Scale AI Systems to drive design-phase execution for our rack-scale platform. This role will coordinate cross-functional execution across rack architecture, accelerator board design, power delivery, thermal and liquid cooling, high-speed interconnect, firmware, diagnostics, test vehicles, system validation, and external CM/JDM partner engagement. You will work closely with Systems Engineering, hardware engineering, firmware, validation, supply chain, and external CM/JDM partners. What You'll Do Here - Drive the integrated execution plan for rack and board design from architecture through design release. - Own and maintain the design-phase master schedule across rack, board, power, thermal, interconnect, mechanical, firmware, diagnostics, validation, and supply-chain dependencies. - Coordinate execution across key platform workstreams, including board electrical/SI/PI readiness, rack power, liquid cooling, cable/optical interconnect, BMC/telemetry, diagnostics, test vehicles, PLM/BOM/ECO readiness, and external CM/JDM design

Matlab/Simulink Engineer (Associate or Mid-Level) 2 Locations posted: Posted 10 Days Ago

Senior SimOps Engineer Onsite - Austin, TX Apptronik is a human-centered robotics company developing AI-powered robots to support humanity in every facet of life. Our flagship humanoid robot, Apollo, is built to collaborate thoughtfully with people, starting with critical industries such as manufacturing and logistics, with future applications in healthcare, the home, and beyond. We operate at the cutting edge of embodied AI, applying our expertise across the full robotics stack to solve some of society's most important problems. You will join a team dedicated to bringing Apollo to market at scale, tackling the complex challenges like safety, commercialization, and mass production to change the world for the better. JOB SUMMARY Apptronik is seeking a SimOps Engineer to architect and maintain the large-scale simulation infrastructure required for Apollo, our general-purpose humanoid robot. In this role, you will apply high-fidelity simulation rigor to humanoid robotics, managing the lifecycle of virtual environments used for locomotion, dexterous manipulation, and synthetic data collection. You will build the scalable frameworks and automated pipelines that allow our teams to perform system-level optimization and reliability analysis, ensuring that virtual testing accurately mirrors the real-world physical performance of Apollo. ESSENTIAL DUTIES AND RESPONSIBILITIES or KEY ACCOUNTABILITIES - Humanoid Simulation Frameworks: Architect and implement scalable, highly-available simulation frameworks. These should support high-fidelity humanoid dynamics, including complex joint interactions and balance controllers, while enabling domain randomization and synthetic data generation. - HPC & Cloud Orchestration: Deploy and manage High-Performance Computing (HPC) clusters (e.g., GCP, on-prem) to enable sub-24-hour turnaround for

Praktikum / Flexikum Application & Infrastructure DevOps Bonn - Friedrich-Ebert-Allee 71-77

Praktikant (m/w/d) Saalfeld, Thuringia posted: Posted 25 Days Ago

Qlik Developer Chennai, India posted: Posted 11 Days Ago

Senior Kinaxis Consultant Warszawa,Mazowieckie,Poland

Android Software Engineer (Azar) Seoul, South Korea

Manufacturing Engineer (NPI) Pittsburgh, PA Waabi, founded by AI visionary Raquel Urtasun, is the leader in Physical AI. With a world-class team, we're unlocking the next era of autonomous transportation with technology that's powering commercial autonomous trucks and robotaxis. Waabi is backed by and partners with world leaders in AI, automotive, logistics, and deep tech. With offices in Toronto, San Francisco, Dallas, and Pittsburgh, Waabi is growing quickly and looking for diverse, innovative and collaborative candidates who want to impact the world in a positive way. To learn more visit: www.waabi.ai You will... - Drive APQP Program Management at CM/Tier 1 sites, owning APQP to ensure a flawless Start of Production (SOP) and obtain PPAP deliverables. - Design for Manufacturing (DFM) & Assembly (DFA): Provide design maturity feedback during APQP Phase 2, ensuring that the hardware can be built repeatedly with the CM's specific tooling and equipment. - Support Supplier Quality Engineering (SQE) by validating that component-level PPAPs from sub-tier vendors are integrated correctly into the CM's assembly process. - Be responsible for the mechanical assembly, test, and integration of sensors, compute, and actuation systems, defining the special characteristic (SC/CC) steps for the manufacturing process. - Work closely with the software team to define, deploy, and validate End-of-Line (EOL) testers and calibration routines that confirm the "digital health" of the hardware. - Lead the development of Process PPAP deliverables, including PFMEAs, Process Flow Diagrams, Control Plans, and Work Instructions ensuring the CM has identified and mitigated all assembly-related risks with

Senior Service Engineer Jakarta,DKI Jakarta Jakarta,Indonesia

Robotics Engineer Hal Kirkop, Malta

DevOps Engineer (RMDC | Platform Operations) India - Bangalore posted: Posted 7 Days Ago