Intertek jobs
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Intern Firmware Engineer
Rockwell Automation - Katowice, PolandIndexed from Workday Benefit evidence checked May 7, 2026posted 84 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIntern Firmware Engineer Katowice, Poland posted: Posted 23 Days Ago
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Electrical Hardware Engineer
Rockwell Automation - Katowice, PolandIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedElectrical Hardware Engineer Katowice, Poland posted: Posted 30+ Days Ago
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Hardware Development Engineer
Rockwell Automation - Katowice, PolandIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedHardware Development Engineer Katowice, Poland posted: Posted 30+ Days Ago
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2026 Intern - Embedded Software Development - UWB
NXP Semiconductors - Shanghai (JingAn)Indexed from Workday Benefit evidence checked May 7, 2026posted 64 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported2026 Intern - Embedded Software Development - UWB Shanghai (JingAn) posted: Posted 3 Days Ago
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Senior Hardware Engineer
Rockwell Automation - Katowice, PolandIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Hardware Engineer Katowice, Poland posted: Posted 30+ Days Ago
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System Hardware Engineer, Nitro team
Amazon - Haifa, Haifa, ISRIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 91 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSystem Hardware Engineer, Nitro team Haifa, Haifa, ISR Annapurna Labs seeks a System HW Engineer to define, shape, and integrate solutions for the next generation of our cloud platforms. As a System Engineer on the hardware team, you will define systems for Annapurna Labs' Network Interface Card (NIC) hardware, support the development and validation of our NIC, and help bring the NIC to mass production. You'll lead the implementation of new hardware interface technologies and scale them to large-scale deployment, continuously delivering a world-class customer experience. This fast-paced, intellectually challenging position requires collaboration with technical experts, senior leaders, and multiple technology teams. Key job responsibilities • Define and design systems to support K2 cards development and manufacturing. • Define and provide feedback to the design of the K2 Smart Network Interface Card. • Work with design partners and manufacturing sites, to enable healthy mass production of the K2 card. • Analyze and debug design/manufacturing/integration issues. • Continuously assess process capabilities and innovate to simplify processes, reduce costs, and shorten the time cycle of K2 cards' development and manufacturing. • Collaborate with members of cross-functional teams, to gain knowledge and improve product design, processes, and quality. • Work with customers, to optimize the entire value stream and put together joint processes that will lead to improved time cycle and lower costs. • Willing to travel abroad one or two times a year, for a week at a time. Basic Qualifications: - At least 5 years' experience leading hardware products from design
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System Development Engineer, XFN (Cross-Border Fulfilment Network)
Amazon - Bengaluru, Karnataka, INDIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 75 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedSystem Development Engineer, XFN (Cross-Border Fulfilment Network) Bengaluru, Karnataka, IND Are you passionate about solving technical challenges? Do you thrive in a dynamic, high-impact environment? Join EU INTech's XFN (Cross-Border Fulfilment Network) team as a System Development Engineer and help us drive the growth of the XFN Program. The XFN's mission is to serve customers and accelerates the flywheel by reducing sourcing costs, increasing selection, and availability by removing country borders as a barrier between supply and demand. Formed out of the convergence of the European Fulfillment Network (EFN) and the North America Fulfillment Network (NAFN), XFN is the only program at Amazon that supports WW intra-regional retail inventory sharing across 14 stores and 3 networks (EFN, NAFN, and FEFN) in EU, NA and FE regions. As a System Development Engineer on XFN, you will join the team that supports services responsible for world-wide cross-border inventory eligibility management. You will be owning deployments, automation, scaling, and solving operations with software across our systems. This will include identifying and resolving issues, automating and improving repetitive processes, and working closely with the development team to identify operational needs. You will become intimately familiar with the architecture of our systems, and be responsible for diving deep into code, while developing solutions for our customers and services. You'll drive prioritization of operational issues, and drive automation design and scaling requirements in support of the wider organization. You will get the opportunity to work closely with a great team of software developers who will help
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Global Hardware Development Intern
Analog Devices - Philippines, Cavite, GTCIndexed from Workday Benefit evidence checked May 7, 2026posted 65 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedGlobal Hardware Development Intern Philippines, Cavite, GTC posted: Posted 4 Days Ago
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Senior Electrical Engineer – DSP ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 75 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Electrical Engineer – DSP ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
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Electronics Hardware Engineer
GE Vernova - NiskayunaIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedElectronics Hardware Engineer Niskayuna posted: Posted 30+ Days Ago
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ASIC II - AMZ9679283
Amazon - Austin, Texas, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 128 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource $136K-$184K From the posting source Equity Inferred from posting 401(k) reportedASIC II - AMZ9679283 Austin, Texas, USA MULTIPLE POSITIONS AVAILABLE Employer: ANNAPURNA LABS (U.S.) INC. Offered Position: ASIC II Job Location: Austin, Texas Job Number: AMZ9679283 Position Responsibilities: Design and validate signal and power integrity (SI/PI) systems for next generation machine learning ASICs and customized hardware platforms optimized for AWS datacenter environments. Perform both time-domain and frequency-domain simulations using tools such as HSPICE, Cadence Sigrity, HFSS, and Keysight ADS, including 3D/2.5D EMIR analysis. Apply transmission line theory and electromagnetics to develop high-speed interfaces like SerDes and PCIe, resolving complex SI issues across digital systems. Collaborate cross-functionally with silicon, packaging, board design, and validation teams to ensure system-level integrity across PCB, interposers, and advanced SoC power delivery architectures using die-level capacitors (DTC, IPD). Use high-speed lab equipment to validate and correlate simulation results, while debugging prototypes to meet stringent performance requirements. Tackle novel challenges in interconnects and power delivery for large-scale compute environments by proposing innovative, high-impact solutions. Document simulation outcomes, measurement data, and design trade-offs, presenting clear recommendations to both technical and non-technical stakeholders while fostering a culture of continuous learning and engineering excellence Position Requirements: Bachelor's degree or foreign equivalent degree in Electrical or Computer Engineering or related field and two years of experience in the job offered or related occupation. Must have one year of experience in the following skills: (1) using time domain and frequency domain tools: Hspice, Sigrity, HFSS, or Microwave Studio; (2) with PCB, Package, interposers (COWOS) and Silicon Technologies; (3) in Transmission line theory
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Senior Electrical Engineer - ASIC/FPGA Verification (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 75 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Electrical Engineer - ASIC/FPGA Verification (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
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Principal Electrical Engineer - ASIC/FPGA (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166Indexed from Workday Benefit evidence checked May 7, 2026posted 75 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Electrical Engineer - ASIC/FPGA (Onsite) US-IA-CEDAR RAPIDS-166 ~ 855 35Th St NE ~ BLDG 166 posted: Posted 14 Days Ago
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Intern – Auto Power Product Applications
Analog Devices - Italy, Milan, AssagoIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIntern – Auto Power Product Applications Italy, Milan, Assago posted: Posted 30+ Days Ago
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Internship: Electro/Thermo Migration Reliability Capabilities of IC Packages
NXP Semiconductors - NijmegenIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Entry From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedInternship: Electro/Thermo Migration Reliability Capabilities of IC Packages Nijmegen posted: Posted 30+ Days Ago
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IC SoC Product & Subsystem Architect (f/m/d)
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIC SoC Product & Subsystem Architect (f/m/d) Hamburg posted: Posted 30+ Days Ago
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IC Production Manager , Annapurna Prod Infra & Operations
Amazon - Haifa, Haifa, ISRIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026posted 108 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Operations From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk Salary not disclosed Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedIC Production Manager , Annapurna Prod Infra & Operations Haifa, Haifa, ISR We are seeking an IC Production Manager to lead semiconductor hardware operations and manage Outsourced Semiconductor Assembly and Test (OSAT) partners, as well as multiple hardware and tooling suppliers. This role is responsible for driving efficient hardware and tooling management, optimizing OSAT partnerships, and ensuring scalable, cost-effective supply across the semiconductor value chain. Key job responsibilities Hardware & Inventory Management • Develop, implement, and maintain robust inventory management systems for semiconductor hardware, including test boards, probe cards, and related equipment located at various locations around the manufacturing partners • Design and deploy digital tools to track hardware movement, utilization, availability, and maintenance schedules • Establish real-time visibility into hardware location, status, and lifecycle stage • Create and maintain hardware lifecycle management processes from deployment through end-of-life • Lead inventory audits and reconciliation activities with OSAT partners OSAT & Supplier Management • Act as the primary point of contact for day-to-day communication with OSATs and strategic suppliers • Coordinate hardware allocation, maintenance, repair, and replacement activities with OSAT partners • Oversee and monitor supplier deliveries, capacity commitments, and operational performance • Conduct supplier audits, performance reviews and scoring • Build, manage, and maintain strong working relationships with OSAT partners Commercial & Contractual Leadership • Lead commercial negotiations with strategic suppliers to improve pricing, terms, and overall cost structure. Own contract management and negotiation, including: Master Development and Supply Agreements (MDSA) Statements of Work (SOW) Product schedules and related commercial
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Principal Mixed-Signal Hardware Engineer
Medtronic - Galway, County Galway, IrelandIndexed from Workday Benefit evidence checked May 7, 2026posted 70 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 24 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Mixed-Signal Hardware Engineer Galway, County Galway, Ireland posted: Posted 9 Days Ago
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Senior FPGA/ASIC Design /Verification Engineer (Onsite)
Raytheon Technologies - US-IA-CEDAR RAPIDS-193 ~ 1120 Collins Rd NE ~ BLDG193Indexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Onsite - 5d office From the posting source Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior FPGA/ASIC Design /Verification Engineer (Onsite) US-IA-CEDAR RAPIDS-193 ~ 1120 Collins Rd NE ~ BLDG193 posted: Posted 30+ Days Ago
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Staff Mixed Signal IC Designer
Analog Devices - United Kingdom, Edinburgh, SC, FreerIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Design From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedStaff Mixed Signal IC Designer United Kingdom, Edinburgh, SC, Freer posted: Posted 30+ Days Ago
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Controls Hardware Engineer
GE Vernova - StaffordIndexed from Workday Benefit evidence checked May 7, 2026posted 91 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedControls Hardware Engineer Stafford posted: Posted 30 Days Ago
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Systems Integration Engineering
Analog Devices - Ireland, LimerickIndexed from Workday Benefit evidence checked May 7, 2026posted 92 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSystems Integration Engineering Ireland, Limerick posted: Posted 30+ Days Ago
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Senior FPGA Engineer
GE Vernova - StaffordIndexed from Workday Benefit evidence checked May 7, 2026posted 72 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior FPGA Engineer Stafford posted: Posted 11 Days Ago
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Principal Hardware Engineer
Raytheon Technologies - Glenrothes, FifeIndexed from Workday Benefit evidence checked May 7, 2026posted 91 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 4 wksource Resolvable source Verified non-birth-parent leave: 4 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Hardware Engineer Glenrothes, Fife posted: Posted 30 Days Ago
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