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Stagiaire Implémentation, test et validation d’une fonction de détection de défaut de non-conduction d’un bras de pont (H/F)
GE Vernova - BelfortIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 10 wksource Resolvable source Verified non-birth-parent leave: 10 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedStagiaire Implémentation, test et validation d’une fonction de détection de défaut de non-conduction d’un bras de pont (H/F) Belfort posted: Posted 30+ Days Ago
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Validation Engineer (Quantifi Photonics, New Zealand)
Teradyne - Validation Engineer (Quantifi Photonics, New Zealand)Indexed from Successfactors Benefit evidence checked May 7, 2026posted 65 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Inferred from posting Verified parental leave: 4 wk Inferred from posting Verified non-birth-parent leave: 4 wk Salary not disclosed Inferred from posting Childcare support EquityValidation Engineer (Quantifi Photonics, New Zealand) Validation Engineer (Quantifi Photonics, New Zealand) Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. Based in Auckland, Quantifi Photonics is proud to be part of the Teradyne family, combining New Zealand's innovative spirit with the resources of a global leader in test, automation, and robotics. We're growing fast, tackling increasingly complex challenges, and are looking for passionate, talented people to help take Quantifi Photonics to the next level. Quantifi Photonics designs and manufactures advanced optical and electronic test instruments that enable engineers to develop and scale up next-generation photonics technologies. Our customers include global tech companies, leading universities, and world-class research institutions in over 25 countries; working across R&D, high-volume manufacturing, defence, aerospace, and academia. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results . Opportunity Overview The Validation Engineer supports New Product Introduction (NPI) programs by executing product validation and verification activities in accordance with established company procedures and engineering standards.
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Principal Digital IP Verification Engineer (f/m/d)
NXP Semiconductors - MunichIndexed from Workday Benefit evidence checked May 7, 2026posted 66 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Digital IP Verification Engineer (f/m/d) Munich posted: Posted Yesterday
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(Senior) RF Engineer Test & Validation (f/m/d)
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reported(Senior) RF Engineer Test & Validation (f/m/d) Hamburg posted: Posted 30+ Days Ago
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Working Student (f/m/d) RF Validation and Lab Automation
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 95 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedWorking Student (f/m/d) RF Validation and Lab Automation Hamburg posted: Posted 30 Days Ago
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Senior NVM Validation Engineer
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 68 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior NVM Validation Engineer Austin (Oakhill, Office) posted: Posted 3 Days Ago
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HW Validation Engineer
NXP Semiconductors - Austin (Oakhill, Office)Indexed from Workday Benefit evidence checked May 7, 2026posted 91 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedHW Validation Engineer Austin (Oakhill, Office) posted: Posted 26 Days Ago
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Distinguished AI/ML Architect (Cortex)
CyberArk - Office - Israel - Tel AvivIndexed from Workday Benefit evidence checked Jun 7, 2026posted 73 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Inferred from posting 401(k) reportedDistinguished AI/ML Architect (Cortex) Office - Israel - Tel Aviv posted: Posted 8 Days Ago
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Sr./Lead FW Verification and Validation Engineer
NXP Semiconductors - BangaloreIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSr./Lead FW Verification and Validation Engineer Bangalore posted: Posted 30+ Days Ago
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Senior Validation Engineer (f/m/d)
NXP Semiconductors - HamburgIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Validation Engineer (f/m/d) Hamburg posted: Posted 30+ Days Ago
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Senior Angular Frontend Engineer - Identity Security (Cortex)
CyberArk - Office - Israel - Tel AvivIndexed from Workday Benefit evidence checked Jun 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Inferred from posting 401(k) reportedSenior Angular Frontend Engineer - Identity Security (Cortex) Office - Israel - Tel Aviv posted: Posted 30+ Days Ago
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Senior UX Designer - Agentic Endpoint Security(Cortex)
CyberArk - Office - Israel - Tel AvivIndexed from Workday Benefit evidence checked Jun 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Design From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Inferred from posting 401(k) reportedSenior UX Designer - Agentic Endpoint Security(Cortex) Office - Israel - Tel Aviv posted: Posted 30+ Days Ago
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Senior / Principle Security Research - Agent ML Team (Cortex)
CyberArk - Office - Israel - Tel AvivIndexed from Workday Benefit evidence checked Jun 7, 2026posted 66 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Inferred from posting 401(k) reportedSenior / Principle Security Research - Agent ML Team (Cortex) Office - Israel - Tel Aviv posted: Posted Yesterday
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Optical Thin Film Coating Material Engineer
Google - New Taipei, Banqiao District, New Taipei City, TaiwanIndexed from Google Custom Benefit evidence checked May 7, 2026posted 72 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedOptical Thin Film Coating Material Engineer New Taipei, Banqiao District, New Taipei City, Taiwan Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology. Lead the development of thin optical coating stacks at vendors, ensuring consistent performance and design across multiple suppliers. Manage material DOEs, analyze test results, and select the best materials for applications such as lens covers and display glass. Collaborate with process engineers, FEA, product designers, industrial designers, and reliability teams on material qualification and product-level testing. Solve mission-critical issues related to coatings to ensure high-quality standards for mass production. Minimum qualifications: Bachelor's degree in Materials Science, Mechanical Engineering, or a related technical field, or equivalent practical experience. 5 years of experience in working with optical coatings, Physical Vapor Deposition (PVD), and material integration. Preferred qualifications: Master's degree or PhD in Physics, Optical Sciences, Material Science or related fields. Experience leading cross-functional efforts, influencing program roadmaps via data-driven insights, driving technical initiatives impacting multiple products, and mentoring junior engineers while growing the technical excellence of multidisciplinary teams. Experience working
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IC & System Validation Engineer F/M
NXP Semiconductors - CaenIndexed from Workday Benefit evidence checked May 7, 2026posted 87 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIC & System Validation Engineer F/M Caen posted: Posted 22 Days Ago
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IC Design Verification Engineer
NXP Semiconductors - KanataIndexed from Workday Benefit evidence checked May 7, 2026posted 68 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIC Design Verification Engineer Kanata posted: Posted 3 Days Ago
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Principal Digital Validation Engineer
NXP Semiconductors - PuneIndexed from Workday Benefit evidence checked May 7, 2026posted 83 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedPrincipal Digital Validation Engineer Pune posted: Posted 18 Days Ago
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Senior Principal Engineer, Analog Validation/Characterization
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 89 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Principal Engineer, Analog Validation/Characterization Noida posted: Posted 24 Days Ago
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IC Design Verification Engineer
NXP Semiconductors - KanataIndexed from Workday Benefit evidence checked May 7, 2026posted 67 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedIC Design Verification Engineer Kanata posted: Posted 2 Days Ago
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High-Speed Interface Validation Engineer, Post Silicon Validation
Amazon - Austin, Texas, USAIndexed from Amazon Custom Benefit evidence checked Jun 7, 2026 Comp disclosed in postingposted 79 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Inferred from posting Verified non-birth-parent leave: 6 wk $144K-$194K From the posting source Inferred from posting Adoption assistance Inferred from posting Childcare support Inferred from posting Fertility benefits Inferred from posting Mental health support Equity Inferred from posting 401(k) reportedHigh-Speed Interface Validation Engineer, Post Silicon Validation Austin, Texas, USA Annapurna Labs, an AWS organization with development centers in the U.S. and Israel, builds custom silicon and software for AWS customers. Our team combines cloud-scale innovation with world-class expertise across silicon engineering, hardware design, verification, software, and operations to tackle technical challenges that have never been seen before. Join our Post-Silicon Validation team to validate the critical high-speed interconnects - HBM, PCIe, UCIe, and chip-to-chip links - that enable massive bandwidth and scaling in AWS's next-generation ML accelerators. You'll ensure link integrity, performance, and reliability at the electrical and protocol layers across the full product lifecycle, from first silicon through production deployment in AWS data centers. You'll work in a fast-paced, startup-like environment alongside some of the brightest minds in the industry on next generation, internet-scale technology that directly impacts how customers use Machine Learning acceleration. Your expertise will be instrumental in validating the I/O technologies that enable our custom silicon to scale beyond what was previously possible. Key job responsibilities Validate high-speed interfaces (HBM, PCIe, UCIe, custom SerDes) end-to-end from PHY training through sustained traffic Perform electrical characterization: eye diagrams, jitter analysis, voltage margin, and equalization tuning Execute protocol-level compliance testing and interoperability validation against industry specifications Stress-test links across PVT (Process, Voltage, Temperature) corners and aging conditions Debug link training failures, bit errors, and performance degradation using lab instrumentation and silicon debug features Collaborate with PHY design teams on equalization optimization, margin improvement, and silicon feedback A day
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Senior Validation Engineer
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Senior From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Validation Engineer Noida posted: Posted 30+ Days Ago
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Senior Principal Validation Engineer
NXP Semiconductors - NoidaIndexed from Workday Benefit evidence checked May 7, 2026posted 89 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Data From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior Principal Validation Engineer Noida posted: Posted 24 Days Ago
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SW TEST/VALIDATION
NXP Semiconductors - PuneIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Other - Mid From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSW TEST/VALIDATION Pune posted: Posted 30+ Days Ago
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Senior / Principal Validation Leader
NXP Semiconductors - ToulouseIndexed from Workday Benefit evidence checked May 7, 2026posted 96 days agoWhy we showed this
Title: semantic matchRole: semantic match+1
Unspecified Engineering From the posting source - Staff Plus From the posting source Resolvable source Verified parental leave: 6 wksource Resolvable source Verified non-birth-parent leave: 6 wksource Salary not disclosed Equity Inferred from posting 401(k) reportedSenior / Principal Validation Leader Toulouse posted: Posted 30+ Days Ago
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