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  • CPU Performance Architect, Platform Architecture

    Apple - Austin, United States of America
    Indexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in posting
    posted 154 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Staff Plus From the posting source $191K-$286K From the posting source Equity Inferred from posting 401(k) reported

    CPU Performance Architect, Platform Architecture Austin, United States of America The CPU Platform Architecture team is responsible for pushing the boundaries of both single-threaded and multi-threaded CPU performance, to enhance the user experience of many Apple products. The team is composed of experts with deep experience in microarchitecture, ISA definition, performance modeling, power modeling, and workload analysis. We are seeking a highly motivated, innovative, and confident individual to join the CPU Platform Architecture team to help drive advanced exploration for next-generation iPhone, iPad, Mac, and server CPU designs. As a CPU Performance Architect with a focus on the memory subsystem, you will be part of a team that is defining and optimizing CPU and cache micro-architecture. Working collaboratively, you will seek out areas of the design for improvement by identifying performance bottlenecks and evaluate ideas to address them. You will engage with experienced CPU and SoC designers in micro-architecture and RTL to assess the feasibility of ideas through modeling, refine ideas and model correlation, and seed new ideas. The role requires the analysis of single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance team to maintain and improve the simulation environment to enable data-driven decisions and always look for ways to boost the productivity of the entire team. Minimum Qualifications: BS degree Experience in CPU and SOC architecture and micro-architecture Experience with performance simulation environments Object-oriented programming experience in C/C++ Experience in a

  • System Validation Engineer

    Intel - Israel, Haifa
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    System Validation Engineer Israel, Haifa posted: Posted 30+ Days Ago

  • Hardware Architect, Deep Learning GPU and System

    NVIDIA Corporation - Israel, Yokneam
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Hardware Architect, Deep Learning GPU and System Israel, Yokneam posted: Posted 30+ Days Ago

  • Project Controls Engineer

    Intel - 3 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Project Controls Engineer 3 Locations posted: Posted 30+ Days Ago

  • Roadmap Pricing Manager

    Intel - 4 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Finance From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Roadmap Pricing Manager 4 Locations posted: Posted 30+ Days Ago

  • Principal Edge AI Runtime & Compiler Engineer

    Ambiq Micro INC - Austin, Texas, United States
    Indexed from Greenhouse Benefit evidence checked Jun 13, 2026
    posted 207 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    +1
    Unspecified Teaching Education From the posting source - Principal From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Principal Edge AI Runtime & Compiler Engineer Austin, Texas, United States Company Overview Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 290 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us - the intelligence everywhere revolution starts here. Scope Ambiq is seeking a Principal Edge AI Runtime & Compiler Engineer to build and optimize the embedded software stack that powers real-time, battery-powered on-device AI. You will develop Ambiq's AI runtimes, performance-critical operator libraries, and profiling/debug tooling that enable customers to deploy efficient inference on resource-constrained devices. While the cloud has been the default home for AI, the next frontier is distributing intelligence everywhere-directly onto real-world devices. Edge AI enables real-time responsiveness, stronger privacy, lower bandwidth cost, and reliable operation even without connectivity. This role helps accelerate

  • Solution Architect - Telco

    Intel - Virtual India
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 117 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Solution Architect - Telco Virtual India posted: Posted 8 Days Ago

  • Senior AI Chip Design Engineer

    NVIDIA Corporation - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior AI Chip Design Engineer 2 Locations posted: Posted 30+ Days Ago

  • AMS Verification Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    AMS Verification Engineer India, Bangalore posted: Posted 30+ Days Ago

  • Principal Engineer, Inference Cloud

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026
    posted 365 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Principal From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Principal Engineer, Inference Cloud Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Location: Sunnyvale We're hiring a Principal Engineer for our Inference Cloud Platform. This team owns the cloud layer behind our Inference Service, including availability, latency, reliability, and multi-region scale. This is one of the most senior IC roles on the team, for someone who can identify the highest-leverage platform problems, set direction across multiple teams, define long-term architecture, and write production code on critical paths. Many of the key decisions are ambiguous at the outset; you'll need to frame the problem, make tradeoffs, and drive execution

  • Power Delivery Design Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 110 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Power Delivery Design Engineer India, Bangalore posted: Posted Yesterday

  • Chip Design Team Lead - AI SOC

    Intel - Israel, Petah-Tikva
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"Role: semantic match
    Unspecified Marketing From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Chip Design Team Lead - AI SOC Israel, Petah-Tikva posted: Posted 30+ Days Ago

  • Electrical Engineer

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 222 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source $150K-$260K From the posting source Equity Inferred from posting 401(k) reported

    Electrical Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Responsibilities - Lead printed circuit board design through all development stages: from definition to implementation, bring-up, qualification, and production release. - Full responsibility for electrical specification, schematic design, components selection, and layout considerations. - Extensive lab bring-up and debugging, including developing automated benchtop setups for board characterization. - Collaborate with various design and operations teams: manufacturing operations & test engineering, supply chain, ASIC, mechanical, signal integrity, power delivery, layout, embedded & diagnostic, etc. Skills & Qualifications - B.S.c, M.S.c, or Ph.D. degree in electrical engineering, or equivalent experience.

  • Analog Design Engineer

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 112 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Analog Design Engineer 2 Locations posted: Posted 3 Days Ago

  • Senior Quality Engineer

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 152 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Senior From the posting source $175K-$275K From the posting source Equity Inferred from posting 401(k) reported

    Senior Quality Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About the Role: We are looking for a hands-on Senior Quality Engineer to drive manufacturing quality for printed circuit board assemblies (PCBAs), subassemblies, and system-level products across our contract manufacturers and suppliers. This role is responsible for ensuring robust manufacturing processes, superior workmanship, high production yields, and effective corrective actions throughout the product lifecycle. The ideal candidate brings deep expertise in SMT manufacturing, IPC standards, electronics assembly processes, and statistical quality methods. Working closely with Manufacturing Engineering, Supplier Quality, Reliability Engineering, Design Engineering, and contract manufacturers, you

  • Construction Project Manager

    Intel - Malaysia, Kulim
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 130 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Operations From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Construction Project Manager Malaysia, Kulim posted: Posted 21 Days Ago

  • Prognostics & Health Monitoring Engineer

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026 Comp disclosed in posting
    posted 152 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source $150K-$250K From the posting source Equity Inferred from posting 401(k) reported

    Prognostics & Health Monitoring Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Role Summary Quality, reliability, and uptime are foundational to scaling Cerebras systems. We are seeking an engineer to define and build our prognostics and health monitoring (PHM) capability-developing frameworks to monitor, assess, and predict hardware health across our fleet. In this role, you will transform telemetry and operational data into actionable insights and automated responses, enabling early detection of degradation, accurate failure prediction, and proactive actions to keep systems highly available, performant, and resilient. This is a highly cross-functional role spanning reliability engineering, data science,

  • Ethernet Product Manager

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 120 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Product From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Ethernet Product Manager 2 Locations posted: Posted 11 Days Ago

  • Senior Staff Mixed Signal IP Enablement and Debug Engineer

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 120 days ago

    Why we showed this

    Employer: "intel"Role: semantic match
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Staff Mixed Signal IP Enablement and Debug Engineer 2 Locations posted: Posted 11 Days Ago

  • Manufacturing Operators (Contract)

    Intel - Malaysia, Penang
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 129 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Operations From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Manufacturing Operators (Contract) Malaysia, Penang posted: Posted 20 Days Ago

  • CPU Structural Design – Technology and Path finding

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"Role: semantic match
    Unspecified Product From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    CPU Structural Design – Technology and Path finding 2 Locations posted: Posted 30+ Days Ago

  • Design Verification Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Design Verification Engineer India, Bangalore posted: Posted 30+ Days Ago

  • Robotics/Physical AI Sales

    Intel - Japan, Tokyo
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 116 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Sales From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Robotics/Physical AI Sales Japan, Tokyo posted: Posted 7 Days Ago

  • Senior Mixed Signal IP Enablement and Debug Engineer

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 120 days ago

    Why we showed this

    Employer: "intel"Role: semantic match
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Mixed Signal IP Enablement and Debug Engineer 2 Locations posted: Posted 11 Days Ago

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