Astera Labs jobs

Lead Product Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Tech Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production. As a key technical contributor, you will own the RF and signal integrity aspects of product engineering - from silicon characterization and validation through production test development and customer-facing debug. You'll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution. With Astera Labs' portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance,

Principal Test Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. Basic Qualifications - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred. - ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing. - Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc. - Professional attitude with ability to execute on multiple tasks with minimal supervision. - Strong team player with good communication skills to

Sr. Principal Product Marketer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal, Product Marketing to serve as the strategic marketing leader for our Leo Smart Memory Extender product line - the industry's most advanced CXL-based solution enabling memory expansion and disaggregation for AI and cloud infrastructure at rack scale. This is a senior individual contributor role with outsized influence, where you'll define how the market understands, evaluates, and adopts CXL memory technology. As AI models scale to hundreds of billions of parameters and memory capacity becomes the defining bottleneck in modern data centers, Leo is uniquely positioned to unlock new levels of performance and efficiency. In this role, you'll operate as the authoritative voice of the Leo product line - shaping narratives that influence hyperscaler architecture decisions, driving industry thought leadership, and partnering with Astera Labs' most senior technical and business leaders to accelerate market creation. This is a

Senior Firmware Engineer - PCIe/CXL Memory Solutions San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking experienced Senior Firmware Engineer PCIe/CXL Memory Solution to lead the design and development of embedded firmware for cutting-edge PCIe/CXL memory expansion products tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite. Required Experience: - Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field. - 5+ years of hands-on experience in embedded firmware development using C. - Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation. - Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C. - Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P. Key Responsibilities & Skills: - Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at

Principal AEC / AOC Program Manager Suzhou Qu, Gansu, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs Principal AEC / AOC Program Manager you will play a crucial role in overseeing the planning, coordination, and execution of manufacturing projects featuring Astera Labs' AEC / AOC portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. You will ensure that production processes run smoothly, meet quality standards, and are completed on time and within budget and responsible for manufacturing from NPI to mass production phases. To accomplish that, you will be working closely with designers, the manufacturing team, suppliers, and contract manufacturers. This role is expected to travel up to 30% of the year and will require business English skills. Job Responsibilities - Project Planning and Execution - Develop Project Plans: Create detailed project plans, including schedules, budgets, resource allocation, and timelines. - Coordinate Production Activities: Oversee all aspects of the manufacturing process,

Director Product Marketing - Signal Connectivity Products San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Director of Product Marketing to lead go-to-market strategy for our industry-leading connectivity solutions . This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our PCIe signal conditioning products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate deep technical capabilities into compelling value propositions that resonate with technical decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the

Senior Principal Engineering Program Manager San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale. Key Responsibilities - Program Ownership & Execution - Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM - Serve as the single point of ownership for assigned ASIC programs - Drive program planning, schedules, budgets, resources, and risk management - Cross-Functional Leadership & Issue Resolution - Lead cross-functional teams across design, validation, product, test, firmware, software, and operations - Resolve complex pre-silicon and post-silicon issues through strong technical judgment - Stakeholder Management & Alignment - Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders - Champion program execution while aligning engineering

Principal Physical Design Engineer, STA San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person. Key Responsibilities - Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. - Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis. - Define and manage I/O timing budgets across hierarchical designs. - Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects. - Leverage ETM libraries for hierarchical timing analysis and correlation,

Principal Digital Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers. Key Responsibilities - Design Ownership & Execution - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design

Physical Design/CAD Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key Responsibilities - As Physical Design CAD Engineer you will support and build flows for world class EDA tools. - Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. - Architect and recommend flow improvements and enhance existing methodology for high performance design. - Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. - Work with cross function teams to define requirements and specifications

Staff/ Principal Design Verification Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Staff/ Principal Design Verification Engineer , you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the

Technical Lead Digital Design Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers. Key Responsibilities - Design Ownership & Execution - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT)

Analog/Mixed-Signal IC Design India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment.

Senior Principal Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: As a Senior Principal Validation Engineer , you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets. You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction. This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives

Senior/ Staff Physical Design CAD Engineer - Automation & Signoff Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team. Key Responsibilities - Develop and

Principal Product Manager - Ethernet San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions. This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, this position requires an in-person presence with travel to customers. Key Responsibilities - Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based

FP&A Business Unit Controller San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview As a FP&A Business Unit Controller you will be primarily responsible for managing the business partnering relationships for the R&D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective. Primary Responsibilities - Establish strong partnership with leadership to help business owners manage their business effectively - Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning - Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics - Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making - Collaborate with Corporate Finance on various projects as needed - Provide

Finance and Administration Intern (Part-Time, Germany 2026) Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Support the finance team across accounting, procurement, financial planning, and process improvement in an international environment. Key Responsibilities - Process invoices, create POs, and support vendor onboarding - Support OPEX planning and analyze production cost structures - Contribute to financial analysis and planning activities - Assist ERP migration and improve processes - Support automation initiatives (e.g., Power Automate, AI tools) Your Profile - Student in Finance, Accounting, Business, or similar - Strong analytical skills and attention to detail - Structured, reliable, and proactive way of working - Quick learner with ability to work independently - Good Excel skills; ERP/automation tools are a plus - Fluent in English and German We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents,

Director of Product Engineering San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes. As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle - from characterization and qualification through production ramp and sustaining - across our portfolio of purpose-built connectivity solutions enabling rack-scale AI. This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to

Principal Package Signal & Power Integrity San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems. In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule. You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip-package-board co-design frameworks to enable scalable execution across

Chip Lead, Senior Director San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. Location - San Jose, CA OR Israel Key Responsibilities - Product Technical Ownership - Own the full technical lifecycle of the product line-architecture assumptions, design integration, validation

Lead HVM Product Engineer Taipei,Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives. Basic qualifications: · Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation) · Experience in working with PCIe Gen3 and above · Have gone through at least

Senior/ Staff Physical Design STA Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities - Execute the STA flow and sign-off methodologies, ensuring our

Senior/ Staff Front-End CAD Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up. As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won't just be using tools; you'll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors. Key Responsibilities - Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes - Create robust applications using Python and Tcl to automate models build, regression and analysis tools and