Intel jobs

CPU–SoC Mask Layout Designer (Diploma Level Contract role) - Silicon Engineering Group (SiG) 2 Locations posted: Posted 30+ Days Ago

CPU Performance Developer Technology Engineer 3 Locations posted: Posted 2 Days Ago

Mask Manufacturing Technician US, Oregon, Hillsboro posted: Posted 11 Days Ago

PERC ESD EDA Engineer 4 Locations posted: Posted 2 Days Ago

Staff/Sr. ML Compute Efficiency Engineer Santa Clara, United States of America Scaling machine learning workloads across thousands of GPUs and TPUs creates challenges that few engineers ever encounter. In Apple's Machine Learning Platform Technologies organization, we build the infrastructure that powers large-scale ML training and inference workloads, bringing together expertise in distributed systems, machine learning infrastructure, and high-performance computing. As a performance engineer in the ML Compute Efficiency team, you'll tackle ambiguous systems challenges, identify inefficiencies and build solutions that maximize accelerator utilization, reduce idle and fragmented capacity, and minimize recovery periods. This includes analyzing accelerator performance, digging into various parallelism techniques, and refining workload scheduling and orchestration across the compute fleet. Characterize ML workload behavior through profiling, benchmarks and metrics. Dive into unfamiliar codebases to prototype changes, evaluate tradeoffs, and build production-ready solutions. Design systems for efficient recovery from failures and preemptions. Create tools to identify and alert bottlenecks across applications and frameworks. Use workload-driven insights to influence next-generation hardware selection and procurement decisions. Collaborate closely with ML researchers and infrastructure engineers to address inefficiencies. Drive impact through hands-on contribution and mentorship. Minimum Qualifications: Experience with large-scale distributed systems for AI/ML workloads running on GPUs or TPUs. Strong software engineering skills with experience developing and optimizing training frameworks (e.g. PyTorch, JAX) using C/C++ or Python. Experience working on cross-functional projects with ML research and infrastructure teams. Familiarity with model architectures and various training techniques. Bachelor's degree in Computer Science or equivalent experience, with 7+ years of industry experience. Preferred

Business Intel Engineer, GO-AI Hyderabad, Telangana, IND Amazon Robotics is at the forefront of applying state-of-the-art artificial intelligence to solve real-world challenges at unprecedented scale. Our fulfillment centers handle more individual items than any company in the world, combining computer vision, mobile robots, advanced end-of-arm tooling, and high-degree of freedom movement with state-of-the-art AI. We collaborate with customers across Amazon worldwide to conceive, develop, prototype, and deploy intelligent robotic systems that push the boundaries of industrial automation. Within Amazon Robotics, the Global Operations - Artificial Intelligence (GO-AI) team enables Amazon to accelerate and scale the next generation of AI-powered robotic solutions. We're transforming how complex visual reasoning tasks are performed across Amazon's robotics operations, moving from traditional manual data annotation processes to state-of-the-art foundation model solutions. As a Business Intelligence Engineer on GO-AI's Technology & Development Team, you'll work with cross-functional teams (Science, Software, Data, BIE) managing massive-scale, proprietary datasets to develop foundation models that achieve human-level performance on complex real-world tasks. Your work will directly impact millions of daily operations across Amazon's global fulfillment network. This is a rare opportunity to work with a team building AI systems that operate at Amazon scale while solving novel technical challenges in computer vision, natural language processing, and human-AI collaboration. You'll collaborate with world-class scientists, engineers, and operations teams to deploy state-of-the-art research into production systems that deliver real-world impact at global scale. Key job responsibilities • Support leadership decision-making by deep-diving into business hypotheses and anecdotes. • Design and automate ETL

Strategic Hardware Partnerships San Francisco, California, United States About the Role We are a small, fast-moving partnerships team that shapes and executes OpenAI's most strategic collaborations. In this role, you will own the end-to-end hardware partnership strategy and portfolio spanning silicon, systems, and manufacturing partners that make our product roadmap real. You will build deep relationships, set and ensure we have the right joint strategy and programs in place, lead cross-functional workstreams, and iterate on complex deals to break new ground and advance OpenAI's most ambitious hardware programs. You are a seasoned leader with deep experience in complex hardware ecosystems, comfortable operating amid ambiguity, and capable of driving alignment across executives, boards, and partners while simultaneously pushing critical programs to delivery. You have a background working closely with product and engineering leaders and expertise in strategic hardware and systems supply deals. You're able to drive work at high velocity and can motivate external and internal partners including product, engineering, sales, finance, legal and operations. Key Responsibilities: - Own strategic hardware partner relationships end-to-end. Be the primary point of contact internally and externally for OpenAI's most important strategic hardware partners. - Define and drive joint strategy and roadmap alignment. Translate product and engineering priorities into partner roadmaps, milestones, and decision points (requirements, capacity, cost targets, reliability, and timelines). - Technical diligence and partner strategy. Evaluate build/buy/partner options, understand where advantages/risks sit, and provide clear recommendations grounded in technical and business analysis (silicon, connectivity, systems, device HW/SW stack, OS, etc.). - Structure

Reliability/DFX Engineer San Francisco, California, United States About the Team OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI-native silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We are seeking a highly skilled cross-stack engineer with deep expertise in making ML systems reliable at scale. This hands-on individual contributor will sit within our hardware team and work closely with chip design, platform design, hardware health, and the broader industry ecosystem to architect, implement, and deploy reliable next-generation AI accelerator systems. This engineer will evaluate system and chip architecture holistically, identify high-ROI opportunities to improve reliability and availability across the stack, and translate those opportunities into strategy and silicon features. In this role, you will: - Oversee DFX architecture, implementation, and execution in silicon from concept to high-volume deployment, and propose high-ROI features to enhance reliability and fault tolerance. DFX includes design for testability, reliability, availability, and serviceability of high-performance AI hardware. - Build system-level reliability models grounded in empirical data to guide organization-wide DFX and reliability strategy. This requires a detailed understanding of chip and system architecture, design, implementation, and component-level reliability. - Collaborate with chip and platform architecture/design teams

PFG Processor Ellisville, Missouri, USA, 63021

Senior Silicon Design Engineer Malaysia, Penang posted: Posted 30+ Days Ago

Design Verification Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Key Responsibilities - Work with architects, designers, post-silicon, and software engineers, to ensure a high-quality design that works for silicon. - Develop and implement verification strategies, detailed tests, and coverage plans based on micro-architecture. - Create verification methodologies and reusable environments, including components such as stimulus, checkers, assertions, and coverage. - Implement tests, manage regressions, gather coverage, and debug test failures. - Collaborate with cross-functional teams, including architecture, RTL design, physical design, firmware, and validation. - Analyze and debug complex issues across simulation, emulation, and silicon bring-up

Cloud and AI System Intern PRC, Shanghai posted: Posted 30+ Days Ago

Silicon Design Verification Engineer India, Bangalore posted: Posted 3 Days Ago

AI Framework Software Engineer PRC, Shanghai posted: Posted 7 Days Ago

Senior Developer Technology Engineer, CPU Performance 3 Locations posted: Posted 30+ Days Ago

EDA Tools Software Engineer Malaysia, Penang posted: Posted 28 Days Ago

Senior AI Performance and Efficiency Engineer 4 Locations posted: Posted 30+ Days Ago

Senior System Software Engineer, CPU 2 Locations posted: Posted 7 Days Ago

SerDes Circuit Design Engineer India, Bangalore posted: Posted 30+ Days Ago

CPU Processor Power Management Verification Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be at the center of a chip design effort collaborating with many teams, with a critical impact on getting functional products to millions of customers quickly. We are looking for a strong candidate to join our processor verification team focusing on Power Management and Clock Control verification. As a CPU Processor Power Management Verification Engineer, you will have the responsibilities as follows: • Work closely with architecture and RTL designers on verifying the functionality correctness of the Power Management and Clock Control logic • Develop and execute test plans and schedules for the power management and clock control logic • Develop tests in Assembly, Scripts, System Verilog, or vectors according to test plans to drive testing in simulation and emulation environments • Root

Senior Analog Design Engineer 2 Locations posted: Posted 3 Days Ago

Senior Executive Compensation Analyst 6 Locations posted: Posted 24 Days Ago

Senior Chip Design Verification Engineer Israel, Tel Aviv posted: Posted 30+ Days Ago

Tool Install Project Manager Malaysia, Penang posted: Posted 2 Days Ago