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Intel jobs

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  • IP RTL Design Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 135 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    IP RTL Design Engineer India, Bangalore posted: Posted 23 Days Ago

  • Connectivity Systems Validation Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 115 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Connectivity Systems Validation Engineer India, Bangalore posted: Posted 3 Days Ago

  • Head of Data Center Acquisition

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026
    posted 146 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Head of Data Center Acquisition Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Why now Demand for Cerebras inference is high and climbing. We need ever-more power-ready data center capacity to meet demand for the world's fastest inference solution. Project facts often change as providers work through power, site, capital, design, security, and schedule issues. This work shapes customer delivery, capital use, and risk for years. The job demands a hands-on deal leader who can separate real capacity from optimistic claims and keep priority transactions on track. Role at a glance - Own the data center capacity pipeline

  • GenAI Software Solutions Engineer

    Intel - Malaysia, Penang
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 133 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    GenAI Software Solutions Engineer Malaysia, Penang posted: Posted 21 Days Ago

  • End to End GPU AI Software Architect

    Intel - 4 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Employer: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    End to End GPU AI Software Architect 4 Locations posted: Posted 30+ Days Ago

  • Sr Test Engineer

    Intel - US, Arizona, Phoenix
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Sr Test Engineer US, Arizona, Phoenix posted: Posted 30+ Days Ago

  • Static Timing Analysis Engineer

    Intel - Israel, Haifa
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Static Timing Analysis Engineer Israel, Haifa posted: Posted 30+ Days Ago

  • Principal FPGA/ASIC Engineer - Level 3

    Northrop Grumman Corporation - United States-Arizona-Gilbert
    Indexed from Eightfold Benefit evidence checked Jun 7, 2026
    posted 112 days ago

    Why we showed this

    Role: semantic match
    Unspecified Data From the posting source - Staff Plus From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Principal FPGA/ASIC Engineer - Level 3 United States-Arizona-Gilbert

  • TEG Module Equipment Engineer

    Intel - Malaysia, Penang
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 140 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    TEG Module Equipment Engineer Malaysia, Penang posted: Posted 28 Days Ago

  • Software Enabling and Optimization Engineer

    Intel - Mexico, Guadalajara
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 120 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Software Enabling and Optimization Engineer Mexico, Guadalajara posted: Posted 8 Days Ago

  • Director / Senior Director, Critical Facility Operations

    Cerebras Systems - Sunnyvale, CA
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026
    posted 121 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Operations From the posting source - Director Plus From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Director / Senior Director, Critical Facility Operations Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. The Role At Cerebras, we build systems that redefine the scale of compute. That ambition extends beyond silicon into the infrastructure that powers it. We are looking for a Director / Sr. Director of Critical Facility Operations to lead the environments that enable next-generation AI workloads. This leader will own availability, operational integrity, and performance across a colocation-driven data center footprint-ensuring our infrastructure operates with precision, predictability, and zero room for error. This is not a traditional facilities role. You will operate at

  • CPU Global Design Lead, Silicon

    Google - Austin, TX, USA
    Indexed from Google Custom Benefit evidence checked May 7, 2026 Comp disclosed in posting
    posted 118 days ago

    Why we showed this

    Role: semantic match
    Unspecified Design From the posting source - Senior From the posting source Resolvable source Verified parental leave: 18 wksource Resolvable source Verified non-birth-parent leave: 18 wksource $240K-$334K From the posting source Equity Inferred from posting 401(k) reported

    CPU Global Design Lead, Silicon Austin, TX, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $240000 - $334000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next generation CPU. Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality. Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals. Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation

  • Foundry Customer Device Engineer

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Foundry Customer Device Engineer 2 Locations posted: Posted 30+ Days Ago

  • AI Software Validation Intern

    Intel - Poland, Gdansk
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 119 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Engineering From the posting source - Entry From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    AI Software Validation Intern Poland, Gdansk posted: Posted 7 Days Ago

  • Embedded CPU Engineer, Platform Architecture

    Apple - Beaverton, United States of America
    Indexed from Apple Custom Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Embedded CPU Engineer, Platform Architecture Beaverton, United States of America We are seeking a highly motivated and innovative Embedded CPU Engineer to join the Platform Architecture team. In this role, you will drive performance and efficiency optimization and architectural feature exploration for Apple's embedded CPUs that power critical functions across Apple's product line. As an Embedded CPU Engineer, you will help define CPUs that are specifically designed for running embedded applications across iPhone, iPad, Mac, and other Apple products. Your focus will be on understanding the unique constraints and opportunities of varied embedded use cases and translating those insights into improvements for both the software stack as well as the hardware including the CPU and its surrounding subsystem. You will be responsible for deep-dive performance analysis of embedded workloads, identifying bottlenecks in existing microarchitectures, and proposing optimization strategies that balance performance, power efficiency, and area. Working closely with algorithm teams, software engineers, and CPU designers, you will explore ISA extensions, microarchitecture enhancements, and system-level optimizations tailored to embedded use cases. This role requires some background in software profiling, performance modeling, and simulation environments. You will use and develop analysis tools and infrastructure to enable data-driven architectural decisions, create and analyze both real workloads and benchmarks representative of embedded workloads, and iterate with design teams to ensure ideas are implementable within power, timing, and area constraints. Analyze performance characteristics of embedded workloads including real-time processing, audio DSP, always-on scenarios, and embedded ML inference Collaborate with system architecture and software teams to

  • On-Device ML Integration Engineer, Graphics, Games and Machine Learning

    Apple - Cupertino, United States of America
    Indexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in posting
    posted 133 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Engineering From the posting source - Senior From the posting source $181K-$318K From the posting source Equity Inferred from posting 401(k) reported

    On-Device ML Integration Engineer, Graphics, Games and Machine Learning Cupertino, United States of America Imagine being at the forefront of an evolution where cutting-edge AI meets the elegance of Apple silicon. The On-Device Machine Learning team transforms groundbreaking research into practical applications, enabling billions of Apple devices to run powerful AI models locally, privately, and efficiently. We stand at the unique intersection of research, software engineering, hardware engineering, and product development, making Apple the leading destination for machine learning innovation. Our team builds the essential infrastructure that enables machine learning at scale on Apple devices. This involves onboarding cutting-edge architectures to embedded systems, developing optimization toolkits for model compression and acceleration, building ML compilers and runtimes for efficient execution, and creating comprehensive benchmarking and debugging toolchains. This infrastructure forms the backbone of Apple's machine learning workflows across Camera, Siri, Health, Vision, and other core experiences, contributing to the overall Apple Intelligence ecosystem. If you are passionate about the technical challenges of running sophisticated ML models across all devices, from resource-constrained devices to powerful clusters, and eager to directly impact how machine learning operates across the Apple ecosystem, this role presents an exciting opportunity to work on the next generation of intelligent experiences on Apple platforms. We are seeking a seasoned ML Engineer with broad experience and an in depth understanding of machine learning, models and infrastructure. In this senior role, you will ensure Apple's inference stack allows integrating ML workflows end-to-end with excellent user experience, flawless functionality, and maximum performance.

  • DFT Verification Infrastructure Engineer

    Intel - Israel, Haifa
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 114 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Engineering From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    DFT Verification Infrastructure Engineer Israel, Haifa posted: Posted 2 Days Ago

  • CPU Performance Architect, Platform Architecture

    Apple - Austin, United States of America
    Indexed from Apple Custom Benefit evidence checked Jun 13, 2026 Comp disclosed in posting
    posted 160 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Staff Plus From the posting source $212K-$318K From the posting source Equity Inferred from posting 401(k) reported

    CPU Performance Architect, Platform Architecture Austin, United States of America Do you have an uncommon desire to seek out and solve exceedingly difficult challenges rather than the easy ones? Do you believe that truly valuable and meaningful accomplishments are the result of pushing the limits of perseverance? Do you believe that a world-class team with relentless drive can surpass even their own high expectations? We do! But we also realize this job isn't for everyone. What we do isn't easy, but you don't take the easy path. We are seeking a highly motivated, innovative, and confident individual to join the CPU Architecture and Performance Team; we are a group that is driving advanced exploration for next generation iPhone, iPad, and Mac CPU architectures! As a CPU Performance Architect with a focus on CPU micro-architecture, you will be part of a team that is pushing the boundaries of innovation in the areas of branch prediction, code/data prefetchers, novel prediction schemes to improve latency and optimization of CPU pipelines. With others you will seek out areas for improvement while collecting data and measurements that either confirm the idea or rule it out. You will collaborate with experienced CPU designers in micro-architecture and RTL to assess the feasibility of ideas through modeling and refine those ideas to make them implementable. The role requires the analysis of specific single-threaded and multi-threaded workloads across existing and new product categories to identify bottlenecks and opportunities for improvement. We collaborate as a larger CPU architecture and performance

  • Senior GenAI Software Architect

    Intel - 2 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 143 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Engineering From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior GenAI Software Architect 2 Locations posted: Posted 30+ Days Ago

  • Senior Physical Design Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 123 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Senior From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Senior Physical Design Engineer India, Bangalore posted: Posted 11 Days Ago

  • Advanced Technology: AI/ML Research Scientist

    Cerebras Systems - Sunnyvale, CA; Toronto, Ontario, Canada; Vancouver, British Columbia, Canada
    Indexed from Greenhouse Benefit evidence checked Jun 7, 2026
    posted 178 days ago

    Why we showed this

    Description: "intel"Role: semantic match
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Inferred from posting 401(k) reported

    Advanced Technology: AI/ML Research Scientist Sunnyvale, CA; Toronto, Ontario, Canada; Vancouver, British Columbia, Canada Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Team Cerebras builds wafer-scale AI processors-single chips delivering tens of PB/s of memory bandwidth and a dataflow architecture that accelerates at a granularity no multi-device system can match. The Advanced Technology Group (ATG) is Cerebras ' pathfinding organization. We work ahead of product to explore new architectures, demonstrate breakthrough performance on scientific and AI workloads, and shape the technical roadmap for future Cerebras hardware and software. Our work regularly appears at top-tier venues (Supercomputing, SIAM, IEEE,

  • SoC Physical Design Engineer

    Intel - India, Bangalore
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 119 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Data From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    SoC Physical Design Engineer India, Bangalore posted: Posted 7 Days Ago

  • Temporary Change Management Practitioner

    Intel - 4 Locations
    Indexed from Workday Benefit evidence checked Jun 13, 2026
    posted 114 days ago

    Why we showed this

    Employer: "intel"
    Unspecified Finance From the posting source - Mid From the posting source Salary not disclosed Equity Inferred from posting 401(k) reported

    Temporary Change Management Practitioner 4 Locations posted: Posted 2 Days Ago

  • Member of Technical Staff - Compute Infrastructure

    xAI - Palo Alto, CA; Seattle, WA
    Indexed from Greenhouse Comp disclosed in posting
    posted 209 days ago

    Why we showed this

    Role: semantic match
    Unspecified Engineering From the posting source - Staff Plus From the posting source $180K-$440K From the posting source Equity

    Member of Technical Staff - Compute Infrastructure Palo Alto, CA; Seattle, WA ABOUT xAI xAI's mission is to create AI systems that can accurately understand the universe and aid humanity in its pursuit of knowledge. Our team is small, highly motivated, and focused on engineering excellence. This organization is for individuals who appreciate challenging themselves and thrive on curiosity. We operate with a flat organizational structure. All employees are expected to be hands-on and to contribute directly to the company's mission. Leadership is given to those who show initiative and consistently deliver excellence. Work ethic and strong prioritization skills are important. All employees are expected to have strong communication skills. They should be able to concisely and accurately share knowledge with their teammates. ABOUT THE ROLE: We are building one of the world's largest AI supercomputers from the ground up. As part of the Compute Infrastructure team, you will own both the raw GPU supercomputer and the platform layer that runs on top of it. You will work across the full stack - from low-level GPU kernel optimizations and Linux kernel internals to massive-scale orchestration and virtualization - to make training and inference at xAI as fast, reliable, and scalable as possible. This is a broad, high-impact role that combines hardcore supercompute and compute infrastructure work. Your contributions will directly accelerate Grok's training speed and overall AI progress. RESPONSIBILITIES : - Design, build, and optimize massive GPU clusters for extreme-scale training and inference workloads - Develop and tune low-level CUDA

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