Intel jobs

Factory Finance Specialist 2 Locations posted: Posted 30+ Days Ago

Physical Design Engineer Malaysia, Penang posted: Posted 30+ Days Ago

Senior FPGA Engineer, Intelligence Systems Reston, Virginia, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. WHAT IS AIS? Anduril Intelligence Systems (AIS) is focused on positioning Anduril as a lead provider of specialized engineering and products for Intelligence Community (IC) customers. We work within the IC to understand their requirements, shape their concepts of operation, and deliver exquisite capability across their problem set. We aim to develop and deploy critically needed capabilities that address our customers' most pressing national security requirements. ABOUT THE JOB We are looking for a Staff FPGA Engineer to join our rapidly growing team in Reston, Virginia . You will be responsible for rapidly developing, testing, and implementing FPGA designs on Xilinx SoC/FPGA platforms. This requires strong skills in digital circuit design, VHDL/Verilog coding, and simulation. WHAT YOU'LL DO - Integrate third-party vendors IP, as necessary. - Participate in entire design life cycle: from

Hardware Health US

Senior Chip Design Engineer Israel, Tel Aviv posted: Posted 9 Days Ago

Materials Development Engineer 2 Locations posted: Posted 30+ Days Ago

System Software Engineer (Embedded) Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. The Role As part of the Embedded Software team, you will help build the critical software foundation that powers the Cerebras Wafer Scale Engine (WSE)-the world's largest AI processor. Our team owns a diverse range of embedded and system level components that enable the WSE to operate reliably at scale, including microcontroller firmware, wafer level monitoring logic, system administration services, and the Linux platform and BSP layers that keep the entire system running smoothly. This role exists at the intersection of embedded systems, platform engineering, and

Semiconductor Manufacturing Engineer Malaysia, Penang posted: Posted 30+ Days Ago

System Modelling Engineer India, Bangalore posted: Posted 30+ Days Ago

IP Verification Engineer India, Bangalore posted: Posted 9 Days Ago

Director, Strategy — Edge AI and Advance Compute Hardware Palo Alto, California, United States of America | Spring, Texas, United States of America

Operations Research Engineer 3 Locations posted: Posted 3 Days Ago

Robotics Research Intern Mexico, Guadalajara posted: Posted 23 Days Ago

Sr. Technical Staff Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. Cerebras Systems Inc. has multiple openings for Sr. Technical Staff. Title: Sr. Technical Staff Job Duties: - Post silicon validation of Cerebras Wafer Scale Engines. Test and debug issues on new silicon. - Test, analyze, and characterize high-speed serial interfaces to verify compliance with hardware specifications, record performance data, and recommend design modifications to optimize functionality. - Work with the silicon and operations team to test, bring-up and run burn-in on wafers scale systems. - Support manufacturing operations to utilize the wafer bring up flow. Perform wafer

AI Developer Evangelist 3 Locations posted: Posted 2 Days Ago

AI Software Engineer Poland, Gdansk posted: Posted 7 Days Ago

Hardware Engineer (High-speed IO/Testing) (Onsite) San Jose, California, United States of America Exciting opportunity for a Hardware Engineer (High-speed IO/testing) and help design, develop, and test next-generation ASICs for global data centers. Collaborate with top engineers, drive innovation in high-speed interfaces, and shape the future of networking. Grow your career with cutting-edge technology and impactful projects at Cisco.

Senior Software Engineer India, Bangalore posted: Posted 2 Days Ago

FPGA Design Engineer United States-Illinois-Rolling Meadows

Discrete Graphics Validation Engineer Virtual Canada posted: Posted Yesterday

Hardware/ Software Co-Design Engineer Austin, Texas, United States; Fremont, California, United States About Neuralink: We are creating devices that enable a bi-directional interface with the brain. These devices allow us to restore movement to the paralyzed, restore sight to the blind, and revolutionize how humans interact with their digital world. Team Description: The Brain Interfaces Soc Department delivers chip architecture and silicon implementation of neural recording and stimulation system-on-chip (SoC) for high-bandwidth brain-machine interface applications. We have crafted a team of exceptional engineers whose mission is to push the frontiers of what is possible today and define the future. Job Description & Responsibilities: Our Hardware/ Software Co-Design Engineer will be responsible for delivering micro-architecture and register-transfer level (RTL) implementation of digital IPs and systems with a focus in high-throughput low-power digital signal processor (DSP) and general-purpose hardware accelerators towards realizing state-of-the-art brain-computer interfaces. Relevant product development experience in micro-architecture design for low-power processors, on-chip bus and network interfaces, audio/video compression processors, AI/ML accelerators, and communication PHY/MAC will be preferred. - Micro-architecture design and RTL implementation of: - Low-power digital signal processors - Low-power general-purpose hardware accelerators - Low-power graphics processing units - Low-power radio MAC/PHY - Low-power serial link MAC/PHY - Design and optimization of hardware/software interface with firmware engineers - Application-specific architecture optimization including: - Complex system modeling for energy and performance benchmarks - Workload analysis and modeling - Energy/performance profiling and analysis - Leveraging architecture-level design trade-offs with process technology and workload type - Balancing cost and performance

Analog Design Engineer India, Bangalore posted: Posted 30+ Days Ago

CPU Performance and Workload Analysis Engineer, Platform Architecture Austin, United States of America Modern system-on-chip (SoC) designs have dramatically changed how hardware and software is developed. It is increasingly important to understand the concerns of software developers when designing hardware while it is also increasingly meaningful for software developers to understand how their applications can map efficiently to modern client and server hardware. Those who can understand both and prefer to live at the intersection of hardware and software are deeply valuable, especially to Apple. The Apple CPU Architecture and Performance Team is seeking highly motivated and self-driven engineers who want to live at this intersection, individuals who have or want to develop domain expertise in emerging areas like AI, individuals who have a high-level CPU architecture understanding and desire to work with a world class team for CPU, SoC, and software development. Are you deeply accountable for your work? Your passion for product ownership and track record of product development will prove critical to your success on our team. We drive advanced exploration for next generation CPU architectures. As a member of this team, you are the interface between the CPU team, system teams, and many software teams at Apple. We have a data driven approach that is focused on real user workloads (both existing and emerging) so your work will guide optimizations and the direction of future CPUs. At the same time, you will be working with software developers to optimize code for our CPU designs and roadmap.

DFT Design Engineer Malaysia, Penang posted: Posted 25 Days Ago