Semiconductor Process Engineering – Diffusion, Wet Etch & CMP

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 13, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Mid From the posting source checked Jun 20, 2026

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company From the posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Semiconductor Process Engineering – Diffusion, Wet Etch & CMP Newport, UK Role Overview We are seeking a Wet Etch & Chemical Mechanical Planarisation (CMP) Process Engineer to support and develop advanced semiconductor manufacturing processes within a high‑volume wafer fabrication environment. All experience levels will be considered however strong preference is given to candidates with significant experience and seniority, capable of operating with minimal supervision and providing technical leadership. Experience with wet/CMP techniques is a prerequisite for this role. The role will suit candidates from a wafer fab or semiconductor equipment vendor background, particularly those with experience in power semiconductor technologies. Experience with SiC and GaN technologies is desirable but not essential. Key Responsibilities Develop and own wet etch and CMP processes in production Drive process stability, yield improvement, defectivity reduction, capability enhancement and cost down projects of varying scope and complexity, both as team lead or as part of a larger team Investigate and resolve process excursions, particle issues and reliability concerns using structured root cause analysis techniques (8D, FMEA etc) Lead process qualification and change management activities Provide technical input to new product introductions (NPI) and technology transfers Define and maintain process specifications, control plans, SPC methodologies and documentation Engage with tool vendors to progress drive tool installs and performance improvements Mentor and technically support junior engineers where appropriate Required Qualifications & Experience Degree (or equivalent experience) in Materials Science, Chemical Engineering, Physics or related discipline Practical experience as a process engineer in a semiconductor wafer fab or comparable

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