Ingénieur Développement FPGA et Traitement du Signal (H/F)

Benefits

Parental leave

Not verified

Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

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Weekend work

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Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Ingénieur Développement FPGA et Traitement du Signal (H/F) Gennevilliers, Hauts-de-Seine, France Nous recherchons un Ingénieur Développement FPGA et Traitement du Signal pour rejoindre notre équipe dynamique à Gennevilliers. Vous serez responsable du développement de FPGA haute densité et de l'implémentation d'algorithmes de traitement du signal. Rejoignez-nous pour contribuer à des projets innovants dans un environnement collaboratif.

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