Principal Engineer, Automated Derivatives

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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Not verified checked Jun 7, 2026

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

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About this role

Principal Engineer, Automated Derivatives Austin, TEXAS, United States Company Description: Job Description: In this multi-disciplinary role, you will lead the end-to-end delivery of derivative SoCs , focusing on the intersection of RTL design, functional verification, and physical implementation. You will not just execute flows; you will build an AI-augmented "Silicon Factory" that uses machine learning to bridge the gap between architectural intent and GDSII. Your goal is to achieve ultra-fast turnaround times by using AI to predict physical outcomes during RTL coding and to automate the verification of design variants. Key Responsibilities 1. AI-Augmented RTL & Architecture Physical-Aware RTL: Use ML-based predictors to evaluate RTL code for timing and congestion bottlenecks before synthesis, reducing the number of "RTL-to-GDS" iterations. Derivative Generation: Develop scripts and Generative AI prompts to automate the creation of RTL wrappers, memory maps, and bus interconnects for design variants. Logic Optimization: Employ AI to identify redundant logic or clock-gating opportunities to hit aggressive power targets in derivative designs. 2. Intelligent Verification Automated Testbench Scaling: Build AI-driven verification environments that automatically adjust constraints and coverage goals when a design derivative (e.g., changed cache size or port count) is instantiated. Smart Regression Management: Use ML to prioritize test cases that are most likely to fail based on historical RTL changes, slashing simulation time and compute costs. Bug Prediction: Deploy pattern-recognition models to identify "bug-prone" modules in the RTL based on complexity metrics and previous tape-out data. 3. Rapid Physical Implementation Seamless Handoff: Ensure a "zero-friction" path from RTL to

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