Physical Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified checked Jun 7, 2026

Salary

Not verified

401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

Was this benefit information wrong? Tell us.

Market context

U.S. role benchmark (BLS OEWS)

$111,944 U.S. median for this role

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Data From the posting source

Seniority

Mid From the posting source

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Physical Design Engineer Catania, , Italy Company Description: Job Description: We are looking for a Physical Design Engineer to join our Analog Backend team and work on the digital island implementation within our analog chips. This role is ideal for someone who enjoys solving complex physical design challenges in mixed-signal environments. What You'll Do Implement key aspects of the ASIC physical design flow, including floorplanning, placement optimization, clock tree synthesis, routing, and physical verification Optimize designs for performance, reliability, and manufacturability Perform chip-level power integrity analysis across multiple voltage domains (IR drop, signal EM, and power EM) Work on digital implementation embedded in analog environments Collaborate with global cross-functional teams including analog designers and verification engineers Qualifications: Experience in ASIC Physical Design Strong understanding of floorplanning, placement, CTS, routing, and sign-off checks Knowledge of power integrity analysis (IR drop and electromigration) A team player who enjoys working in an international, collaborative environment Analog Layout experience is a plus Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences

Read the full description at jobs.smartrecruiters.com. FewerJobs shows a preview and links to the original posting.