Senior QPU Software Engineer (FPGA)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Senior From the posting source checked Jun 20, 2026

Schedule

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Weekend work

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Company

Equity

Offered From the posting source checked Jun 20, 2026

Application

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Deadline

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About this role

Senior QPU Software Engineer (FPGA) Boston, MA, USA Senior FPGA Engineer - Quantum Computing Control Systems Company Overview Join QuEra Computing's engineering team to develop cutting-edge FPGA systems for neutral atom quantum computers. You'll work on real-time control systems that manipulate individual atoms with microsecond precision, enabling breakthrough quantum algorithms and applications. Role Summary We're seeking a Senior FPGA Engineer to design, implement, and optimize high-performance FPGA systems for quantum computing applications. You'll work on complex real-time control systems, high-speed data acquisition, and precision timing systems that are critical to our quantum computer's operation. Key Responsibilities Core FPGA Development - Design and implement System Verilog modules for quantum control systems including: - Scheduled multitone generators for RF/microwave quantum gates - Real-time pulse sequencers for laser control - High-speed ADC/DAC interfaces (16-bit, 4 samples/clock) - Hardware-accelerated image processing for atom detection - Develop and maintain Ulti-board FPGA designs (Xilinx Zynq UltraScale+ RFSoC) - Implement high-speed serial interfaces (CoaXPress, Aurora, AXI4-Stream) - Design clock domain crossing logic with proper CDC verification - Optimize resource utilization and timing closure for complex designs System Integration & Verification - Create comprehensive testbenches using System Verilog and Python (cocotb) - Develop simulation models for quantum control peripherals - Implement formal verification for critical timing constraints - Design and validate real-time trigger and synchronization systems - Troubleshoot hardware-software integration issues Performance & Reliability - Optimize data through put for high-bandwidth quantum control signals - Implement error detection and recovery mechanisms - Design robust clocking architectures for multi-domain

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