ML Research Engineer - Hardware Codesign

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About this role

ML Research Engineer - Hardware Codesign San Francisco, California, United States About the Team OpenAI's Hardware organization develops silicon and system-level solutions designed for the unique demands of advanced AI workloads. The team is responsible for building the next generation of AI silicon while working closely with software and research partners to co-design hardware tightly integrated with AI models. In addition to delivering production-grade silicon for OpenAI's supercomputing infrastructure, the team also creates custom design tools and methodologies that accelerate innovation and enable hardware optimized specifically for AI. About the Role We're seeking a Research-Hardware Codesign Engineer to operate at the boundary between model research and silicon/system architecture. You'll help shape the numerics, architecture, and technology bets of future OpenAI silicon in collaboration with both Research and Hardware. Your work will include debugging gaps between rooflines and reality, writing quantization kernels, derisking numerics via model evals, quantifying system architecture tradeoffs, and implementing novel numeric RTL. This is a hands-on role for people who go looking for hard problems, get to ground truth, and drive it to production. Strong prioritization and clear, honest communication are essential. Location: San Francisco, CA (Hybrid: 3 days/week onsite) Relocation assistance available. In this role you will: - Build on our roofline simulator to track evolving workloads, and deliver analyses that quantify the impact of system architecture decisions and support technology pathfinding. - Debug gaps between performance simulation and real measurements; clearly communicate root cause, bottlenecks, and invalid assumptions. - Write emulation kernels for low-precision numerics

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