Member of Technical Staff - GPU Performance Engineer

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

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Salary

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401(k) match

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Role

Role function

Engineering From the posting source checked Jun 20, 2026

Seniority

Staff Plus From the posting source checked Jun 20, 2026

Work mode

Remote From the posting source checked Jun 20, 2026

In-office days

0 days From the posting source checked Jun 20, 2026

Schedule

Shift type

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Weekend work

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Company

Equity

Offered From the posting source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Member of Technical Staff - GPU Performance Engineer San Francisco, United States, Boston, Remote About Liquid AI Spun out of MIT CSAIL, we build general-purpose AI systems that run efficiently across deployment targets, from data center accelerators to on-device hardware, ensuring low latency, minimal memory usage, privacy, and reliability. We partner with enterprises across consumer electronics, automotive, life sciences, and financial services. We are scaling rapidly and need exceptional people to help us get there. The Opportunity Our models and workflows require performance work that generic frameworks don't solve. You'll design and ship custom CUDA kernels, profile at the hardware level, and integrate research ideas into production code that delivers measurable speedups in real pipelines (training, post-training, and inference). Our team is small, fast-moving, and high-ownership. We're looking for someone who finds joy in memory hierarchies, tensor cores, and profiler output. While San Francisco and Boston are preferred, we are open to other locations. What We're Looking For We need someone who: - Works profiler-first: You use tools like Nsight Systems / Nsight Compute to find bottlenecks, validate hypotheses, and iterate until improvements show up in end-to-end benchmarks. - Bridges theory and practice: You can translate ideas from papers into implementations that are robust, testable, and performant. - Executes independently: Given an ambiguous bottleneck, you can drive from profiling to kernel/integration changes to benchmarked results to maintained ownership. - Cares about the details: Memory hierarchy, occupancy, launch configs, tensor core utilization, bandwidth vs compute limits. The Work - Write high-performance

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