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Post-silicon Validation and Debug Engineer

Intel - 2 Locations

Posted Apr 27, 2026

Verified benefits

Parental leave
12 weeks source
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed

Where they hire

State eligibility is not yet verified.

About this role

Post-silicon Validation and Debug Engineer 2 Locations Post-silicon Validation and Debug Engineer /job/US-Oregon-Hillsboro/Post-silicon-Validation-and-Debug-Engineer_JR0282304 2 Locations Posted 9 Days Ago

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