Mixed Signal Logic Design Engineer
Intel - Malaysia, Penang
Posted 5/6/2026
Verified benefits
- Parental leave
- 12 weeks source
- Non-birth-parent leave
- 12 weeks
- Verified
- Yes last checked unknown
- Salary
- Not disclosed
Where they hire
State eligibility is not yet verified.
About this role
Mixed Signal Logic Design Engineer Malaysia, Penang Mixed Signal Logic Design Engineer /job/Malaysia-Penang/Mixed-Signal-Logic-Design-Engineer_JR0283765 Malaysia, Penang Posted Today
Read the full description at intel.wd1.myworkdayjobs.com. FewerJobs shows a short excerpt and links to the source.
Related jobs
-
Sr. Optical Lens Designer
Ametek - Location not specified
-
Mold Design Engineer
Ametek - Location not specified
-
Vice President, Client Platforms User Experience Designer
Ares Management - London, UK
-
Intern- Integrated Production Services Design
Ametek - Location not specified