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Mixed Signal Logic Design Engineer

Intel - Malaysia, Penang

Posted 5/6/2026

Verified benefits

Parental leave
12 weeks source
Non-birth-parent leave
12 weeks
Verified
Yes last checked unknown
Salary
Not disclosed

Where they hire

State eligibility is not yet verified.

About this role

Mixed Signal Logic Design Engineer Malaysia, Penang Mixed Signal Logic Design Engineer /job/Malaysia-Penang/Mixed-Signal-Logic-Design-Engineer_JR0283765 Malaysia, Penang Posted Today

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