Compute Design Engineer, Principal
d-Matrix - Santa Clara, Santa Clara, Ca, Ca, United States
Posted Mar 3, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Salary
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- 401(k) match
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Schedule
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- Weekend work
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Application
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- Deadline
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Where they hire
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About this role
Compute Design Engineer, Principal Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Compute Design Engineer, Principal What you will do: As part of this team, you will be responsible for the micro-architecture and design of the AI sub-system modules including SIMD, Hardware Execution Engines. You will also be responsible for definition and implementation of Custom ISA. Work with System Architects to develop efficient C-Kernel utilizing the Custom ISA. You will own design, document, execute and deliver fully verified, high performance, area, and power efficient RTL to achieve the design targets and specifications. You will also design of micro-architecture and RTL, synthesis, logic and timing verification using leading edge CAD tools and semiconductor process technologies. You will design and implement logic functions that enable efficient test and debug and participate in silicon bring-up and validation for blocks owned. RESPONSIBILITIES: -
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