Senior Design Engineer

Benefits

Parental leave

Not verified

Non-birth-parent leave

Not verified

Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

Not verified

Relocation assistance

Not verified

Childcare support

Not verified

Learning budget

Not verified

Verification

Not verified last checked Jun 13, 2026

Salary

Not verified

401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

Was this benefit information wrong? Tell us.

Schedule

Shift type

Not verified

Weekend work

Not verified

Application

Cover letter

Not verified

Assessment

Not verified

Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Senior Design Engineer Taiwan Senior Digital Verification Engineer About Cohu Cohu is a global technology and market leader in semiconductor test and inspection metrology markets. Our advanced systems are critical to ensuring the quality and reliability of the next generation of electronics. This role is a key part of the team developing our state-of-the-art 26 GHz RF semiconductor tester platform , leveraging cutting-edge Xilinx Versal ACAP technology to achieve unparalleled performance. Learn more at cohu.com . Job Summary Cohu is seeking a Senior Digital Verification Engineer to join our expanding digital team. This critical role focuses on verifying complex digital designs for our power IC, RF, digital, and mixed-signal test solutions within the Versal ACAP. The successful candidate will utilize advanced tools and methodologies-including SystemVerilog (UVM) and Cadence vManager -to develop and execute comprehensive verification plans that ensure first-pass silicon success for our high-performance hardware. Key Responsibilities Verification Strategy and Planning Develop and implement detailed, reusable test plans and verification strategies based on design requirements, architecture specifications, and product functional objectives. Environment Development Create and maintain robust, scalable verification environments using SystemVerilog and the Universal Verification Methodology (UVM) . Test Development and Execution Write, execute, and manage targeted and constrained-random tests to verify functionality at various abstraction levels (unit, block, and full system). Verification IP and Modeling Develop reusable Verification IP (vIP) and Bus Functional Models (BFMs) to accurately simulate and verify interfaces (e.g., AMBA/AXI , I²C , SPI ). Model-Based Verification Implement verification testbenches and comparison points derived from

Read the full description at hcbo.fa.us2.oraclecloud.com. FewerJobs shows a source-linked preview and links to the original posting.