Senior Design Verification Engineer - PCI-Express Controller IP

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified last checked Jun 13, 2026

Salary

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401(k) match

Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

State eligibility is not yet verified.

About this role

Senior Design Verification Engineer - PCI-Express Controller IP SOFIA, UNAVAILABLE, BG Overview Rambus, a premier chip and silicon IP provider, is seeking to hire an exceptional mid tosenior-level individual contributor Design Verification Engineer to join our PCIe Express IP Products team in Sofia, Bulgaria. The successful candidate will participate in pre-silicon RTL Verification activities related to PCIe Controller SoftIP development, on leading-edge PCI-Express and CXL controller technologies. This is a Full Time position, reporting to the local onsite Verification management. Rambus offers a flexible work environment, embracing a hybrid approach for the majority of our office-based roles. We encourage employees to spend an average of at least three days per week working onsite while also allowing for two days of remote work. Responsibilities Duties in this position will include: Testbench and test sequence development for verification of new controller technologies and features Functional coverage planning, coverage item coding, and test suite augmentation to achieve Functional Coverage Regression test development, monitoring, debug/triage, and correction to test environment, sequences, debug of controller RTL design Development & support of Verification environment scripting and capabilities Qualifications Bachelors Degree or above in EE/CS, at least 5-7 years prior experience with HDL logic Design-Verification SystemVerilog and/or UVM testbench, Verilog/SystemVerilog logic design, /RTL familiarity/project work Pre-existing Experience / familiarity with one or more I/O controller technologies such as PCI-Express, is highly desireable Working experience with Python and TCL scripting languages preferred About Rambus Rambus is a global company that makes industry-leading memory interface chips and Silicon IP

Read the full description at careers-rambus.icims.com. FewerJobs shows a source-linked preview and links to the original posting.