Lead MTS Analog Engineering
Rambus INC - San Jose, CA, US
Posted May 1, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Lead MTS Analog Engineering San Jose, CA, US Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead MTS Analog Engineering to join our Memory Interface Chip team in San Jose. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Rambus offers a flexible work environment, embracing a hybrid approach for most office-based roles. Employees are encouraged to spend an average of at least three days per week onsite, allowing for two days of remote work. Responsibilities Primary focus will be the products IO ESD/LU/EOS area, design & maintain the centralized ESD/LU/EOS design across multiple products. Create Chip/block level floorplan and work with mask designer to complete layout. Work with package engineering to create bonding diagram. Ownership of Analog/Mixed signal designs at chip and/or block level Chip level integration Work closely with Digital team to define analog/digital interface. Design, simulate and characterize analog/mixed signal circuits (e.g. Bandgap, Bias, LDO, IO, DC-DC BUCK, etc). Create and maintain test documents for test and validation engineering Work with the Lab/Validation team for test plan, silicon bring up and characterization Work closely with cross functional teams from different geographies and time zones to ensure engagement and execution Other responsibilities include design documentation and post silicon activity support Qualifications Deep understanding the process device ESD/LU/EOS. Deep understanding ERC/DRC/LVS. Competent in using fast simulator (CustomSim, XPS, AMS) for
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Apply link verified; last checked Jun 13, 2026.
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