Staff Engineer, Digital ASIC Design (CONTRACT)

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

• Fertility benefits: Not verified
• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Verification

Not verified checked Jun 7, 2026

Salary

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401(k) match

Reported from DOL Form 5500 industry filing (not employer-specific)

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Market context

U.S. role benchmark (BLS OEWS)

$116,543 U.S. median for this role

Projected growth (BLS Employment Projections)

+9.8% - Much faster than average

Matched to SOC 15-1252 - Software Engineering aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type

Not verified

Weekend work

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Company

Company stage

Public-company Verified - from the job posting source checked Jun 20, 2026

Equity

Offered Verified - SEC 10-K source checked Jun 20, 2026

Application

Cover letter

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Assessment

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Deadline

Not stated

Where they hire

State eligibility is not yet verified.

About this role

Staff Engineer, Digital ASIC Design (CONTRACT) Burlington, MA Office Job Description The role of the Staff Digital ASIC Designer offers the opportunity to work within the heart of the product development team and founders and to own the core of what will set Butterfly Network apart. This individual will design, implement, and verify digital signal processing, high speed interface, and system-on-a-chip logic for a suite of next-generation products. As part of our team, your core responsibilities will be: - Develop low-power RTL for large SoCs in an advanced node. - Implement and optimize signal processing algorithms in RTL. - Integrate multiple embedded processor cores into a large design. - Develop efficient high bandwidth on chip data paths. - Other Technology, Architecture, & Productivity duties as assigned Qualifications Baseline skills/experiences/attributes: - BS/MS/PhD in EE/CE (or equivalent practical silicon design experience). - 8+ years (typical Staff level) in digital IC / ASIC / SoC design with substantial hands-on RTL ownership and at least one major-IP or full-chip tapeout cycle. - Proven ownership of a defined digital IP/subsystem from micro-architecture and RTL implementation through verification closure and tapeout support. - Strong RTL skills in SystemVerilog/Verilog, including pipelined datapaths, control logic/state machines, and high-throughput streaming interfaces. - Experience designing sustained high-throughput datapaths, including buffering/FIFOs, arbitration/backpressure, bandwidth budgeting, and SRAM/memory interface considerations. - Strong understanding of silicon-level design constraints, including clock/reset architecture, CDC/RDC risk mitigation, power-aware design, and PPA tradeoffs. - Effective collaboration with verification to drive functional closure through signoff (SV/UVM and/or Python-based frameworks

Read the full description at www.butterflynetwork.com. FewerJobs shows a preview and links to the original posting.