Principal Digital Design Engineer (AI Fabric)

Benefits

Parental leave

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Non-birth-parent leave

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Family-building benefits

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• Adoption assistance: Not verified
• Surrogacy assistance: Not verified

Mental health support

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Relocation assistance

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Childcare support

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Learning budget

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Salary

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401(k) match

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Market context

Median wage (BLS OEWS)

$111,944 national median

Projected growth (BLS Employment Projections)

+13.7% - Much faster than average

85% above the BLS national median for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

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Weekend work

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Application

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Assessment

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Deadline

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Where they hire

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About this role

Principal Digital Design Engineer (AI Fabric) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment. Key Responsibilities - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design. - Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. - Work closely with post-silicon teams to facilitate silicon bring-up and debug. - Mentor junior engineers to develop their technical skills and expertise. - Actively contribute to the development and improvement of silicon development processes. - Drive designs to production, ensuring accountability for quality, schedule, and overall design

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