Manager, Package Design Engineering
Astera Labs - San Jose, California, United States
Posted Mar 26, 2026
Benefits
- Parental leave
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- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
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- Mental health support
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- 401(k) match
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About this role
Manager, Package Design Engineering San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products. As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers. This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven
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