SoC DFT Engineer
Apple - Austin, United States of America
Posted Apr 10, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
SoC DFT Engineer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. In this highly visible role, you will be at the center of a semiconductor design effort collaborating with all disciplines, with a critical impact on getting functional products to millions of customers quickly. As a DFT engineer you will be involved with the complete DFT solution for a design project, you will have responsibilities spanning all aspects of semiconductor design. - Developing and implementing DFT architecture - Implementing DFT infrastructure - Working with the DV team to verify DFT implementations and implement ECOs - Generating structural test vectors and analyzing and improving coverage - Working with designers on STA, physical, power and logical issues - Working with test engineers to bring up test vectors on silicon - Running schedules and supporting multi-functional engineering efforts Minimum Qualifications: Minimum of BS + 0 years relevant industry experience. Preferred Qualifications: Knowledge about industrial standards and practices in DFT, including ATPG, JTAG, MBIST
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