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SoC DFT DV Engineer

Apple - Austin, United States of America

Posted Apr 10, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Schedule

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Weekend work
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Application

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Assessment
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Deadline
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Where they hire

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About this role

SoC DFT DV Engineer Austin, United States of America Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, inquisitive people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our multifaceted group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and inspire millions of Apple's customers every single day. Are you ready to join a team redefining hardware technology? We are searching for a hard-working engineer to join our exciting team of problem solvers. In this highly transparent and interactive role, your primary responsibilities will include: - Reviewing Architecture and Design Specifications. - Extracting design features and developing attributes and verification plans. - Working with designers to verify DFT implementation and run various checks. - Implementing test benches, generating advised/constrained random tests. - Debugging failures, running gate level simulations, supervising bugs, and closing coverage. - Handling schedules and supporting multi-functional engineering effort. - Assisting in verification

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