Graphics FE Integration Engineer
Apple - Austin, United States of America
Posted Apr 14, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
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- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
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- Childcare support
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- Learning budget
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- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Graphics FE Integration Engineer Austin, United States of America Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. As a member of GPU FE Design integration team, you will create GPU RTL by integrating various IPs following architectural parameters, physical constraints, DFT logic and power intent. As a GPU Design Integration Engineer, you will be responsible for: - RTL integration, partitioning, design analysis, qualification, packaging and delivery. - Run logic equivalence checking between designs. - Ensure implementation readiness with RTL lint, custom checks and unit level synthesis. - Develop innovative methods to improve front-end design integration process. - Understand and contribute to specifications for design units. - Collaborate effectively with Architecture, IP, DV, SOC, DFT, IMPL teams spanning multiple sites. Minimum Qualifications: BS + 3 years of relevant experience. Experience with Verilog/System Verilog. Experience with the one of the following scripting languages: Perl/Ruby/Python. Preferred Qualifications: Knowledge of PPA optimization techniques and implementation flows. Experience with scalable designs, DFT insertion, LEC, Lint and codeline management. Ability to debug and solve various design integration issues in a timely manner. Proficiency in logic design principles. Proficiency in
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