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GPU Physical Design Clocking Engineer

Apple - Austin, United States of America

Posted Feb 13, 2026

Benefits

Parental leave
Not verified
Non-birth-parent leave
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Family-building benefits
  • Fertility benefits: Not verified
  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked Jun 13, 2026
Salary
$181K-$318K not verified - source not recorded; timestamp not recorded
401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.

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Market context

U.S. role benchmark (BLS OEWS)
$111,944 U.S. median for this role
Projected growth (BLS Employment Projections)
+13.7% - Much faster than average

123% above the BLS role benchmark for data and ml aggregate.

Matched to SOC 15-1252 - Data and ML aggregate by role bucket.

Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.

Schedule

Shift type
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Weekend work
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Application

Cover letter
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Assessment
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Deadline
Not stated

Where they hire

State eligibility is not yet verified.

About this role

GPU Physical Design Clocking Engineer Austin, United States of America Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC)! You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration. As a GPU Clocking engineer, you will collaborate with FE teams to understand chip architecture and drive clocking aspects early in design cycle. You will drive best in class clocking construction and solutions for performance, power and Area (PPA). You will collaborate to drive clocking methodologies and “best known methods” to streamline PD work, come up with guidelines and checklists, drive execution, and supervise progress. You will need to communicate and drive the needs of PD and Clocking with multi-functional teams that will enable achieving the goals of the back-end design for the project. Minimum Qualifications: BS + 10 years of relevant experience Experience with ASIC integration including one or more of the following: Floorplanning, Clock and Power distribution, global signal planning,

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