CPU Implementation Lead Engineer
Apple - Santa Clara, United States of America
Posted Apr 13, 2026
Benefits
- Parental leave
- Not verified
- Non-birth-parent leave
- Not verified
- Family-building benefits
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- Fertility benefits: Not verified
- Adoption assistance: Not verified
- Surrogacy assistance: Not verified
- Mental health support
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- Relocation assistance
- Not verified
- Childcare support
- Not verified
- Learning budget
- Not verified
- Verification
- Not verified last checked Jun 13, 2026
- Salary
- Not verified not verified - source not recorded; timestamp not recorded
- 401(k) match
- Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked Jun 13, 2026.
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Schedule
- Shift type
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- Weekend work
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Application
- Cover letter
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- Assessment
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- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
CPU Implementation Lead Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! Apple's Silicon Engineering Group (SEG) is hiring experienced engineers for the CPU Implementation leadership team. As a CPU Implementation Lead Engineer, you will own or participate in the following: • CPU IP delivery • Work with multi-functional engineering teams to implement and validate physical design in the aspects of timing, power, area, electrical analysis, functionality, reliability, and testability • Work extensively with the partition implementation team to make area/frequency/performance/power tradeoffs and remove bottlenecks in meeting design targets and delivery schedule • Participate in the definition and enhancement of RTL-to-GDS flow through synthesis and place-and-route targeting aggressive targets for power, performance, and area • Mentor junior engineers Minimum Qualifications: Minimum BS and 10+ years of relevant industry experience Experience in driving chip implementation from definition phase to silicon correlation Experience working with cross-functional teams spanning technology, architecture, RTL & Physical design Experience in
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