Sr. DFT Design Engineer, AWS Machine Learning Acceleration

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About this role

Sr. DFT Design Engineer, AWS Machine Learning Acceleration Austin, Texas, USA Custom SoCs (System on Chip) are at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team, you'll be responsible for designing and optimizing hardware in our data centers, including AWS Inferentia and Trainium systems-our custom-designed machine learning inference and training servers. Our success depends on world-class server infrastructure as we handle massive scale and rapidly integrate emerging technologies. We're looking for a Sr. DFT Design Engineer to help us trailblaze new technologies and architectures while ensuring high design quality and making the right trade-offs. Key job responsibilities • Define and develop state-of-the-art Design for Test (DFT) architectures for advanced technology nodes • Work closely with block designers and physical design (PD) team to implement highly efficient DFT solutions • Act as the primary point of contact for cross-functional stakeholders (PD, Architecture, and Product Engineering) to align schedules and goals • Mentor and develop junior engineers through code reviews, methodology training, and technical guidance • Manage project timelines and deliverables, ensuring high-quality DFT implementation from RTL through Silicon bring-up Basic Qualifications: - Bachelor's degree in computer science, electrical engineering, or related field - 5+ years of practical semiconductor ASIC design work including owning end to end design of major SOC blocks experience - Knowledge about industry standard tools and practices in DFT, including ATPG, JTAG, MBIST and trade-offs between test quality and test time - Experience with automation script development Preferred Qualifications:

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