Principal Applied Scientist, ML Codesign
Amazon - Sunnyvale, California, USA
Posted Jun 10, 2026
Benefits
- Parental leave
- 6 weeks From the posting source checked Jun 20, 2026
- Non-birth-parent leave
- 6 weeks From the posting source checked Jun 20, 2026
- Family-building benefits
- Mental health support
- Offered From the posting source checked Jun 20, 2026
- Relocation assistance
- Not verified
- Childcare support
- Offered From the posting source checked Jun 20, 2026
- Learning budget
- Not verified
- Verification
- Source-linked checked Jun 7, 2026
- Salary
- $229K-$309K From the posting source checked Jun 20, 2026
- 401(k) match
- Reported from DOL Form 5500 industry filing (not employer-specific)
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Market context
- U.S. role benchmark (BLS OEWS)
- $111,944 U.S. median for this role
- Projected growth (BLS Employment Projections)
- +13.7% - Much faster than average
140% above the BLS role benchmark for data and ml aggregate.
Matched to SOC 15-1252 - Data and ML aggregate by role bucket.
Source: U.S. Bureau of Labor Statistics, OEWS, May 2024 and Employment Projections, 2024-2034.
Role
Schedule
- Shift type
- Not verified
- Weekend work
- Not verified
Company
Application
- Cover letter
- Not verified
- Assessment
- Not verified
- Deadline
- Not stated
Where they hire
State eligibility is not yet verified.
About this role
Principal Applied Scientist, ML Codesign Sunnyvale, California, USA Define the joint optimization of model compression and silicon architecture for Amazon's next generation of edge and cloud inference accelerators. Your work will set the technical targets that propagate across the model, compiler, runtime, and silicon stack. We are hiring a Principal Applied Scientist to be the technical leader who closes the loop between compression science and silicon design. Today's generation ships advanced quantization and large-model distillation in production, running multi-billion parameter language models at inference economics typical of much larger systems. Future generations target significantly larger models at the edge and in the cloud. You will be a principal architect of the next-generation accelerator and of the compression algorithms it executes natively. Few roles in the industry let one technical leader influence the model, the compiler, the runtime, and the silicon without organizational friction. This is one of them. You have spent the last several years thinking about why hardware decisions and accuracy decisions live in different teams, and you want to be the person who owns both. You have published at MLSys, ISCA, MICRO, NeurIPS, or ICML on quantization, pruning, or hardware-aware training, and you want your next paper to ship in a chip rather than in a benchmark suite. You want a vertical stack-model, compression, compiler, runtime, operating system, silicon-where the same engineering organization owns every layer and a principal architect can move all of them. Key job responsibilities • Define the hardware-aware compression roadmap for next-generation accelerators, working
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