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Principal Analog IC Design Engineer, High Speed SerDes

Cadence Design Systems - SAN JOSE

Posted Apr 29, 2026

Benefits

Parental leave
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Non-birth-parent leave
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Family-building benefits
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  • Adoption assistance: Not verified
  • Surrogacy assistance: Not verified
Mental health support
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Relocation assistance
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Childcare support
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Learning budget
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Verification
Not verified last checked May 7, 2026
Salary
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401(k) match
Listed Source: EMPLR_CONTRIB_INCOME_AMT. source Last checked May 7, 2026.

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Schedule

Shift type
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Weekend work
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Application

Cover letter
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Assessment
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Deadline
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Where they hire

State eligibility is not yet verified.

About this role

Principal Analog IC Design Engineer, High Speed SerDes SAN JOSE Principal Analog IC Design Engineer, High Speed SerDes /job/SAN-JOSE/Principal-Analog-IC-Designer_R52909-1 SAN JOSE Posted 7 Days Ago

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