I'm looking for a job. I exported this list from FewerJobs.com - a curated job board.

Please:
1. Rank these jobs by fit for me, given my resume / skills.
2. Highlight the top 5 with a one-sentence rationale each.
3. Flag any concerns, including benefit values without source-backed evidence.
4. Suggest one or two filter changes I could make on FewerJobs to find more good matches.

Filters I applied:
- q: Synopsys
- quality_floor: default
- match_401k_strict: true
- parental_strict: true
- non_birth_strict: true
- pto_strict: true
- include_older: false
- apply_url_verified: false
- page: 1
- per_page: 100
- sort: relevance

Jobs (100 total):

---
TITLE: Software Engineering
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/software-engineering-jobs
EXCERPT: Software Engineering Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: Software Engineering Save Senior Software Engineer - Platform Software Bengaluru, India Category: Engineering Posted: 04/20/2026 Job ID: 16989 Save Silicon Validation, Staff Engineer - 16247 Mississauga, Canada Category: Engineering Posted: 04/07/2026 Job ID: 16247 Save Senior Software Engineer - Device Driver and Firmware Bengaluru, India Category: Engineering Posted: 03/30/2026 Job ID: 16622 Save Software Engineer - Silicon Validation Tools (SerDes) Mississauga, Canada Category: Engineering Posted: 03/22/2026 Job ID: 16183 Save Software Engineering, Staff - 15410 Hillsboro, Oregon Category: Engineering Posted: 02/24/2026 Job ID: 15410 Filter Results Refine by Keyword Add Category Engineering (5) Sub Category Software Engineering (5) Remote Eligible No (5) JobRefID 15410 (1) 16183 (1) 16247 (1) 16622 (1) 16989 (1) CareerAreas Analog Design (63) Applications Engineering (116) ASIC Digital Design (105) ASIC Physical Design (16) R&D Engineering (118) Sales Account Management (38) Software Engineering (5) Sub
---
TITLE: Technical Writing Internship
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/job/canonsburg/technical-writing-internship/44408/94574445920
EXCERPT: Technical Writing Internship At-Synopsys,-we-want-talented-people-of-every-background-to-feel-valued-and-supported-to-do-their-best-work.-Synopsys-considers-all-applicants-for-employment-without-regard-to-race,-color,-religion,-national-origin,-gender,-sexual-orientation,-age,-military-veteran-status,-or-disability. custom_fields.Disclaimer- In-addition-to-the-base-salary,-this-role-may-be-eligible-for-an-annual-bonus,-equity,-and-other-discretionary-bonuses.-Synopsys-offers-comprehensive-health,-wellness,-and-financial-benefits-as-part-of-a-competitive-total-rewards-package.-The-actual-compensation-offered-will-be-based-on-a-number-of-job-related-factors,-including-location,-skills,-experience,-and-education.-Your-recruiter-can-share-more-specific-details-on-the-total-rewards-package-upon-request.-The-base-salary-range-for-this-role-is-across-the-U.S. custom_fields.SalaryRange-$0-$0 custom_fields.SubCategory-Intern,-Co-Op custom_fields.EmployeeStatus-Intern custom_fields.unposting_date-2026-05-08"> Technical Writing Internship at Synopsys Skip to main content Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Search Jobs Find Jobs For Where? Search Jobs Technical Writing Internship Canonsburg, Pennsylvania, United States Interns/Temp Intern $0-$0 Apply Save Job Share Email LinkedIn X Facebook Jump to Overview Job Description Benefits Culture How We Hire Overview Our internship programs offer real-world projects, hands-on experience, and opportunities to collaborate with passionate teams globally. Explore your interests, share your ideas, and bring them to life while shaping your career path within our inclusive culture that fosters innovation and collaboration. Engineer your future with us! Play Video Job Description Date posted 03/29/2026 Category Interns/Temp Hire Type Intern Job ID 16253 Base Salary Range $0-$0 Remote Eligible No Date Posted 03/29/2026 *Please include a writing sample with your application* Introduction: Our technology drives the Era of Pervasive Intelligence, where smart tech and AI are seamlessly woven into daily life. From self-driving cars and health-monitoring smartwatches to renewable energy systems that efficiently distribute clean power, Synopsys creates high-performance silicon chips that help build a healthier, safer, and more sustainable world. Internship Experience:
---
TITLE: Click here
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://synopsys.avature.net/talentcommunity?jobId=88&source=Radancy&tags=Careersite_leads
EXCERPT: Click here Applying to Synopsys Talent Community | Synopsys Skip to content Synopsys Synopsys Talent Community Select your resume 1 /3 Select your resume, step 1 of 3 Personal info 2 /3 Confirmation 3 /3 Synopsys and Ansys are Now United: Join Our Talent Community What is the Synopsys Talent Community? The Synopsys Talent Community is a vibrant network of professionals eager to stay connected with exciting job opportunities, recruitment activities, and the latest industry trends as we Power the Era of Pervasive Intelligence. Why Should You Join? How We Utilize Your Information Your journey with us starts with your resume. Here's how we use your information to benefit you: Personalized Matching: Align your skills with the perfect opportunities. Career Engagement: Receive tailored job openings, success stories, and career advice. Exclusive Events: Invitations to events that match your expertise. Key Areas of Focus Our Talent Community is a way for us to know more about you. Your skills and experience are aligned with the key areas where we are always seeking to hire talent globally across our locations: Hardware: Innovate with roles in layout, analog, ASIC, application engineering, and physical design. Software: Shape the future with positions in design automation, software engineering, product/solution engineering, AI, and tech support. IT: Drive excellence in cloud solutions, network engineering, IT support, DevOps, site reliability, and data centers. Go-To-Market: Propel growth in customer relationships, sales engineering, product marketing, territory account management, and field roles. Join Us and Make a Difference! At Synopsys, we are
---
TITLE: Sales Account Management
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/sales-account-management-jobs
EXCERPT: Sales Account Management Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: Sales Account Management Save Director of Sales Account Management (Foundry) Sunnyvale, California Category: Sales Posted: 05/03/2026 Job ID: 17272 Save Sales Account Management, Staff Tokyo, Japan Category: Sales Posted: 05/03/2026 Job ID: 17260 Save Sales Account Management, Sr Staff Tokyo, Japan Category: Sales Posted: 05/03/2026 Job ID: 17262 Save Enterprise Account Executive United States Off-site Category: Sales Posted: 04/26/2026 Job ID: 17117 Save Director of Sales Account Management Marlborough, Massachusetts Category: Sales Posted: 04/30/2026 Job ID: 17274 Save Sales Account Management, Sr Associate Taipei, Taiwan Category: Sales Posted: 03/10/2026 Job ID: 16052 Save Product Sales Manager, Staff Taipei, Taiwan Category: Sales Posted: 03/09/2026 Job ID: 16043 Save Sales Account Management, Staff Seoul, South Korea Category: Sales Posted: 04/22/2026 Job ID: 17032 Save Account Representative Taipei, Taiwan Category: Sales Posted: 04/14/2026 Job ID: 16943 Save Sales Account Management, Principal
---
TITLE: R&D Engineering
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/rd-engineering-jobs
EXCERPT: R&D Engineering Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: R&D Engineering Save R&D Engineering, Principal Engineer Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17222 Save R&D Engineering, Sr Engineer Noida, India Category: Engineering Posted: 04/12/2026 Job ID: 16737 Save R&D Engineering, Staff Engineer (C/C++, Data Structures, Algorithm, RTL compiler) Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 17265 Save Senior Staff R&D Engineer - C/C++, System-level programming, Unix/Linux, Cryptographic algorithms, perl, python Bengaluru, India Category: Engineering Posted: 04/27/2026 Job ID: 16970 Save Senior Staff Software Engineer Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 16969 Save R&D Engineering, Staff Engineer (Fusion Compiler GPU Acceleration) Sunnyvale, California Category: Engineering Posted: 05/03/2026 Job ID: 17296 Save Firmware Development Engineer Noida, India Category: Engineering Posted: 05/01/2026 Job ID: 17239 Save R&D Engineering, Sr Engineer ( GUI, PyQt, Python) Pune, India Category: Engineering Posted: 04/29/2026 Job ID: 16892 Save Lead Software
---
TITLE: Benefits (Opens in new window)
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://www.synopsys.com/careers/benefits.html
EXCERPT: Benefits (Opens in new window) Synopsys Benefits Why Synopsys Solutions Products Support & Training Resources Search Synopsys.com Contact Sales Contact Sales Search Synopsys Cancel Popular Content Innovate Faster with Synopsys Multi-Die Solution Explore our eBook for scalable multi-die solutions to boost innovation, productivity, and success. Automotive Executive Guide: Rethinking Automotive Development A guide to virtualization in software-defined vehicles for automotive leaders. Mastering AI Chip Complexity This eBook explores AI chip design trends, challenges, and strategies for first-pass silicon success. Back Our Company Careers Ecosystem Partners Global Offices Investors Leadership Responsible Business × Why Synopsys? Our Technology, Your Innovation™. Trusted industry leader. Learn more Industry Aerospace & Government AI Chip Development Automotive Edge AI HPC & Data Center Mobile Technology Artificial Intelligence Cloud Electronics Digital Twins Energy-Efficient SoCs Multi-Die Photonics & Optics Navigating Software-Defined Vehicle Development Discover strategies to boost SDV innovation, reduce costs, and enhance reliability. Download By Function Analog Design Digital Design Design for Test Verification Virtual Prototyping Hardware Assisted Verification Signoff Silicon Lifecycle Management Manufacturing SoC Integration View all Products Synopsys.ai AI-enabled EDA Design, Automation, Insights AI-powered Optimization Design, Verification, Test, Analog AI-powered Analytics Design, Process Control, Production GenAI 24/7 Expert Copilot Agentic AI Multi-Agent Workflows EDA Fusion Compiler Synthesis & Implementation Custom Compiler Analog & Custom IC Design 3DIC Compiler Multi-die Design PrimeTime Design Signoff VCS Logic Simulation TestMAX IC Test IC Validator Physical Verification RedHawk-SC Digital Power Integrity Signoff System Platform Architect SoC Architecture Exploration ZeBu IC Emulation HAPS IC Prototyping Virtualizer Virtual Prototyping Synplify Complete
---
TITLE: 9 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/finance-jobs/44408/8675456/1
EXCERPT: 9 open roles Search Finance Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Finance Jobs Filtered by Save Revenue Recognition Staff Bengaluru, India Category: Finance Posted: 05/04/2026 Job ID: 15557 Save Financial Planning & Analysis, Principal Hillsboro, Oregon Category: Finance Posted: 04/28/2026 Job ID: 16887 Save Financial Planning and Analysis, Sr Staff Hyderabad, India Category: Finance Posted: 04/23/2026 Job ID: 16998 Save Stock Administration, Senior Associate - 15067 Sunnyvale, California Category: Finance Posted: 02/05/2026 Job ID: 15067 Save Payable Accountant, Ho Chi Minh city Ho Chi Minh City, Vietnam Category: Finance Posted: 04/08/2026 Job ID: 16872 Save Financial Planning & Analysis, Staff Bengaluru, India Category: Finance Posted: 04/20/2026 Job ID: 16918 Save Global Workplace & Real Estate Financial Planning & Analysis, Sr Staff Hillsboro, Oregon Category: Finance Posted: 04/05/2026 Job ID: 16640 Save IT Auditor, Sr Associate/Staff Bengaluru, India Category: Finance Posted: 03/05/2026 Job ID: 15976 Save Revenue Accounting Manager Bengaluru, India Category: Finance Posted:
---
TITLE: Stay safe and know the signs of recruitment fraud.
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/UnderstandingRecruitmentFraud
EXCERPT: Stay safe and know the signs of recruitment fraud. Understanding Recruitment Fraud | Synopsys Skip to main content Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Understanding Recruitment Fraud Stay Safe At Synopsys, we understand that the job search process can be both exciting and overwhelming. Unfortunately, with the rise of fraudulent recruiting tactics, it's important to stay vigilant and informed. We genuinely care about your experience and want to ensure that your journey with us is safe and secure. We take the hiring process very seriously and value the time and effort of every candidate. Our official processes are designed to protect your privacy and provide a transparent recruitment experience. Know the Signs To help you navigate this landscape, here are some red flags to watch out for when considering job offers: Email Domain If you receive communication from an email address that does not end in @synopsys.com, it's a warning sign. Communication Methods Be cautious if your interactions are limited to online messaging or social media without any live conversations via Zoom or face-to-face
---
TITLE: 12 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/information-technology-jobs/44408/8738528/1
EXCERPT: 12 open roles Search Information Technology Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Information Technology Jobs Filtered by Save Site Reliability, Sr Associate Seongnam-si, South Korea Category: Information Technology Posted: 04/28/2026 Job ID: 17208 Save Salesforce Developer Bengaluru, India Category: Information Technology Posted: 04/16/2026 Job ID: 16609 Save Principal Site Reliability Engineer Sunnyvale, California Category: Information Technology Posted: 04/11/2026 Job ID: 16495 Save SAP ABAP Developer Hyderabad, India Category: Information Technology Posted: 04/09/2026 Job ID: 16832 Save Site Reliability AI - Staff Bengaluru, India Category: Information Technology Posted: 04/06/2026 Job ID: 16668 Save Principal IT Security Architect Austin, Texas Category: Information Technology Posted: 03/30/2026 Job ID: 16261 Save IT Director - Infrastructure Engineering Bengaluru, India Category: Information Technology Posted: 03/01/2026 Job ID: 15412 Save IT Security Staff Bengaluru, India Category: Information Technology Posted: 02/25/2026 Job ID: 15374 Save Sr. Network Architect - Datacenter, Automation, Cloud Sunnyvale, California Category: Information Technology Posted: 02/23/2026 Job ID:
---
TITLE: 6 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/operations-jobs/44408/8675728/1
EXCERPT: 6 open roles Search Operations Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Operations Jobs Filtered by Save Senior Manufacturing Planner & CM Management Sunnyvale, California Category: Operations Posted: 04/23/2026 Job ID: 16746 Save Senior Business Analyst Porto Salvo, Portugal Category: Operations Posted: 03/09/2026 Job ID: 15972 Save Director, Business Applications Product Owner Porto Salvo, Portugal Category: Operations Posted: 04/09/2026 Job ID: 16733 Save Senior Business Process Management Porto Salvo, Portugal Category: Operations Posted: 03/24/2026 Job ID: 16602 Save Principal Engineer - Manufacturing Process/Electronic Assemblies Rungis, France Category: Operations Posted: 03/08/2026 Job ID: 15988 Save Business Process Management, Sr Staff Tokyo, Japan Category: Operations Posted: 02/25/2026 Job ID: 15427 Filter Results Refine by Keyword Add Category Consulting (1) Customer Application Services (1) Engineering (566) Finance (9) General Management (11) Information Technology (12) Interns/Temp (28) Legal (4) Marketing (3) Operations (6) People (6) Product Management (13) Sales (46) Sales Enablement (3) Strategic Planning and Corp Dev
---
TITLE: USA 149 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-usa
EXCERPT: USA 149 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: United States Save Technical Writing Internship Canonsburg, Pennsylvania Category: Interns/Temp Posted: 03/29/2026 Job ID: 16253 Save Strategic Engagements Manager United States Off-site Category: Sales Enablement Posted: 05/04/2026 Job ID: 17161 Save Director of Sales Account Management (Foundry) Sunnyvale, California Category: Sales Posted: 05/03/2026 Job ID: 17272 Save Insider Threat Analyst Austin, Texas Category: Engineering Posted: 05/03/2026 Job ID: 17218 Save Software Testing Engineering Internship Canonsburg, Pennsylvania Category: Interns/Temp Posted: 05/03/2026 Job ID: 17288 Save Channel Global Campaigns Manager United States Off-site Category: Marketing Posted: 05/03/2026 Job ID: 17231 Save Director Applications Engineering Sunnyvale, California Category: Engineering Posted: 04/09/2026 Job ID: 16880 Save Technical Support Engineer, Electronics Thermal Canonsburg, Pennsylvania Category: Customer Application Services Posted: 05/03/2026 Job ID: 17209 Save R&D Engineering, Staff Engineer (Fusion Compiler GPU Acceleration) Sunnyvale, California Category: Engineering Posted: 05/03/2026 Job ID: 17296 Save
---
TITLE: 566 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/engineering-jobs/44408/8675488/1
EXCERPT: 566 open roles Search Engineering Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Engineering Jobs Filtered by Save Principal Engineer, DDR/LPDDR/PHY Systems- 15193 Nepean, Canada Category: Engineering Posted: 02/17/2026 Job ID: 15193 Save Staff, Analog Mixed Signal Layout Design and Methodology Engineer-16944 Markham, Canada Category: Engineering Posted: 05/03/2026 Job ID: 16944 Save System design & Validation, Principal Engineer- 15024 Mississauga, Canada Category: Engineering Posted: 01/29/2026 Job ID: 15024 Save ASIC Physical Design, Sr Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 17079 Save Senior Applications Engineer / Erfahrener Applikationsingenieur Munich, Germany Category: Engineering Posted: 03/22/2026 Job ID: 15553 Save R&D Engineering, Principal Engineer Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17222 Save ASIC Digital Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 16849 Save Senior Applications Engineer-EDA Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17252 Save Senior Pre/Post-Silicon Validation Engineer Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID:
---
TITLE: 3 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/marketing-jobs/44408/8675712/1
EXCERPT: 3 open roles Search Marketing Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Marketing Jobs Filtered by Save Channel Global Campaigns Manager United States Off-site Category: Marketing Posted: 05/03/2026 Job ID: 17231 Save Field Marketing Manager (High-Tech) United States Off-site Category: Marketing Posted: 04/30/2026 Job ID: 17230 Save Director, Field Marketing Germany Off-site Category: Marketing Posted: 04/28/2026 Job ID: 17275 Filter Results Refine by Keyword Add Category Consulting (1) Customer Application Services (1) Engineering (566) Finance (9) General Management (11) Information Technology (12) Interns/Temp (28) Legal (4) Marketing (3) Operations (6) People (6) Product Management (13) Sales (46) Sales Enablement (3) Strategic Planning and Corp Dev (1) Workplace Resources (1) Sub Category Channel Marketing (1) Field Marketing (2) Remote Eligible Yes (3) JobRefID 17230 (1) 17231 (1) 17275 (1) Sub Category Search GTM (2) AJDType Employee (3) Country Germany (1) United States (2) State California (1) Land Berlin (1) Pennsylvania (1) City Berlin (1) Canonsburg
---
TITLE: Find out more
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/be-excellent-here
EXCERPT: Find out more Be Excellent Here Skip to main content Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Be Excellent Here Breakthrough moments happen when talented people of every background feel valued and supported to do their best work. Play Video At Synopsys, we know that when people of different nationalities, backgrounds, genders, and generations come together to collaborate and share their unique perspectives, innovation flourishes . Find Your Career We want to make one thing clear Your individual excellence isn't just welcomed - it's essential Here at Synopsys, you can: Be Yourself Be Yourself We want everyone to be able to be their best selves at work. Our culture is built on trust and respect, fostering genuine connections, and enabling everyone to contribute and be recognized. Be Valued Be Valued Your dedication deserves our attention. We're building a workplace where your distinct skills and perspectives aren't just acknowledged-they're actively sought out to drive innovation and help shape our future. Be Excellent Be Excellent Your unique brilliance drives our excellence. We've created an environment where exceptional
---
TITLE: 28 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/interns-temp-jobs/44408/8675664/1
EXCERPT: 28 open roles Search Interns/Temp Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Interns/Temp Jobs Filtered by Save Technical Writing Internship Canonsburg, Pennsylvania Category: Interns/Temp Posted: 03/29/2026 Job ID: 16253 Save Software Testing Engineering Internship Canonsburg, Pennsylvania Category: Interns/Temp Posted: 05/03/2026 Job ID: 17288 Save Analog and Mixed Signal Design Apprenticeship Noida, India Category: Interns/Temp Posted: 03/24/2026 Job ID: 15366 Save GenAI Platform Apprenticeship Hyderabad, India Category: Interns/Temp Posted: 04/15/2026 Job ID: 16729 Save AI/ML Engineering Internship Mississauga, Canada Category: Interns/Temp Posted: 04/30/2026 Job ID: 17242 Save Quantum Algorithms Development Internship Canonsburg, Pennsylvania Category: Interns/Temp Posted: 04/29/2026 Job ID: 17258 Save Physics AI Internship United States Off-site Category: Interns/Temp Posted: 04/29/2026 Job ID: 17256 Save AI-Assisted Analog EDA Engineering Internship Hsinchu, Taiwan Category: Interns/Temp Posted: 04/27/2026 Job ID: 17232 Save FC PV Internship - AI Driven Runtime Validation Hsinchu, Taiwan Category: Interns/Temp Posted: 04/27/2026 Job ID: 17207 Save Applications Engineering Intern - 16520 United States
---
TITLE: DevOps Specialist
EMPLOYER: Vodafone Group
LOCATION: Bucuresti, Bucuresti, Romania (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696611136
EXCERPT: DevOps Specialist Bucuresti, Bucuresti, Romania
---
TITLE: DevOps Service Engineer - MCCM
EMPLOYER: Vodafone Group
LOCATION: Ankara, Ankara, Türkiye (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696546238
EXCERPT: DevOps Service Engineer - MCCM Ankara, Ankara, Türkiye
---
TITLE: DevOps Specialist
EMPLOYER: Amdocs
LOCATION: Cyprus- Limassol (Amdocs Site) (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://amdocs.eightfold.ai/careers/job/563431012641581
EXCERPT: DevOps Specialist Cyprus- Limassol (Amdocs Site)
---
TITLE: DevOps Engineer
EMPLOYER: Vodafone Group
LOCATION: Budapest, Hungary (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018687386512
EXCERPT: DevOps Engineer Budapest, Hungary
---
TITLE: DevOps Engineer-VOIS
EMPLOYER: Vodafone Group
LOCATION: Giza, Egypt (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696837290
EXCERPT: DevOps Engineer-VOIS Giza, Egypt
---
TITLE: Systems Engineer / DevOps
EMPLOYER: Hive
LOCATION: Seattle (unspecified)
SALARY: $120K-$180K
POSTED: 2022-04-21
APPLY_URL: https://jobs.lever.co/hive/efb68714-6896-4987-8d12-f06622323b2a
EXCERPT: Systems Engineer / DevOps Seattle About Hive Hive is the leading provider of cloud-based AI solutions to understand, search, and generate content, and is trusted by hundreds of the world's largest and most innovative organizations. The company empowers developers with a portfolio of best-in-class, pre-trained AI models, serving billions of customer API requests every month. Hive also offers turnkey software applications powered by proprietary AI models and datasets, enabling breakthrough use cases across industries. Together, Hive's solutions are transforming content moderation, brand protection, sponsorship measurement, context-based ad targeting, and more. Hive has raised over $120M in capital from leading investors, including General Catalyst, 8VC, Glynn Capital, Bain & Company, Visa Ventures, and others. We have over 250 employees globally in our San Francisco, Seattle, and Delhi offices. Please reach out if you are interested in joining the future of AI! DevOps and Systems Team Our unique machine learning needs led us to open our own data centers, with an emphasis on GPU resources. Even with these data centers, we maintain a hybrid infrastructure into AWS to power some parts of our consumer apps. As we continue to commercialize our machine learning models, we also need to grow our DevOps and Systems team to maintain the reliability of a SaaS offering for our customers. Our ideal candidate is someone who is able to thrive in an unstructured environment and takes automation seriously. You believe there is no task that can't be automated and no server scale too large. You take pride
---
TITLE: Senior Database DevOps Engineer
EMPLOYER: SumUp
LOCATION: Sofia, Bulgaria (unspecified)
SALARY: Not disclosed
POSTED: 2026-04-07
K401_MATCH: yes (not source-backed)
MENTAL_HEALTH_SUPPORT: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://sumup.com/careers/positions/8482964002?gh_jid=8482964002
EXCERPT: Senior Database DevOps Engineer Sofia, Bulgaria SumUp is looking for a Senior Database DevOps Engineer to join our team in Sofia. In this role, you will develop and maintain the Cloud Platform infrastructure related to databases that serves as the foundation for our development teams. You will play a critical part in ensuring the availability, performance, and security of our databases by implementing automation and improving infrastructure code quality. We are looking for an expert who can help us shift database ownership "left" safely through standardized automation and deep-level guardrails. You will collaborate closely with Platform Infrastructure and Development teams to lower costs, improve self-service tooling, and actively participate in audits related to our database infrastructure. About the team The DBOps team sits within SumUp's Platform tribe and is responsible for the database infrastructure that underpins payment and financial products used by over 4 million businesses worldwide. The team is at a pivotal moment: migrating 80+ legacy databases to Aurora PostgreSQL, building deep-level guardrails, and shifting database ownership closer to the development teams who rely on it daily. This role is central to that work, bringing platform engineering discipline, automation-first thinking, and database expertise to a function where the impact is felt across the entire engineering organisation. 👉 Take a look at our Sofia offic... What you'll do - Build and maintain Cloud Platform database infrastructure that development teams across SumUp depend on for reliability, performance, and security - Lead the migration of legacy RDS databases to Aurora PostgreSQL, contributing
---
TITLE: Senior Data Software Engineer (Python & PySpark) - Vice President
EMPLOYER: Citigroup Inc.
LOCATION: SINGAPORE, Singapore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859034899355
EXCERPT: Senior Data Software Engineer (Python & PySpark) - Vice President SINGAPORE, Singapore
---
TITLE: PySpark Big Data Senior Developer - Vice President
EMPLOYER: Citigroup Inc.
LOCATION: MISSISSAUGA, Ontario, Canada (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859034961625
EXCERPT: PySpark Big Data Senior Developer - Vice President MISSISSAUGA, Ontario, Canada
---
TITLE: Senior DFT Engineer (Einfochips)
EMPLOYER: Arrow Financial CORP
LOCATION: US-AZ-Arizona (Remote Employees) (remote)
SALARY: Not disclosed
POSTED: 2026-05-24
K401_MATCH: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
HIRE_STATES: AZ
APPLY_URL: https://arrow.wd1.myworkdayjobs.com/AC/job/US-AZ-Arizona-Remote-Employees/Senior-DFT-Engineer--Einfochips-_R243606
EXCERPT: Senior DFT Engineer (Einfochips) US-AZ-Arizona (Remote Employees) Position: Senior DFT Engineer (Einfochips) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options
---
TITLE: Backend Engineer - POS
EMPLOYER: SumUp
LOCATION: Berlin, Germany (unspecified)
SALARY: Not disclosed
POSTED: 2026-03-04
K401_MATCH: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://sumup.com/careers/positions/8427119002?gh_jid=8427119002
EXCERPT: Backend Engineer - POS Berlin, Germany SumUp's Point-of-Sale (POS) solution empowers cafes, shops, bars, hair salons, and other businesses to operate efficiently and grow. It offers a wide range of features, including product catalogs, inventory management, business analytics, compliance support, and loyalty tools. As a Backend Engineer in the Orders & Sales or Catalog Platform team, you will build the engine powering core infrastructure for over 4 million businesses worldwide. Whether you are architecting global sales APIs or scaling item management systems, your work is central to the SumUp ecosystem. The Orders & Sales team builds high-performance APIs and receipt engines that unify transaction and sales data, utilizing an AI-native mindset and extreme collaboration. Meanwhile, the Catalog Platform team owns the backend for item management, variants, categories, and taxes, focusing on high-stakes reliability and core POS infrastructure scaling. What you'll do - Develop and evolve high-performance backend services and APIs using Kotlin and Spring Boot . - Design and maintain robust data schemas and event-driven integrations (Kafka) to handle complex transaction and catalog data at scale. - Write clean, well-tested, production-grade code and contribute meaningfully to code reviews and team rituals. - Collaborate with mobile and product teams to ship end-to-end features with a focus on performance and data consistency. - Engage in daily pair programming to solve complex concurrency challenges and maintain high architectural standards. - Take full ownership of the development lifecycle, including managing CI/CD pipelines and monitoring service health in production. - Actively use and experiment with
---
TITLE: Design For Test Engineer (Einfochips Inc)
EMPLOYER: Arrow Electronics
LOCATION: San Jose, California, United States of America (unspecified)
SALARY: Not disclosed
POSTED: 2026-04-24
K401_MATCH: yes (not source-backed)
APPLY_URL: https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497/apply
EXCERPT: Design For Test Engineer (Einfochips Inc) San Jose, California, United States of America Embrace the role of a Design for Test Engineer and drive innovation in semiconductor design. Leverage your expertise in DFT, pattern simulation, and hardware debugging to support cutting-edge networking solutions. Collaborate with top engineers and work with advanced tools like Mentor Tessent and Synopsys. Shape the future of technology with us!
---
TITLE: Design For Test Engineer (Einfochips Inc)
EMPLOYER: Arrow Financial CORP
LOCATION: US-CA-Mountain View, California (Google) (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-31
K401_MATCH: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497
EXCERPT: Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health
---
TITLE: Design For Test Engineer IV (IC)
EMPLOYER: Arrow Financial CORP
LOCATION: US-CA-San Jose, California (unspecified)
SALARY: $112K-$170K
POSTED: 2026-05-20
K401_MATCH: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-San-Jose-California/Design-For-Test-Engineer-III--IC-_R242745
EXCERPT: Design For Test Engineer IV (IC) US-CA-San Jose, California Position: Design For Test Engineer IV (IC) Job Description: What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA)/Health
---
TITLE: ASIC Physical Design Engineer
EMPLOYER: Cisco
LOCATION: 2 Locations (unspecified)
SALARY: $136K-$195K
POSTED: 2026-05-25
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/ASIC-Physical-Design-Engineer_2011518
EXCERPT: ASIC Physical Design Engineer 2 Locations The application window is expected to close on: 05/29/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Acacia, part of Cisco, provides innovative silicon-based high-speed optical interconnect products to accelerate network scalability through advancements in performance, capacity, and cost. Our DSP ASICs, silicon photonic PICs, and coherent modules empower cloud and service providers to meet the fast-growing demand for data. We have assembled a team of cross-functional experts capable of solving the challenges of next-generation optical interconnects, resulting in industry-leading, award-winning products. Come join us at Cisco, named the #1 world's best workplaces, and do purposeful work that makes a global impact and gives back to a company culture that empowers an inclusive future for all. Your Impact As a Physical Design Engineer with Acacia, you will focus on the technical execution of high-performance ASIC designs. Working as an individual contributor, you will lead the RTL-to-GDSII implementation flow for advanced semiconductor nodes, ensuring that Acacia's networking platforms meet rigorous power, performance, and area (PPA) targets. You will be responsible for the successful delivery of assigned blocks from specification through to tapeout. Implement end-to-end RTL-to-GDSII implementation for advanced nodes (sub-7nm to 2nm) Perform hierarchical floor planning, place and route, and clock/power distribution Conduct static timing analysis (STA) and drive timing closure for multi-mode/multi-corner designs Lead the physical design of assigned blocks, ensuring quality and alignment to project timelines Develop
---
TITLE: ASIC Physical Design
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/asic-physical-design-jobs
EXCERPT: ASIC Physical Design Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: ASIC Physical Design Save ASIC Physical Design, Sr Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 17079 Save Principal ASIC Physical Design Engineer Bengaluru, India Category: Engineering Posted: 04/28/2026 Job ID: 17010 Save ASIC Physical Design, Sr Staff Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/28/2026 Job ID: 16727 Save ASIC Physical Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 04/27/2026 Job ID: 17243 Save ASIC Physical Design Senior Manager Bengaluru, India Category: Engineering Posted: 04/21/2026 Job ID: 17130 Save ASIC Physical Design, Staff Engineer Bengaluru, India Category: Engineering Posted: 04/19/2026 Job ID: 16869 Save Principal Physical Design Engineer - SerDes - 16976 Mississauga, Canada Category: Engineering Posted: 04/16/2026 Job ID: 16976 Save ASIC Physical Design, Sr Staff Engineer in HCMC or Da Nang Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/15/2026 Job
---
TITLE: Analog Design Engineering
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/analog-design-engineering-jobs
EXCERPT: Analog Design Engineering Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: Analog Design Save System design & Validation, Principal Engineer- 15024 Mississauga, Canada Category: Engineering Posted: 01/29/2026 Job ID: 15024 Save Analog Circuit Design, Sr Engineer in Da Nang Da Nang, Vietnam Category: Engineering Posted: 05/03/2026 Job ID: 17202 Save Analog Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 17055 Save Staff Analog/Mixed-Signal Design Engineer Porto Salvo, Portugal Category: Engineering Posted: 04/29/2026 Job ID: 17060 Save Principal or Senior Staff Analog Design Engineer Kanata, Canada Category: Engineering Posted: 04/28/2026 Job ID: 16079 Save Analog Design, Architect - 17009 Sunnyvale, California Category: Engineering Posted: 04/27/2026 Job ID: 17009 Save Advanced Packaging Design, Sr Staff Engineer - 13846 Sunnyvale, California Category: Engineering Posted: 04/26/2026 Job ID: 13846 Save Engineering Architect (Analog Mixed-Signal Architect) - 15195 Boxborough, Massachusetts Category: Engineering Posted: 04/26/2026 Job ID: 15195 Save Analog I/O Staff
---
TITLE: DevOps Engineer - Vice President
EMPLOYER: iCapital
LOCATION: Lisbon, Portugal (unspecified)
SALARY: Not disclosed
POSTED: 2026-02-27
APPLY_URL: https://job-boards.greenhouse.io/icapitalnetwork/jobs/8393349002
EXCERPT: DevOps Engineer - Vice President Lisbon, Portugal About the role This role is responsible for owning the performance, reliability, security, and operation of the company's SQL and NoSQL database platforms . The role operates within a database team who partners with application engineering, platform, and security teams to ensure databases are scalable, resilient, secure, and observable across all environments. Responsibilities Platform Performance & Scalability - Own end‑to‑end performance of SQL and NoSQL databases across environments, including query optimization, indexing strategies, execution plan analysis, and tuning of database runtime parameters (e.g., PostgreSQL query plans, MongoDB indexes, DynamoDB access patterns). - Proactively prevent performance regressions through representative load testing, performance analysis tooling, and CI/CD validation gates. - Partner with application teams on schema design, data modeling, and workload‑driven performance improvements , including relational schemas, document models, and NoSQL access patterns . Reliability, High Availability & Disaster Recovery - Design, operate, and harden production‑grade SQL, NoSQL, and document database systems with strong replication, failover, backup/restore, and security controls. - Define, implement, and validate backup and disaster recovery strategies, including routine restore testing and compliance with RPO/RTO objectives. Observability & Operational Excellence - Establish SLIs and SLOs for database health, including latency, error rates, contention, replication lag, storage growth, and cache efficiency across SQL & NoSQL databases . - Deliver actionable dashboards and alerts and maintain operational runbooks alongside up‑to‑date documentation. - Lead or participate in production incident response and post‑incident reviews related to database platforms. Security, Governance & Automation - Enforce database security
---
TITLE: Data DevOps Engineer
EMPLOYER: Versa Networks
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.jobvite.com/versa-networks/job/ov7UwfwM
EXCERPT: Data DevOps Engineer Data DevOps Engineer
---
TITLE: Canada 70 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-canada
EXCERPT: Canada 70 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: Canada Save Principal Engineer, DDR/LPDDR/PHY Systems- 15193 Nepean, Canada Category: Engineering Posted: 02/17/2026 Job ID: 15193 Save Staff, Analog Mixed Signal Layout Design and Methodology Engineer-16944 Markham, Canada Category: Engineering Posted: 05/03/2026 Job ID: 16944 Save System design & Validation, Principal Engineer- 15024 Mississauga, Canada Category: Engineering Posted: 01/29/2026 Job ID: 15024 Save Project Engineering Management, Principal Engineer- 16823 Ottawa, Canada Category: Engineering Posted: 04/22/2026 Job ID: 16823 Save AI/ML Engineering Internship Mississauga, Canada Category: Interns/Temp Posted: 04/30/2026 Job ID: 17242 Save Principal Engineer, IP Design Methodology & Quality-14704 Nepean, Canada Category: Engineering Posted: 02/03/2026 Job ID: 14704 Save Product Management, Director Ottawa, Canada Category: Product Management Posted: 04/30/2026 Job ID: 16950 Save AI Principal Software Engineer Canada Off-site Category: Engineering Posted: 04/29/2026 Job ID: 17201 Save Applications Engineering, Principal Engineer- 17051 Mississauga, Canada Category: Engineering Posted:
---
TITLE: Applications Engineering
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/applications-engineering-jobs
EXCERPT: Applications Engineering Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: Applications Engineering Save Senior Applications Engineer / Erfahrener Applikationsingenieur Munich, Germany Category: Engineering Posted: 03/22/2026 Job ID: 15553 Save Senior Applications Engineer-EDA Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17252 Save Applications Engineering, Sr Engineer Hsinchu, Taiwan Category: Engineering Posted: 05/03/2026 Job ID: 17310 Save Director Applications Engineering Sunnyvale, California Category: Engineering Posted: 04/09/2026 Job ID: 16880 Save Senior Applications Engineer-PDN/STA/ECO/PrimeTime/PrimeClosure/RHSC Noida, India Category: Engineering Posted: 05/03/2026 Job ID: 16928 Save Staff Application Engineer - Physical Implementation Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 17141 Save Product Engineer - HAV (Emulation/FPGA) Hsinchu, Taiwan Category: Engineering Posted: 01/26/2026 Job ID: 14114 Save Applications Engineering, Principal Engineer Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 17126 Save Applications Engineering, Principal Engineer Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 17057 Save Applications Engineering, Sr Staff Engineer - Static Timing
---
TITLE: DevOps Engineer
EMPLOYER: Amdocs
LOCATION: Indonesia- Jakarta (Customer Site) (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://amdocs.eightfold.ai/careers/job/563431012789778
EXCERPT: DevOps Engineer Indonesia- Jakarta (Customer Site)
---
TITLE: Armenia 13 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-armenia
EXCERPT: Armenia 13 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: Armenia Save ASIC Physical Design, Sr Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 17079 Save ASIC Digital Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 16849 Save Analog Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 17055 Save ASIC Physical Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 04/27/2026 Job ID: 17243 Save Analog Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 04/22/2026 Job ID: 17087 Save SoC Design and Verification Staff Engineer Yerevan, Armenia Category: Engineering Posted: 04/16/2026 Job ID: 16963 Save Project Engineering Manager Yerevan, Armenia Category: Engineering Posted: 03/23/2026 Job ID: 16483 Save DevOps Intern Yerevan, Armenia Category: Interns/Temp Posted: 04/13/2026 Job ID: 16964 Save HW Release Engineer Yerevan, Armenia Category: Engineering Posted: 04/07/2026 Job ID: 16506 Save RTL Design & Verification - Senior Staff
---
TITLE: India 231 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-india
EXCERPT: India 231 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: India Save Revenue Recognition Staff Bengaluru, India Category: Finance Posted: 05/04/2026 Job ID: 15557 Save R&D Engineering, Principal Engineer Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17222 Save Senior Applications Engineer-EDA Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17252 Save Senior Pre/Post-Silicon Validation Engineer Bengaluru, India Category: Engineering Posted: 05/04/2026 Job ID: 17268 Save Staff RTL Design Engineer Noida, India Category: Engineering Posted: 05/04/2026 Job ID: 17238 Save R&D Engineering, Sr Engineer Noida, India Category: Engineering Posted: 04/12/2026 Job ID: 16737 Save Senior Verification Manager - IP Development Noida, India Category: Engineering Posted: 05/04/2026 Job ID: 13453 Save Gen AI Staff Engineer Bengaluru, India Category: Engineering Posted: 01/21/2026 Job ID: 14124 Save R&D Engineering, Staff Engineer (C/C++, Data Structures, Algorithm, RTL compiler) Bengaluru, India Category: Engineering Posted: 05/03/2026 Job ID: 17265 Save Senior Staff R&D
---
TITLE: Cloud DevOps Engineer
EMPLOYER: Versa Networks
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.jobvite.com/versa-networks/job/olC4wfwh
EXCERPT: Cloud DevOps Engineer Cloud DevOps Engineer
---
TITLE: Portugal 26 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-portugal
EXCERPT: Portugal 26 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: Portugal Save Staff Analog/Mixed-Signal Design Engineer Porto Salvo, Portugal Category: Engineering Posted: 04/29/2026 Job ID: 17060 Save Technology Enablement Engineer Porto Salvo, Portugal Category: Engineering Posted: 04/28/2026 Job ID: 17092 Save ASIC Digital Design, Staff Engineer Porto Salvo, Portugal Category: Engineering Posted: 04/26/2026 Job ID: 17084 Save Lab Analog Design, Staff Engineer Porto Salvo, Portugal Category: Engineering Posted: 04/20/2026 Job ID: 17031 Save Technical Operations Lead Porto Salvo, Portugal Category: Engineering Posted: 04/23/2026 Job ID: 17100 Save Project Engineering Management, Staff Engineer Moreira, Portugal Category: Engineering Posted: 04/15/2026 Job ID: 16939 Save Analog Design, Staff Engineer Moreira, Portugal Category: Engineering Posted: 04/20/2026 Job ID: 17030 Save Senior Business Analyst Porto Salvo, Portugal Category: Operations Posted: 03/09/2026 Job ID: 15972 Save ASIC Digital Design Engineer, Staff Moreira, Portugal Category: Engineering Posted: 01/29/2026 Job ID: 14618 Save RF Analog
---
TITLE: DevOps Engineer - (m/f/d)
EMPLOYER: voize
LOCATION: Berlin | Remote | Hamburg | Munich | Frankfurt (remote)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.ashbyhq.com/voize/0e841b7c-ee61-484e-953c-546cdd3c775a
EXCERPT: DevOps Engineer - (m/f/d) Berlin | Remote | Hamburg | Munich | Frankfurt 🎤 WHY VOIZE? BECAUSE WE'RE MORE THAN JUST A JOB! At voize, we believe the greatest gift to frontline workers is time - time to care, connect, and be present. Today, that time is lost to busywork and complex systems that pull them away from what matters most: people. Our vision is to change that by building AI companions that seamlessly take over digital workflows. We don't replace humans with technology - we amplify their impact. Our mission is backed with a $50M Series A funding led by Balderton Capital, with support from HV Capital, Y Combinator and other leading VCs. Today, 2,000+ facilities trust voize, and over 200,000 users rely on our AI companion to ease their daily workload. As a dynamic team, we combine first-in-class technology with meaningful social impact. And now, we're looking for you to join us on this mission! 💡 YOUR MISSION: DELIGHT CUSTOMERS, OPTIMIZE PROCESSES! As DevOps Engineer, you will build and own voize's platform and infrastructure - from cloud and edge systems to ML data pipelines; ensuring our systems are secure, reliable, and compliant. You will enable product and ML teams to ship state-of-the-art healthcare AI with confidence to hospitals, care facilities, and mobile devices across Europe. 🚀 YOUR DAILY BUSINESS - NO TWO DAYS ARE ALIKE - Own and operate our Kubernetes clusters (AWS EKS production, bare-metal K3s for ML training, on-premises appliances running K3s) using GitOps (FluxCD) and
---
TITLE: DevOps Service Engineer - CCT
EMPLOYER: Vodafone Group
LOCATION: İstanbul, Istanbul, Türkiye (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696264577
EXCERPT: DevOps Service Engineer - CCT İstanbul, Istanbul, Türkiye
---
TITLE: Taiwan 34 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-taiwan
EXCERPT: Taiwan 34 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: Taiwan Save Applications Engineering, Sr Engineer Hsinchu, Taiwan Category: Engineering Posted: 05/03/2026 Job ID: 17310 Save Product Engineer - HAV (Emulation/FPGA) Hsinchu, Taiwan Category: Engineering Posted: 01/26/2026 Job ID: 14114 Save OPC Applications Engineer, Sr Staff Hsinchu, Taiwan Category: Engineering Posted: 04/29/2026 Job ID: 15260 Save AI-Assisted Analog EDA Engineering Internship Hsinchu, Taiwan Category: Interns/Temp Posted: 04/27/2026 Job ID: 17232 Save Applications Engineering, Staff Engineer_3DIC Hsinchu, Taiwan Category: Engineering Posted: 04/26/2026 Job ID: 17234 Save FC PV Internship - AI Driven Runtime Validation Hsinchu, Taiwan Category: Interns/Temp Posted: 04/27/2026 Job ID: 17207 Save Foundry Support, Sr Engineer Zhubei, Taiwan Category: Engineering Posted: 04/22/2026 Job ID: 17114 Save TestMAX Software Internship Hsinchu, Taiwan Category: Interns/Temp Posted: 04/23/2026 Job ID: 17167 Save Applications Engineering, Sr Staff Engineer Hsinchu, Taiwan Category: Engineering Posted: 04/21/2026 Job ID: 17118 Save Sales Account
---
TITLE: Devops Engineer - I
EMPLOYER: Netomi
LOCATION: Gurugram (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-07
APPLY_URL: https://jobs.lever.co/netomi/78ceaf47-c13a-4735-a2c6-d7301af7f3fc
EXCERPT: Devops Engineer - I Gurugram About the Company: Netomi is the leading agentic AI platform for enterprise customer experience. We work with the largest global brands like Delta Airlines, MetLife, MGM, United, and others to enable agentic automation at scale across the entire customer journey. Our no-code platform delivers the fastest time to market, lowest total cost of ownership, and simple, scalable management of AI agents for any CX use case. Backed by WndrCo, Y Combinator, and Index Ventures, we help enterprises drive efficiency, lower costs, and deliver higher quality customer experiences. Want to be part of the AI revolution and transform how the world's largest global brands do business? Join us! About the role: We are looking for a DevOps Engineer to work collaboratively with the software development team to deploy and operate the systems. You'll be responsible to ensure the system is running smoothly and is being monitored continuously to resolve issues. Responsibilities Requirements
---
TITLE: DevOps Consultant, Veeva Vault
EMPLOYER: Haleon
LOCATION: Bengaluru Campus 31, Bengaluru, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
APPLY_URL: https://careers.haleon.com/careers/job/563705891383282
EXCERPT: DevOps Consultant, Veeva Vault Bengaluru Campus 31, Bengaluru, India
---
TITLE: Python and PySpark Developer
EMPLOYER: Citigroup Inc.
LOCATION: Chennai, Tamil Nādu, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859035678337
EXCERPT: Python and PySpark Developer Chennai, Tamil Nādu, India
---
TITLE: CLOUD FINOPS ENGINEER - VOIS
EMPLOYER: Vodafone Group
LOCATION: Pune, Maharashtra, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696286713
EXCERPT: CLOUD FINOPS ENGINEER - VOIS Pune, Maharashtra, India
---
TITLE: Vietnam 38 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/jobs-in-vietnam
EXCERPT: Vietnam 38 open roles Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by Country: Vietnam Save Digital Verification Sr Staff Engineer/ Principal Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 05/04/2026 Job ID: 17204 Save Analog Circuit Design, Sr Engineer in Da Nang Da Nang, Vietnam Category: Engineering Posted: 05/03/2026 Job ID: 17202 Save Senior/Staff Design Verification Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/15/2026 Job ID: 16078 Save ASIC Physical Design, Sr Staff Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/28/2026 Job ID: 16727 Save ASIC Verification Engineer, Sr Staff Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/26/2026 Job ID: 16012 Save Staff Applications Engineer (Backend) Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/22/2026 Job ID: 17155 Save Payable Accountant, Ho Chi Minh city Ho Chi Minh City, Vietnam Category: Finance Posted: 04/08/2026 Job ID: 16872 Save ASIC Digital Verification Staff Engineer in
---
TITLE: 13 open roles
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/category/product-management-jobs/44408/8738496/1
EXCERPT: 13 open roles Search Product Management Jobs at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Product Management Jobs Filtered by Save Product Management, Director Ottawa, Canada Category: Product Management Posted: 04/30/2026 Job ID: 16950 Save Principal Technical Product Management Sunnyvale, California Category: Product Management Posted: 04/27/2026 Job ID: 15464 Save Technical Product Manager, Director United States Off-site Category: Product Management Posted: 04/27/2026 Job ID: 16930 Save Product Engineer, Icepak-17072 United States Off-site Category: Product Management Posted: 04/23/2026 Job ID: 17072 Save Product Management, Director Sunnyvale, California Category: Product Management Posted: 04/23/2026 Job ID: 16968 Save Developer Ecosystem - Staff Technical Program Manager United States Off-site Category: Product Management Posted: 04/21/2026 Job ID: 16741 Save Technical Product Management Architect - HAV AI Platform Strategy United States Off-site Category: Product Management Posted: 04/20/2026 Job ID: 15524 Save Senior Staff Product Manager, Ethernet IP Sunnyvale, California Category: Product Management Posted: 04/20/2026 Job ID: 16541 Save Technical Document Control and
---
TITLE: Sr. Partner Delivery Manager
EMPLOYER: Databricks
LOCATION: Singapore (unspecified)
SALARY: Not disclosed
POSTED: 2026-03-16
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
APPLY_URL: https://databricks.com/company/careers/open-positions/job?gh_jid=8458134002
EXCERPT: Sr. Partner Delivery Manager Singapore CSQ327R54 At Databricks we work on some of the most complex distributed processing and machine learning problems in the world and our customers challenge us with interesting new big data and AI use cases. You will shape the future of big data and the machine learning landscape for leading Fortune 500 organizations. Professional Services Delivery Partner Manager supports the mission of the Professional Services team, which is to accelerate and de-risk our customers' business outcomes through effective enablement and delivery of Databricks platform technology. This is an individual contributor role that will oversee the Databricks Delivery Partner Program which looks to use close partnerships with key system integrators to effectively co-deliver Databricks services engagements. The impact you will have: - You will work with the Professional Services team in order to use Databricks delivery partners to accelerate our customer project outcomes . - Build and develop Professional Services relationships with Global System Integrators (GSIs), Regional System Integrators (RSIs), regional Partner team to support bi-directional pipeline review and bi-directional engagements (subcontracting, and advisory) for company priorities. - Build a RFP process to support Partner Selection for large complex multi year, multi phase migration deals. Create templates, scorecards to supplement partner selection with a data driven approach. - Spearhead and lead efforts to incubate and ramp new partners with Gen AI capabilities. - Drive MBRs and QBRs with priority partners , and develop long term roadmaps for PS Partner delivery priorities. Develop scorecards and feedback loops to
---
TITLE: DevOps Engineer - Senior Vice President
EMPLOYER: iCapital
LOCATION: New York, New York, United States (unspecified)
SALARY: $180K-$230K
POSTED: 2026-02-18
APPLY_URL: https://job-boards.greenhouse.io/icapitalnetwork/jobs/8390699002
EXCERPT: DevOps Engineer - Senior Vice President New York, New York, United States About the Role The Platform Infrastructure team at iCapital plays a critical role in ensuring that both production and development environments operate smoothly, securely, and reliably. This role leverages advanced cloud capabilities to support the Platform Infrastructure strategy of market agility and lean operating principles, with a strong emphasis on quality to meet the ever‑growing demands of our clients. We are seeking highly collaborative, creative, and intellectually curious MLOps/DevOps Engineers with deep expertise in machine learning operations, cloud infrastructure, CI/CD automation, Kubernetes, and security. This role requires hands‑on experience designing, building, and operating scalable DevOps and enterprise‑grade MLOps platforms, including model lifecycle automation, observability, and governance. As a Platform Engineer, you will wear multiple hats in a highly visible role, partnering closely with engineering, security, data, and business teams to deliver secure, reliable, and highly automated platforms that support both application and machine‑learning workloads. Responsibilities - Design, build, and operate MLOps pipelines supporting the full ML lifecycle (training, validation, deployment, monitoring). - Enable production workloads for AI/ML and Generative AI systems, including LLM‑based services. - Develop and maintain CI/CD pipelines for AI/ML services and supporting infrastructure. - Build and manage cloud‑native infrastructure on AWS, with heavy use of Kubernetes and containerized workloads. - Automate infrastructure provisioning and configuration using Infrastructure as Code (Terraform). - Implement model versioning, experiment tracking, and artifact management across environments. - Ensure reliability, scalability, observability, and cost efficiency of AI platforms. - Partner with
---
TITLE: ASIC Digital Design
EMPLOYER: Synopsys
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: no (not source-backed)
APPLY_URL: https://careers.synopsys.com/asic-digital-design-jobs
EXCERPT: ASIC Digital Design Search our Job Opportunities at Synopsys Skip to main content Skip to Search Results Skip to Search Filters Join our Talent Community! Click here . Stay safe and know the signs of recruitment fraud. Career Areas Software Engineering Applications Engineering ASIC Digital Design ASIC Physical Design Analog Design Engineering R&D Engineering Sales Account Management Locations (Opens in new window) Early Careers Life at Synopsys (Opens in new window) Benefits (Opens in new window) EN Saved Jobs Search Jobs 0 Saved Jobs Engineer the Future with Us We currently have 711 open roles Search Jobs Find Jobs For Where? Search Jobs Sort Jobs Most Relevant Most Recent Filtered by CareerAreas: ASIC Digital Design Save Principal Engineer, DDR/LPDDR/PHY Systems- 15193 Nepean, Canada Category: Engineering Posted: 02/17/2026 Job ID: 15193 Save ASIC Digital Design, Staff Engineer Yerevan, Armenia Category: Engineering Posted: 05/04/2026 Job ID: 16849 Save Digital Verification Sr Staff Engineer/ Principal Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 05/04/2026 Job ID: 17204 Save Senior/Staff Design Verification Engineer Ho Chi Minh City, Vietnam Category: Engineering Posted: 04/15/2026 Job ID: 16078 Save Staff RTL Design Engineer Noida, India Category: Engineering Posted: 05/04/2026 Job ID: 17238 Save Senior Verification Manager - IP Development Noida, India Category: Engineering Posted: 05/04/2026 Job ID: 13453 Save Principal Engineer, IP Design Methodology & Quality-14704 Nepean, Canada Category: Engineering Posted: 02/03/2026 Job ID: 14704 Save ASIC Digital Design, Architect Dublin, Ireland Category: Engineering Posted: 03/12/2026 Job ID: 16210 Save ASIC Digital Design, Principal Engineer Dublin,
---
TITLE: DevOps Engineer
EMPLOYER: Torq
LOCATION: Tel Aviv (unspecified)
SALARY: Not disclosed
POSTED: 2026-02-23
APPLY_URL: https://job-boards.greenhouse.io/torq/jobs/5810373004
EXCERPT: DevOps Engineer Tel Aviv Skeletons, lasers, tattoo buses - the Torq brand grabs attention like nothing else in cybersecurity. And we're growing like crazy, backed by Series D funding, 200% employee growth, and 300% revenue growth. Fueling Torq's momentum is our game-changing AI SOC platform, backed by a team and culture that makes Torq one of Forbes' Best Startup Employers in America, and a Business Insider 'startup to bet your career on'. Life at Torq is all gas, no brakes. We're a team of relentless, collaborative go-getters pushing the boundaries of what's possible for security automation. Every role is an essential driver of Torq's success as the AI-native autonomous SecOps platform of choice for security teams across the Fortune 500. We are looking for a DevOps Engineer to join our fast growing company and in a breakthrough stage where we build our dream team with the most passionate and professional people in the industry. Our team thinks differently and quickly, delivering high quality and innovative solutions with the latest technologies and frameworks. And we never forget to enjoy the ride along the way! What You'll Be Doing: - Championing DevOps culture: Identify friction points and implement scalable automation to improve reliability, delivery speed, and developer experience. - Operating and optimizing production environments: Leverage infrastructure as code and modern observability tools to ensure stability and performance. - Empowering R&D: Build intuitive internal tools that foster a self-service culture and enable teams to own their operational workflows. - Leading deployment lifecycles: Drive
---
TITLE: ASIC Engineer
EMPLOYER: Jane Street Group, LLC
LOCATION: London, England, United Kingdom (unspecified)
SALARY: Not disclosed
POSTED: 2025-10-29
K401_MATCH: yes (not source-backed)
APPLY_URL: https://job-boards.greenhouse.io/janestreet/jobs/8233259002
EXCERPT: ASIC Engineer London, England, United Kingdom About the Position We are looking to hire an experienced ASIC Engineer to help us design, test and deploy advanced hardware designs. As part of our Ultra Low Latency team, you'll have the opportunity to collaborate with people in areas across the firm, including trading, networking and research infrastructure. We are looking for someone who can contribute to all of our projects and be happy to work on both FPGA-based and ASIC-based technologies. We're big believers in the ability of tools to improve the productivity, reliability and day-to-day joy of hardware engineering. That's why we created Hardcaml, a hardware development toolchain embedded in OCaml. We don't expect you to know OCaml (we'll teach you here), but we are looking for hardware engineers who are excited about the advantages that better tools can bring, and are willing to try new things as a result. About You - Have 4+ years practical experience in RTL design and verification - Experienced in ASIC design using either Synopsys or Cadence flows, including at least one of the following: - Front-end RTL design and synthesis - Back-end physical design - Verification (including formal) - Interested in using software engineering techniques to improve the hardware design process, and experience programming in some high-level languages (Python, C++, Java, Haskell, etc.) - Fluent in English If you're a recruiting agency and want to partner with us, please reach out to agency-partnerships@janestreet.com.
---
TITLE: VP of Partnerships and Network Development - Remote
EMPLOYER: Thriveworks
LOCATION: 2 Locations (remote)
SALARY: Not disclosed
POSTED: 2026-05-28
APPLY_URL: https://thriveworks.wd5.myworkdayjobs.com/Thriveworks/job/US---Remote/VP-of-Care-Partnerships---Remote_JR101049
EXCERPT: VP of Partnerships and Network Development - Remote 2 Locations posted: Posted 15 Days Ago
---
TITLE: Data Engineering Python and Pyspark - Assistant Vice President
EMPLOYER: Citigroup Inc.
LOCATION: CHENNAI, Tamil Nādu, India | PUNE, Mahārāshtra, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859035490067
EXCERPT: Data Engineering Python and Pyspark - Assistant Vice President CHENNAI, Tamil Nādu, India | PUNE, Mahārāshtra, India
---
TITLE: Physical Design Group Leader
EMPLOYER: Cisco
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Caesarea-Israel/Physical-Design-Group-Leader_2009634
EXCERPT: Physical Design Group Leader 2 Locations Cisco Silicon One is seeking a Physical Design Group Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As the Physical Design Group Leader, you will provide strategic and technical leadership to a team of engineers, guiding them through the entire chip design lifecycle. You will be responsible for the group's output, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Qualifications · A VLSI Design with extensive experience in backend design · B.Sc./M.Sc. in Electrical Engineering. · Strong understanding of Place & Route flow. · 10+ years of hands-on experience in a relevant domain · 4+ years of proven Management or Technical Leadership experience. Preferred Qualifications · Deep understanding of all aspects of Physical construction and Integration. · Knowledge in Physical Design Verification methodology LVS/DRC. · Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). #li-as6 Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly
---
TITLE: Experienced PCB Design Engineer
EMPLOYER: Renesas Electronics
LOCATION: Ho Chi Minh, , Vietnam (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/RenesasElectronics/744000130992933--experienced-pcb-design-engineer
EXCERPT: Experienced PCB Design Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: - Extract S-parameters (Touchstone format) and RLC ladder models from design data using electromagnetic analysis tools (Ansys HFSS and SIwave) - Perform simulations with a sim tool (Synopsys HSPICE) - Design board (.brd) and package (.mcm) data using a design tool (Cadense Allegro)- Create schematics using Cadense OrCAD (optional) Qualifications: - Hands-on expertise with Ansys HFSS, Ansys SIwave, and Synopsys HSPICE - Strong understanding of: Signal Integrity (SI); and Power Integrity (PI) - High-speed interconnect modeling - Ability to interpret design data and convert it into meaningful electrical models - Experience with Cadence Allegro for board and package design - Familiarity with .brd and .mcm file formats - Experience with Cadence OrCAD schematic capture -Strong problem solving mindset and ability to work in fast-paced environment. -Good communication skills, ability to cooperate with other teams. - Ability to communicate in Japanese is a plus. Additional Information: We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for
---
TITLE: RevOps Analyst (Analytics)
EMPLOYER: Cohere Health
LOCATION: New York | San Francisco | Toronto (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.ashbyhq.com/cohere/cd3eacfe-1169-4df0-8164-93a857d5ddf0
EXCERPT: RevOps Analyst (Analytics) New York | San Francisco | Toronto Who are we? Our mission is to scale intelligence to serve humanity. We're training and deploying frontier models for developers and enterprises who are building AI systems to power magical experiences like content generation, semantic search, RAG, and agents. We believe that our work is instrumental to the widespread adoption of AI. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. We like to work hard and move fast to do what's best for our customers. Cohere is a team of researchers, engineers, designers, and more, who are passionate about their craft. Each person is one of the best in the world at what they do. We believe that a diverse range of perspectives is a requirement for building great products. Join us on our mission and shape the future! RevOps Analyst (Analytics) Department: Revenue Operations Function: GTM Analyst, Analytics Location: NYC, SF, Toronto The Revenue Operations team's mission is to build and maintain the systems, data, and processes that power our go-to-market engine. We are looking for a RevOps Analyst, Analytics to join the team, reporting to the Head of Revenue Operations, focused on partnering with the business to deliver insight to drive measurable revenue growth and operational impact. In this role you may: - Partner with GTM leadership to elevate reporting, systems and process to drive revenue growth
---
TITLE: DevOps Senior Programmer - Assistant Vice President
EMPLOYER: Citigroup Inc.
LOCATION: PUNE, Mahārāshtra, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859034859531
EXCERPT: DevOps Senior Programmer - Assistant Vice President PUNE, Mahārāshtra, India
---
TITLE: Analog Design Engineer, Staff
EMPLOYER: d-Matrix
LOCATION: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
SALARY: Not disclosed
POSTED: 2025-05-20
APPLY_URL: https://jobs.ashbyhq.com/d-matrix/baf4903f-0fff-4ad2-aa2b-8a56b104db5c
EXCERPT: Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up
---
TITLE: AI and Devops Technical Support Analyst
EMPLOYER: Citigroup Inc.
LOCATION: WARSAW, Poland (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859034978991
EXCERPT: AI and Devops Technical Support Analyst WARSAW, Poland
---
TITLE: Principal Engineer, ASIC Verification & Validation Engineering
EMPLOYER: SanDisk
LOCATION: Bengaluru, KA, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.smartrecruiters.com/Sandisk/744000129648389-principal-engineer-asic-verification-validation-engineering
EXCERPT: Principal Engineer, ASIC Verification & Validation Engineering Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: Role Overview The Platform Engineering organization is looking for a self-driven, hands-on engineer who can bridge the communication and skillset divide between firmware, silicon design, and hardware validation. Your primary responsibility will be supporting our advanced prototyping and emulation platforms, with a specific focus on end users. The ideal candidate has a broad, systems-level knowledge base, with deep technical expertise in platform bring-up, hardware/software co-verification, and high-density FPGA deployments. Duties
---
TITLE: Senior DevOps Engineer, Vice President
EMPLOYER: Citigroup Inc.
LOCATION: JERSEY CITY, New Jersey, United States of America | TAMPA, Florida, United States of America (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859035007618
EXCERPT: Senior DevOps Engineer, Vice President JERSEY CITY, New Jersey, United States of America | TAMPA, Florida, United States of America
---
TITLE: Physical Design Technical Leader
EMPLOYER: Cisco
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-07
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Caesarea-Israel/Physical-Design-Technical-Leader_2003308
EXCERPT: Physical Design Technical Leader 2 Locations Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Requirements A VLSI Design with extensive experience in backend design B.Sc./M.Sc. in Electrical Engineering. Strong understanding of Place & Route flow. 7+ years of hands-on experience in a relevant domain Preferred/Adva ntageous Qualifications Deep understanding of all aspects of Physical construction and Integration. Knowledge in Physical Design Verification methodology LVS/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. #li-as6 Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital
---
TITLE: Cellular SoC Static Timing Analysis Engineer
EMPLOYER: Apple
LOCATION: San Diego, United States of America (unspecified)
SALARY: $120K-$181K
POSTED: 2025-10-28
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200628423/cellular-soc-static-timing-analysis-engineer?team=HRDWR
EXCERPT: Cellular SoC Static Timing Analysis Engineer San Diego, United States of America Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, developed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple's custom silicon. You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product? As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of sophisticated SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple
---
TITLE: Associate CloudOps Engineer
EMPLOYER: Tyler Technologies
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.jobvite.com/tylertech/job/ovULzfwt
EXCERPT: Associate CloudOps Engineer Associate CloudOps Engineer
---
TITLE: ASIC Engineering Technical Leader- STA
EMPLOYER: Cisco
LOCATION: San Jose, California, US (unspecified)
SALARY: $211K-$305K
POSTED: 2026-06-08
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader--STA_2011055
EXCERPT: ASIC Engineering Technical Leader- STA San Jose, California, US The application window is expected to close on: 07/09/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Your Impact: Define, design and verify ASIC and ASIC subsystems to be deployed in a range of Cisco platforms. Contribute to a multi-disciplined engineering team to meet the power, performance, and area goals for products. Design, document, and develop ASIC subsystems for release in high volume and quality. Help define the process, methods, and tools for design and implementation of complex developments. What You'll Do: Oversees the definition, architecture and design of high performance ASICs Oversees all applications and code including methodology of reusable code Oversees code creation and determines methodology behind coding Consults for architecture and design decisions for complex areas Drives design solutions across the business Creates guidelines and standards Creates innovative verification strategies Oversees system level verification using test benches Ensures culture of code reviews and postmortems Architects and designs analog/mixed-signal circuits Reviews complex IC designs and makes recommendations for improvements Directs the mixed-signal team to define requirements, influences packaging and hardware team to ensure specifications are met Oversees all physical design functions bringing technical expertise to highly complex scenarios Interfaces with vendors and design leads on complex issues Drives different technology design rules to develop innovative packages Minimum Qualifications: Bachelor's with 10 years of related experience, or Master's with 5 years of related experience, or PhD with
---
TITLE: Partner Success Manager – Cloud, Security & Software
EMPLOYER: TD Synnex
LOCATION: Birkerod, Capital, Denmark (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-26
K401_MATCH: yes (not source-backed)
APPLY_URL: https://synnex.wd5.myworkdayjobs.com/tdsynnexcareers/job/Birkerod-Denmark/Partner-Success-Manager_R50685/apply
EXCERPT: Partner Success Manager – Cloud, Security & Software Birkerod, Capital, Denmark Vi søger en Partner Success Manager til at styrke vores relationer med partnere inden for Cloud, Security & Software. Du vil være ansvarlig for onboarding, support og træning, samt sikre en fremragende kundeoplevelse. Bliv en del af et globalt team i en førende teknologivirksomhed!
---
TITLE: ASIC DFT CAD Technical Leader
EMPLOYER: Cisco
LOCATION: San Jose, California, US (unspecified)
SALARY: $184K-$264K
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-DFT-CAD-Technical-Leader_2012616
EXCERPT: ASIC DFT CAD Technical Leader San Jose, California, US The application window is expected to close on: 07/24/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Who We Are: The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's revolutionary solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Key Responsibilities: Own and drive end-to-end DFT flow architecture. Build and maintain scalable DFT CAD infrastructure from RTL ‚ DFT insertion, ATPG, simulation, reporting. Develop robust regression frameworks (LSF/cluster-based) with job orchestration, monitoring, logging, and failure recovery. Lead AI-driven automation initiatives for log analysis, failure triage, regression optimization, and intelligent debug. Collaborate with RTL, Physical Design, and Validation teams to ensure seamless DFT integration and signoff. Define and track key metrics (coverage, pattern count, runtime, regression health) and build dashboards for visibility. Standardize flows, improve reusability, and
---
TITLE: FinOps Cloud (Azure & AWS)
EMPLOYER: Kyndryl
LOCATION: Madrid, Spain (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-05
K401_MATCH: yes (not source-backed)
APPLY_URL: https://kyndryl.wd5.myworkdayjobs.com/KyndrylProfessionalCareers/job/Madrid-Spain/FinOps-Cloud--Azure---AWS-_R-61804
EXCERPT: FinOps Cloud (Azure & AWS) Madrid, Spain posted: Posted 7 Days Ago
---
TITLE: Memory Design Engineer - SRAM / TCAM
EMPLOYER: Cisco
LOCATION: Zhubei, Taiwan (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410
EXCERPT: Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional
---
TITLE: DevOps Engineer (SIF, Orange team)
EMPLOYER: Thales
LOCATION: Bucharest, Romania (unspecified)
SALARY: Not disclosed
POSTED: 2025-12-16
K401_MATCH: yes (not source-backed)
APPLY_URL: https://thales.wd3.myworkdayjobs.com/Careers/job/Bucharest/DevOps-Engineer--SIF--Orange-team-_R0310115/apply
EXCERPT: DevOps Engineer (SIF, Orange team) Bucharest, Romania Join our team as a DevOps Engineer and work with cutting-edge technologies in a collaborative Agile environment. You'll implement CI/CD pipelines, automate processes with Ansible, and contribute to innovative solutions that impact global industries. If you're passionate about DevOps and cloud services, we want to hear from you!
---
TITLE: Senior CAD Engineer, ASIC Development Infrastructure, RTL Design
EMPLOYER: Amazon
LOCATION: Boise, Idaho, USA (unspecified)
SALARY: $159K-$215K
POSTED: 2026-02-23
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (not source-backed)
FERTILITY_FAMILY_BUILDING_BENEFITS: yes (not source-backed)
ADOPTION_ASSISTANCE_OFFERED: yes (not source-backed)
MENTAL_HEALTH_SUPPORT: yes (not source-backed)
CHILDCARE_SUBSIDY: yes (not source-backed)
APPLY_URL: https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design
EXCERPT: Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts
---
TITLE: Senior Java PySpark Developer – Assistant Vice President
EMPLOYER: Citigroup Inc.
LOCATION: PUNE, Mahārāshtra, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859034840475
EXCERPT: Senior Java PySpark Developer – Assistant Vice President PUNE, Mahārāshtra, India
---
TITLE: FinOps Practitioner
EMPLOYER: Cisco
LOCATION: 4 Locations (unspecified)
SALARY: $93K-$149K
POSTED: 2026-05-25
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/RTP-North-Carolina-US/FinOps-Practitioner_2010880
EXCERPT: FinOps Practitioner 4 Locations The application window is expected to close on: 05/15/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Splunk Cloud FinOps is dedicated to maximizing the business value of our cloud investments by driving financial accountability and optimizing cloud spend across the organization. We sit at the strategic intersection of engineering, finance, and business units, fostering deep collaboration to ensure efficient resource utilization, predictable cloud costs, and data-driven decision-making at scale. Our tight-knit team, comprised of a Scrum Master, an Engineering Team Lead, two Engineers, and two FinOps Practitioners, thrives on a culture of support, partnership, and innovation. We are passionate about building automation-first and API-first solutions to serve our diverse internal customer base, tackling complex challenges across nine-figure cloud spend at massive scale. If you're excited about making a tangible impact on how a leading technology company manages and optimizes its cloud infrastructure, this is the team for you. Your Impact Analyze on-demand cloud spend patterns and strategically apply Reservations (RIs), Savings Plans (SPs), and Committed Use Discounts (CUDs) to maximize coverage while minimizing risk of overcommitment or unused capacity. Lead dedicated monthly reviews with Engineering, Product Management, and Finance teams to advance FinOps principles, incorporating FinOps deliverables into roadmaps and helping guide engineers to solve FinOps problems based on risk and business value. Partner closely with Cloud Architecture, Product, and Engineering teams to understand architecture strategy and identify optimization
---
TITLE: Physical Design Engineer, PnR
EMPLOYER: TensTorrent
LOCATION: Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States (unspecified)
SALARY: $100K-$500K
POSTED: 2026-05-04
APPLY_URL: https://job-boards.greenhouse.io/tenstorrent/jobs/5126996007
EXCERPT: Physical Design Engineer, PnR Austin, Texas, United States; Fort Collins, Colorado, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is seeking talented Physical Design Engineers to implement high-performance partitions for an industry-leading AI SOC. You'll own the complete implementation flow from synthesis to tapeout, working alongside world-class engineers to push the boundaries of performance, power, and area. If you're passionate about crafting silicon that powers the future of AI computing and thrive on solving complex design challenges, we want you on our team. This role is hybrid, based out of Austin,TX or Santa Clara, CA or Fort Collins, CO. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who you are - Experienced with synthesis and place-and-route flows, especially using Synopsys Design Compiler / Fusion Compiler and IC Compiler
---
TITLE: Analog Design Engineer Sr Staff
EMPLOYER: d-Matrix
LOCATION: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-03-19
APPLY_URL: https://jobs.ashbyhq.com/d-matrix/8cd5868b-fe7e-429d-bf5a-63b551036878
EXCERPT: Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in
---
TITLE: DevOps Engineer – Any database stack | AWS | Terraform | Ansible | Jenkins (Mandate Skils) (4–7 Years)
EMPLOYER: Cisco
LOCATION: Bangalore, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-05
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Bangalore-India/DevOps-Engineer---Any-database-stack---AWS---Terraform---Ansible---Jenkins--Mandate-Skils---4-7-Years-_2012961
EXCERPT: DevOps Engineer – Any database stack | AWS | Terraform | Ansible | Jenkins (Mandate Skils) (4–7 Years) Bangalore, India Meet the Team We are the Webex Persistence Team within the Webex Service Engineering & SRE organization. Our team designs, builds, and operates highly scalable persistence services powering Webex Teams, Webex Meetings, and the broader Webex Suite. We work across Webex Data Centers and AWS Cloud environments , ensuring high availability, reliability, and performance at a global scale. As part of this team, you will work on mission-critical infrastructure and platform systems , including data, streaming, and persistence layers, with a strong focus on automation, scalability, and cloud-native engineering . Your Impact We are looking for a DevOps Engineer (G8) with strong expertise in Python, AWS, Infrastructure as Code, and CI/CD pipelines to build and operate scalable, automated platforms. This role is focused on hands-on implementation, automation, system reliability, and platform support, with exposure to data platforms, streaming systems, and AI/ML workloads. Key Responsibilities Design, develop, and maintain scalable backend systems using Python flask, sqlalchemy, apscheduler, cache. Design and manage AWS cloud infrastructure (EC2, S3, RDS, VPC, IAM) Implement Infrastructure as Code using Terraform and Ansible Build and maintain CI/CD pipelines using Jenkins and GitHub Automate infrastructure provisioning, deployments, and operational workflows Monitor system performance, reliability, and availability; troubleshoot production issues Support and manage Either Kafka or Postgres, Cassandra ,opensearch database. Build or support backend utilities/services using Python and/or Java Support infrastructure for data platforms and AI/ML workloads (including GenAI/LLM
---
TITLE: Memory Circuit Design Engineer - SRAM / TCAM
EMPLOYER: Cisco
LOCATION: Zhubei, Taiwan (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1
EXCERPT: Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in
---
TITLE: Memory circuit design engineer - 3.
EMPLOYER: Cisco
LOCATION: Zhubei, Taiwan (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413
EXCERPT: Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing
---
TITLE: FinOps Program Manager
EMPLOYER: Plaid
LOCATION: San Francisco HQ, San Francisco, California, United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-08
NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed)
APPLY_URL: https://jobs.ashbyhq.com/plaid/5159cfbb-a402-4ad3-8762-07cd81a5c3c2
EXCERPT: FinOps Program Manager San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. The FinOps function is responsible for financial accountability, visibility, and optimization across all engineering-related spend at Plaid. This includes cloud infrastructure, AI/ML and data workloads, third-party SaaS tools, and other technical investments that support Plaid's products and internal platforms. The team operates at the intersection of Engineering, Product, and Finance, ensuring that spending decisions are transparent, intentional, and aligned with product strategy and business priorities. Rather than functioning as a cost-control or approval layer, FinOps enables teams to understand, own, and optimize their spend while maintaining engineering velocity. Responsibilities - Monitors and analyzes engineering spend across cloud, AI/ML, data platforms, and SaaS, identifying trends, anomalies, and optimization opportunities. - Builds and
---
TITLE: Cellular SoC Static Timing Analysis Engineer
EMPLOYER: Apple
LOCATION: San Diego, United States of America (unspecified)
SALARY: $172K-$302K
POSTED: 2025-10-28
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200628785/cellular-soc-static-timing-analysis-engineer?team=HRDWR
EXCERPT: Cellular SoC Static Timing Analysis Engineer San Diego, United States of America Do you have a passion for invention and self-challenge? Do you thrive on pushing the limits of what's considered feasible. As part of a world class modem team, you'll be at the heart of chip design! Apple recently announced first in-house 5G modem platforms, the C1 and C1X, designed to deliver industry-leading connectivity performance, improved energy efficiency, and seamless integration with Apple's custom silicon. You'll ensure Apple products and services can seamlessly handle the tasks that make them beloved by millions. Join us, and you'll help us innovate new cellular technologies that continually outperform the previous iterations! Do you want to have an impact on every single Apple product? As an ASIC STA engineer, you will be responsible for all aspects of timing including, working with designers for timing constraints generation, helping construct/modify flows, timing analysis and timing closure. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Generation of block and full chip timing constraints. Own timing sign-off to make sure timing requirements are met across all corners, modes, and conditions. Work closely with various multi-functional teams on resolving sophisticated timing issues for major building blocks of complex SoCs. Work on Apple SoC (System-on-Silicon) chips in deep sub-micron technologies targeted for high end mobile applications. As an STA Engineer, the day-to-day work involves performing static timing analysis across multiple
---
TITLE: Engineer III - Data Center FinOps (Hybrid)
EMPLOYER: CrowdStrike
LOCATION: 4 Locations (hybrid)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://crowdstrike.wd5.myworkdayjobs.com/crowdstrikecareers/job/USA---Remote-NY/Engineer-III---Data-Analytics--Hybrid-_R28230
EXCERPT: Engineer III - Data Center FinOps (Hybrid) 4 Locations posted: Posted Today
---
TITLE: Associate Backend Engineer
EMPLOYER: Renesas Electronics
LOCATION: Ho Chi Minh, , Vietnam (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/RenesasElectronics/744000131372011-associate-backend-engineer
EXCERPT: Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of
---
TITLE: Senior PySpark Developer - Vice President
EMPLOYER: Citigroup Inc.
LOCATION: TAMPA, Florida, United States of America (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://citi.eightfold.ai/careers/job/859035188701
EXCERPT: Senior PySpark Developer - Vice President TAMPA, Florida, United States of America
---
TITLE: Sr. Staff Engineer - Timing Methodology
EMPLOYER: Ambiq Micro INC
LOCATION: Austin, Texas, United States (unspecified)
SALARY: Not disclosed
POSTED: 2025-11-05
K401_MATCH: yes (not source-backed)
APPLY_URL: https://job-boards.greenhouse.io/ambiqmicroinc/jobs/4031850009
EXCERPT: Sr. Staff Engineer - Timing Methodology Austin, Texas, United States Company Overview Ambiq is on a mission to enable intelligence everywhere - powering the AI edge revolution with the world's lowest-power semiconductor solutions. Built on our proprietary sub- and near-threshold technology, our chips deliver multi-fold improvements in energy efficiency without costly process scaling. Since 2010, we've shipped over 290 million units to customers building smarter wearables, medical devices, IoT products, and AI-powered edge applications. Our cross-functional teams span design, research, development, production, marketing, sales, and operations across Austin, Hsinchu, Shanghai, Shenzhen, and Singapore. We move fast, tackle hard problems, and create space for people to grow through complex, meaningful work that shapes the future of technology. We're looking for self-motivated, creative problem-solvers who are eager to push technological limits and make a real impact in energy efficiency. At Ambiq, we live by five values: Innovate. Collaborate. Focus. Learn. Achieve. If that's you, join us - the intelligence everywhere revolution starts here. Scope As a Sr. Staff Engineer - Timing Methodology, you will play a critical role in transforming our cutting-edge designs into silicon reality. You will be responsible for all aspects of timing closure from defining methodology, developing flows, closing timing at the block level and timing convergence at SOC level as well. Responsibilities: In-depth expertise on Timing Methodology and Timing closure both at block level and SOC level in modern Finfet and multi-patterning based process technologies using Cadence Tempus or Synopsys Primetime. Own all aspects of timing convergence, including
---
TITLE: DevOps Engineer
EMPLOYER: SKY Harbour Group CORP
LOCATION: Milan, Monte Penice (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
APPLY_URL: https://sky.wd3.myworkdayjobs.com/sky_careers/job/Milan-Monte-Penice/Devops-Engineer_R0043533
EXCERPT: DevOps Engineer Milan, Monte Penice
---
TITLE: Sr DFT Engineer (eInfochips Inc)
EMPLOYER: Arrow Financial CORP
LOCATION: San Jose, California (Cisco) (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
LEARNING_BUDGET_OFFERED: yes (not source-backed)
APPLY_URL: https://arrow.wd1.myworkdayjobs.com/AC/job/San-Jose-California-Cisco/Sr-DFT-Engineer--eInfochips-Inc-_R242729
EXCERPT: Sr DFT Engineer (eInfochips Inc) San Jose, California (Cisco) Position: Sr DFT Engineer (eInfochips Inc) Job Description: What You'll Be Doing: Design and implement DFT, including scan, MBIST, ATPG, Sims, Post-Si diagnosis at block and SoC level Verify test patterns using gate-level simulations. Collaborate closely with Synthesis, STA and physical design to debug and resolve DFT-related problems. Work in partnership with test engineers to bring up test vectors on silicon and ensure successful testing. What We Are Looking For: Strong understanding of industry standards and best practices in DFT - Scan, ATPG, JTAG, and MBIST. Proven experience in developing DFT specifications and architectures for complex designs. Expertise in debugging DFT issues, including ATPG patterns, MBIST implementations, coverage analysis, and more. Proficiency in Siemens-Tessent, Synopsys for DFT implementation, vector generation, and verification. Ability to conduct experiments during silicon debug, effectively gather and analyze data to identify root causes. Efficient scripting skills using TCL for automating tasks and developing custom flows. What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health Savings Account (HSA)/Health Reimbursement Account (HRA) Options Paid Time Off (including sick, holiday, vacation, etc.) Tuition Reimbursement Growth Opportunities And more! Work Arrangement Fully OnSite: Must be able to travel to an Arrow Client office location as requested by Arrow Client
---
TITLE: DevOps Manager
EMPLOYER: Blackbaud INC
LOCATION: Hyderabad - India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
APPLY_URL: https://blackbaud.wd1.myworkdayjobs.com/ExternalCareers/job/Hyderabad---India/Manager--Software-Development_R0012633
EXCERPT: DevOps Manager Hyderabad - India
---
TITLE: Full-Chip Physical Design Engineer
EMPLOYER: Cisco
LOCATION: Armenia (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/Full-Chip-Physical-Design-Engineer_2011199
EXCERPT: Full-Chip Physical Design Engineer Armenia Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full-chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Together, we're building the foundation for the future of connectivity, driving advancements in power, performance, and reliability with every project. Your Impact Drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software to empower people worldwide. Execute top-level RTL to GDSII implementation and signoff to ensure the delivery of high-quality, reliable silicon. Perform critical physical design tasks, including gate-level netlist synthesis, floorplanning, and routing, while applying advanced Clock Tree Architectures like Mesh and H-Tree. Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. Collaborate with multi-functional teams to accelerate design processes and deliver impactful technology that shapes the future of connectivity. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering or Computer Science. Minimum of 3 years of experience in ASIC design and verification. Experience in deep submicron CMOS technologies. Comprehensive knowledge of the full design cycle from RTL to GDSII. Preferred Qualifications Experience in RTL2GDS flow, floorplanning, and power planning. Proficiency in PnR tools such as Synopsys or Cadence. Strong scripting skills for automation and efficiency improvements. Experience with chip-level design
---
TITLE: Contract Specialist II
EMPLOYER: TechnipFMC
LOCATION: Houston, TX (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
APPLY_URL: https://careers.technipfmc.com/job/Houston-Contract-Specialist-II-TX-77001/1348870400/
EXCERPT: Contract Specialist II Houston, TX Job Purpose Advise project managers on contract strategy and ensure that all aspects of the contract during the execution phase are addressed with the objective of contributing to maximize project revenues. Job Description Act as a key integral member of the project team and participate in commercial strategic discussions and decisions to ensure that contracts risks are identified, properly evaluated and mitigated. Provide the project (including team work onshore and offshore) with accurate summaries of contract related matters including contract synopsis, contract review, contract obligations matrix and guidance on contract requirements. Responsible for preparation/review of all relevant contractual correspondence exchanged during project execution to and from the Client, partners, subcontractors and authorities. Monitor all project deliverables as well as identify risks and opportunities. Assumes overall responsibility for all contractual and commercial issues related to management of change, including ensuring claims are issued within the timeframes set out in the Contract receiving all required internal approvals: prepare, interfacing with involved functions, and negotiate any claims against client, joint-venture partners and subcontractors. You are meant for this job if: Bachelor's degree or relevant experience in pertinent discipline preferred. Minimum 5 years experience with contracts. At least 2 years experience with Subsea contracts preferred, oil & gas O&G industry
---
TITLE: STA Engineer
EMPLOYER: Apple
LOCATION: Austin, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2026-04-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200657272/sta-engineer?team=HRDWR
EXCERPT: STA Engineer Austin, United States of America Imagine what you could do here at Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will get the unrivaled and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a hardworking engineer to join our exciting team of problem solvers. Come join our team and be responsible for leading edge IP development and coordinating with multiple SOC teams. In this role, you will work collaboratively with various SOC teams to execute design and integration tasks for the high quality IP deliverables. As an ASIC STA Engineer, you will have responsibilities spanning various aspects of SOC design: Full chip and block level timing closure ownership throughout the entire project. Develop and maintain methodology and flows related
---
TITLE: DEVOPS ENGINEER - CLOUD & CI/CD - VOIS
EMPLOYER: Vodafone Group
LOCATION: Pune, Maharashtra, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://vodafone.eightfold.ai/careers/job/563018696823460
EXCERPT: DEVOPS ENGINEER - CLOUD & CI/CD - VOIS Pune, Maharashtra, India
---
TITLE: Physical Design Lead – Custom Silicon Management
EMPLOYER: Apple
LOCATION: Austin, United States of America (unspecified)
SALARY: $172K-$306K
POSTED: 2026-04-24
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200659712/physical-design-lead-custom-silicon-management?team=HRDWR
EXCERPT: Physical Design Lead – Custom Silicon Management Austin, United States of America Are you a leader and want to apply your engineering background to make big things happen? Can you influence, connect, get results and communicate effectively? Can you deliver on a predictable and dynamic schedule? The Custom Silicon Management Group provides critical custom silicon for all mobile products including iPhone, iPad, iPod, and AppleTV. We have an extraordinary opportunity for senior level engineers to drive and lead technical engagements between Apple and silicon suppliers working on groundbreaking technologies. We are looking for a remarkable Physical Design Lead to work with a highly hardworking Custom Silicon team at Apple to design and develop innovative chips for the coolest products. This position focuses specifically on supporting Physical Design and related activities for the chips. You will have the opportunity to integrate and come-up with new insights, as well as work with vendors to promote efficiency in the Silicon community and ensure high quality of the chips. Audit vendor PD flows and methodologies for any holes and set up issues. Suggest improvements to their methodology to optimize it to obtain the best QoR for Apple chips. Work closely with the internal teams like systems and program management to ensure that the vendor PD implementation team is meeting the design goals. Work closely with specialists from other teams like the packaging, process etc. to resolve any issues in the project which are in an area closely related to PD. Conduct periodic design reviews
---
TITLE: CloudOps Engineer
EMPLOYER: Tyler Technologies
LOCATION: Location not specified (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.jobvite.com/tylertech/job/oTtLzfwq
EXCERPT: CloudOps Engineer CloudOps Engineer
---
TITLE: VP Sales, EMEA
EMPLOYER: Cohere Health
LOCATION: Berlin | Hybrid | Frankfurt | Munich | Remote (hybrid)
SALARY: Not disclosed
POSTED: 2026-06-10
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.ashbyhq.com/cohere/277827a9-02b7-49ca-8590-458e93cab0e6
EXCERPT: VP Sales, EMEA Berlin | Hybrid | Frankfurt | Munich | Remote Who are we? Our mission is to scale intelligence to serve humanity. We're training and deploying frontier models for developers and enterprises who are building AI systems to power magical experiences like content generation, semantic search, RAG, and agents. We believe that our work is instrumental to the widespread adoption of AI. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. We like to work hard and move fast to do what's best for our customers. Cohere is a team of researchers, engineers, designers, and more, who are passionate about their craft. Each person is one of the best in the world at what they do. We believe that a diverse range of perspectives is a requirement for building great products. Join us on our mission and shape the future! Why This Role? As our VP Sales, EMEA you will spearhead year-over-year revenue growth by developing and executing on enterprise level customer acquisition strategies across the region. You will drive long-term success through strategic development, coaching, and expanding Cohere's presence in EMEA. In this pivotal leadership role, you will cultivate and guide our enterprise sales team to exceed revenue targets and organizational goals, while fostering a culture of excellence and innovation. As our VP of Sales, you will: - Develop, execute, and lead a comprehensive go-to-market growth strategy
---
TITLE: Chiplet Physical Design Engineer
EMPLOYER: TensTorrent
LOCATION: United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-02-12
APPLY_URL: https://job-boards.greenhouse.io/tenstorrent/jobs/5045929007
EXCERPT: Chiplet Physical Design Engineer United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. As a Senior Chiplet Physical Design Engineer at Tenstorrent, you will work on a high-profile, cutting-edge program designing and integrating multiple chiplets into a System-in-Package (SiP). You'll collaborate closely with Tenstorrent experts and leaders across the USA, Japan, and other global sites, as well as external partners, to deliver world-class CPU and AI silicon. In this role, you will own critical aspects of synthesis and place-and-route for high-speed CPU core designs, contributing directly to performance, power, and area outcomes on advanced process nodes. This role is remote, based out of The United States. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - An experienced physical design engineer with at least 10 years of relevant experience, who thrives in complex,
---
TITLE: FPGA Verification Engineer (Level 5)
EMPLOYER: Northrop Grumman
LOCATION: United States-Maryland-Linthicum (unspecified)
SALARY: $186K-$279K
POSTED: 2026-05-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (not source-backed)
RELOCATION_ASSISTANCE: no (not source-backed)
CHILDCARE_SUBSIDY: yes (not source-backed)
APPLY_URL: https://ngc.wd1.myworkdayjobs.com/Northrop_Grumman_External_Site/job/United-States-Maryland-Linthicum/FPGA-Verification-Engineer--Level-5-_R10227450
EXCERPT: FPGA Verification Engineer (Level 5) United States-Maryland-Linthicum RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: SCI TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Join Northrop Grumman Eastern Region Engineering Team on our continued mission to push the boundaries of possible across space systems. Enjoy a culture where your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world's biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible. With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today. Northrop Grumman Space
---

[PASTE YOUR RESUME OR SKILLS HERE]