I'm looking for a job. I exported this list from FewerJobs.com - a curated job board.

Please:
1. Rank these jobs by fit for me, given my resume / skills.
2. Highlight the top 5 with a one-sentence rationale each.
3. Flag any concerns, including benefit values without source-backed evidence.
4. Suggest one or two filter changes I could make on FewerJobs to find more good matches.

Filters I applied:
- q: Ingram Micro
- quality_floor: default
- match_401k_strict: true
- parental_strict: true
- non_birth_strict: true
- pto_strict: true
- include_older: false
- verified_benefits_only: true
- apply_url_verified: false
- page: 1
- per_page: 100
- sort: relevance

Jobs (48 total):

---
TITLE: Micro Optics Engineering Manager
EMPLOYER: Corning
LOCATION: Keller, TX (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://corningjobs.corning.com/job/Keller-Micro-Optics-Engineering-Manager-TX-76248/1394655300/
EXCERPT: Micro Optics Engineering Manager Keller, TX Requisition Number: 74897 The company built on breakthroughs. ​ Join us.​ Corning is one of the world's leading innovators in glass, ceramic, and materials science. From the depths of the ocean to the farthest reaches of space, our technologies push the boundaries of what's possible. ​ How do we do this? With our people. They break through limitations and expectations - not once in a career, but every day. They help move our company, and the world, forward. ​ ​At Corning, there are endless possibilities for making an impact. You can help connect the unconnected, drive the future of automobiles, transform at-home entertainment, and ensure the delivery of lifesaving medicines. And so much more.​ ​Come break through with us. Our Optical Communications segment has recently evolved from being a manufacturer of optical fiber and cable, hardware and equipment to being a comprehensive provider of industry-leading optical solutions across the broader communications industry.This segment is classified into two main product groupings - carrier network and enterprise network. The carrier network product group consists primarily of products and solutions for optical-based communications infrastructure for services such as video, data and voice communications. The enterprise network product group consists primarily of optical-based communication networks sold to businesses, governments and individuals for their own use. Purpose of Position: We are seeking a seasoned Manufacturing Engineeri
---
TITLE: Silicon Micro-architecture and RTL Lead, Google Cloud
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-04-28
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXiAZPQspEkwABvZ6BujZJltNS3E2m7WTxg4dUcXd9YtEjsACxwdTOYq9JSIqkGURs04FP8E5uhd97AQRZrIk6iLNW1H1k9NQg2lg39195nHmwKBIQxKVHgGCZBpRA%3D%3D_V2&loc=IN&title=Silicon+Micro-architecture+and+RTL+Lead
EXCERPT: Silicon Micro-architecture and RTL Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to
---
TITLE: Senior Product Manager - Micro-Segmentation Platform and Operational Experience
EMPLOYER: Akamai Technologies
LOCATION: Israel (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-07
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 10 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://fa-extu-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/requisitions/job/2870
EXCERPT: Senior Product Manager - Micro-Segmentation Platform and Operational Experience Israel We're looking for an experienced Product Manager to join us and own the Platform and Operational Experience aspects of the Guardicore product, ensuring it delivers exceptional experiences to our global enterprise customers. You will drive this through product strategy, innovation, and execution across the product development lifecycle, removing adoption frictions and boosting customer value.
---
TITLE: Senior Human Resources Business Partner - FAC
EMPLOYER: Abbott Laboratories
LOCATION: Algeria > Algiers : Micro-Zone d'activité Hydra (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
PARENTAL_LEAVE_WEEKS: 8 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 8 (not source-backed)
APPLY_URL: https://abbott.wd5.myworkdayjobs.com/abbottcareers/job/Algeria--Algiers--Micro-Zone-dactivit-Hydra/Head-of-HR---FAC_31136826
EXCERPT: Senior Human Resources Business Partner - FAC Algeria > Algiers : Micro-Zone d'activité Hydra posted: Posted 30+ Days Ago
---
TITLE: Senior Technical Account Manager, Microsegmentation - Mumbai
EMPLOYER: Akamai Technologies
LOCATION: India (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-21
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 10 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://fa-extu-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/requisitions/job/2868
EXCERPT: Senior Technical Account Manager, Microsegmentation - Mumbai India The Technical Account Manager role involves leveraging technical expertise to optimize Guardicore platform value through micro-segmentation, ZTNA, and DNS Firewall solutions.
---
TITLE: Assoc QC Micro Analyst
EMPLOYER: Regeneron Pharmaceuticals
LOCATION: Limerick (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://regeneron.wd1.myworkdayjobs.com/Careers/job/Limerick/Assoc-QC-Micro-Analyst_R46656
EXCERPT: Assoc QC Micro Analyst Limerick posted: Posted Yesterday
---
TITLE: Product Manager - Micro-Segmentation Platform and Operational Experience
EMPLOYER: Akamai Technologies
LOCATION: Israel (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-07
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 10 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://fa-extu-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/requisitions/job/3022
EXCERPT: Product Manager - Micro-Segmentation Platform and Operational Experience Israel We're looking for a Product Manager to join us and own the Platform and Operational Experience aspects of the Guardicore product, ensuring it delivers exceptional experiences to our global enterprise customers. You will drive this through product strategy, innovation, and execution across the product development lifecycle, removing adoption frictions and boosting customer value.
---
TITLE: Microbiologist II
EMPLOYER: AbbVie Inc.
LOCATION: Singapore, , Singapore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.smartrecruiters.com/AbbVie/3743990013290356-microbiologist-ii
EXCERPT: Microbiologist II Singapore, , Singapore Company Description: About AbbVie AbbVie's mission is to discover and deliver innovative medicines and solutions that solve serious health issues today and address the medical challenges of tomorrow. We strive to have a remarkable impact on people's lives across several key therapeutic areas including immunology, oncology and neuroscience - and products and services in our Allergan Aesthetics portfolio. For more information about AbbVie, please visit us at www.abbvie.com . Follow @abbvie on LinkedIn, Facebook , Instagram , X and YouTube. Job Description: Purpose: The primary role is to ensure smooth QC operational activities support to routine or new product introduction per cGMP/EHS/Regulatory expectations with global/site standards. Enables QC functional operational readiness, infrastructure/instrumentation support and compliance readiness. Major Responsibilities: Team Support Responsible for supporting QC micro-operations by timely conduct of test/release of routine or new product introduction activities. Develops technical competency and jointly creates a great place to work in. Financial Support Supports financial spending are within the latest best estimates. Compliance (Quality and Safety) SME for QC Micro - Operational readiness (Eg: Environment, Utilities and Product test), infrastructure/instrumentation needs and compliance readiness (Eg: Track & Trend) against cGMP/EHS/Regulatory compliance expectations to global/site procedures. Authors/Reviews lab documentation per cGMP or EHS expectations of the global/local site procedural needs. Support in resolution of manufacturing/laboratories investigation or exceptions for timely closure or issue resolution. Support in internal/external audits and enables audit response for a successful outcome in sustaining licenses to operate. Infrastructure & Instrumentation Supports QC function infrastructure/instrumentation
---
TITLE: Python Software Engineer II - Remote/Poland
EMPLOYER: Akamai Technologies
LOCATION: Poland (remote)
SALARY: Not disclosed
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 10 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://fa-extu-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/requisitions/job/3197
EXCERPT: Python Software Engineer II - Remote/Poland Poland You'll work on optimizing the placement of the workload in the compute platform. You'll also improve the existing solution to make it faster and more scalable. We're a closely-knit team with a focus on agile development and innovative solutions. In our projects, we implement new micro services using technologies: Flask, gRPC, SQLAlchemy, Docker, Kubernetes and many others.
---
TITLE: Python Senior Software Engineer - Remote/Poland
EMPLOYER: Akamai Technologies
LOCATION: Poland (remote)
SALARY: Not disclosed
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 10 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://fa-extu-saasfaprod1.fa.ocs.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX/requisitions/job/3210
EXCERPT: Python Senior Software Engineer - Remote/Poland Poland You'll work on optimizing the placement of the workload in the compute platform. You'll also improve the existing solution to make it faster and more scalable. We're a closely-knit team with a focus on agile development and innovative solutions. In our projects, we implement new micro services using technologies: Flask, gRPC, SQLAlchemy, Docker, Kubernetes and many others.
---
TITLE: Senior AI Developer - SAP Labs East Asia Singapore
EMPLOYER: SAP
LOCATION: Senior AI Developer - SAP Labs East Asia Singapore | Country Singapore | Internal Posting Location Singapore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Singapore-Senior-AI-Developer-SAP-Labs-East-Asia-Singapore-117440/1386116633/
EXCERPT: Senior AI Developer - SAP Labs East Asia Singapore Senior AI Developer - SAP Labs East Asia Singapore | Country Singapore | Internal Posting Location Singapore We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. *SAP will be prioritizing candidates with full working rights in Singapore* What you'll do Your tasks include: Own, create, prioritise and maintain the backlog, while shaping the roadmap together with Area Product Owner, engineering, and Product Manager Act as a hands-on technical product owner who can drive product roadmap, priority coordination, product definition, implementation, and delivery lifecycle. Explore, understand, and implement most recent technologies and approaches for cloud platform and data pipelines. Makes decisions about in-house developments, purchases, or partnerships on product level. Comfortably handle multi-tenant and multiple micro-services environments Ensures product delivery: Prioritises and describes the product backlog. Ensures the delivery of high-quality specifications according to customer and user requirements, to create a competitive advantage for SAP. Ensures the delivery of high-quality products under customer requirements, including the completio
---
TITLE: ASIC Digital Design Engineer II, Silicon Engineering
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-08
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcHsrgwWN7Y2d6pNVVICVe2b0jfdsrwKnS2Duw_RfL4yEjsACxwdTM8PdhjKksREzrwUS05bAsHYIsnAM0j18suBmBOP_jXW3Qr7CK8ogRakyjXMqLc743ndvIUFPg%3D%3D_V2&loc=IN&title=ASIC+Digital+Design+Engineer+II
EXCERPT: ASIC Digital Design Engineer II, Silicon Engineering Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will be a part of the team which designs the Tensor Processing Unit (TPU) core and sub-system. The TPU core is the heart of Google's Tensor SoC. You will be working through all phases of design and implementation. You will be working with Architects to come-up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/proto-typing experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical design (PD) team to take the design through PD cycle and eventual tape-out. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Use simulation/emulation/power analysis tools and techniques to
---
TITLE: RTL Design Engineer, Google Cloud, Silicon
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRdZcO5rQorwYsIKOXpPSknn10hl8Ydg2e55Pks_qKHgEjsACxwdTHFCJSO5ha3tKkQZ-1dfKUwcSbh4GVdNJqG3PDmoETP6LnpPwhrRoMIJrLAAOg1J_u6u1kui-A%3D%3D_V2&loc=IN&title=RTL+Design+Engineer
EXCERPT: RTL Design Engineer, Google Cloud, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Own microarchitecture and implementation of Internet Protocol (IP) and subsystems. Work with Architecture, Firmware, and Software teams to drive feature closure
---
TITLE: Java Full Stack Developer - SAP Business Accelerator Hub
EMPLOYER: SAP
LOCATION: Country India | Internal Posting Location Bangalore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Bangalore-Java-Full-Stack-Developer-SAP-Business-Accelerator-Hub-560066/1273001501/
EXCERPT: Java Full Stack Developer - SAP Business Accelerator Hub Country India | Internal Posting Location Bangalore We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll build To support our development initiative for the SAP Business Accelerator Hub within SAP Intergration Suite Business Unit is seeking for experienced Java Full Stack Developers who are passionate about technology and intrigued by its limitless possibilities. You can access the SAP Business Accelerator Hub at https://hub.sap.com. Technologies We Work On Programming Languages: Java, JavaScript, TypeScript, HTML5, Angular Cloud Infrastructure: Virtualisation, Cloud Foundry, AWS, CDN Analytics: Elasticsearch/ELK, Grafana Database: Postgres DevOps: Scripting - Shell or Python, Dynatrace Technologies: REST/ODATA, Micro-service architecture What you bring Expectations from You 4-7 years of relevant experience in software development with a focus on strong hands-on development experienc using programming Languages like Java and JavaScripts, like, TypeScript, HTML5, Angular. University Degree (BE/BTech/MTech) in Computer Science or related engineering subject Analyse, design and
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TITLE: Silicon SoC Integration Design Lead, Google Cloud
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-08
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckX8jvwKb6wpl2fQ-znYkUFJYigKRxSIBz8pIlIVqxdMZEjsACxwdTAYR-rnkO34pTjinfxpcNaW-3r-RpA9RHG9-ppfaTyjFAYD9FAb1JkoFiG5E4kmWYW7y-5fuTQ%3D%3D_V2&loc=IN&title=Silicon+SoC+Integration+Design+Lead
EXCERPT: Silicon SoC Integration Design Lead, Google Cloud Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Lead SoC/SS integration team. Drive development of complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization. Own microarchitecture and implementation of IPs and subsystems. Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance and Area improvements for the domains owned. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. 5 years of experience in micro-architecture and design
---
TITLE: Coherent NoC IP Design Engineer
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXdfi4SoqQLsrRhpoHX58gnSh-5sQfT_cYti5r1jK92UEjsACxwdTKK7KUEIEjkcTRdnUel0APalXt5Ttmh7-DzPZWz5_AYHwQsIVMqy1TtnAvSbguQF_YNCdwk4Gw%3D%3D_V2&loc=IN&title=Coherent+NoC+IP+Design+Engineer
EXCERPT: Coherent NoC IP Design Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will join a team developing Application-Specific Integrated Circuits (ASICs) to accelerate machine learning computation in data centers. You will collaborate with Architecture, Verification, Power and Performance, and Physical Design teams to specify and deliver quality designs for next-generation accelerators. You will solve technical problems through micro-architecture innovation and evaluate design trade-offs between performance and power. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Own and execute the Register-Transfer Level (RTL) design and micro-architecture for high-performance fabrics and Network on Chip (NoC) subsystems from concept to tape-out. Run and analyze Power Performance Area (PPA) for the designs, and do design trade-offs to understand/optimize the design. Perform in-depth search performance analysis of NoC topologies, including latency modeling, bandwidth bottleneck identification, and arbitration tuning. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Drive front-end implementation tasks,
---
TITLE: SAP Concur iXp Intern - Global Customer Marketing
EMPLOYER: SAP
LOCATION: Country USA | Internal Posting Location Bellevue (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Bellevue-SAP-Concur-iXp-Intern-Global-Customer-Marketing-WA-98004/1399922333/
EXCERPT: SAP Concur iXp Intern - Global Customer Marketing Country USA | Internal Posting Location Bellevue We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What You'll Build The SAP Internship Experience Program is SAP's global, strategic, paid internship program that provides university students with opportunities to find purpose in their careers. This is more than an internship; it's the foundation for a career built on connection, creativity, and impact. Position title: SAP Concur iXp Intern - Global Customer Marketing Location: Hybrid - Bellevue Expected start date to end date: July 2026 - December 2026 Working hours: Full time 40 hrs./week We are seeking a highly analytical and curious Global Customer Marketing Intern to join our team. This role offers a unique opportunity to work at the intersection of data, customer insights, and marketing strategy, helping us deliver highly personalized, micro-targeted campaigns to niche customer segments worldwide. In this role, the intern will analyze customer data to identify patterns and insights, breaking down and segmenting datasets to better
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TITLE: Staff Software Engineer, Vertex AI, Workbench
EMPLOYER: Google
LOCATION: Warsaw, Poland (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPQanmmZIwmMzux4WIn_LFcJdxvFnRz7oZsPP8pNYe7EjsACxwdTBnAYP32XD6BJG1S2_YThEZLLiZXIFaDg7RgGzoCP-rHPmlJ6Bi2pWFxevxgZSgLvwKegSjAHg%3D%3D_V2&loc=PL&title=Staff+Software+Engineer
EXCERPT: Staff Software Engineer, Vertex AI, Workbench Warsaw, Poland Google Cloud's mission is to make every business successful through AI by combining cutting-edge technology, infrastructure, and talent. AI/ML software engineers in Cloud bridge the gap between pioneering models and a massive product vehicle reaching billions. Our talent density and AI-powered tools drive rapid development, rooted in a culture of empowerment and a bias to action. In this role, you aren't just building technology; you're shaping the frontier of enterprise and driving the evolution of advanced models. In this role, you will be at the forefront of delivering excellent notebook experience and building the foundational infrastructure for Gen AI agents. You will lead a team, directly enhancing Vertex AI Notebooks, including both Workbench Enterprise, as you collaborate with dynamic, cross-functional teams. While direct AI Agent development experience isn't a prerequisite, passion for learning Google's AI technologies is essential. You should have experience in languages like Java, Golang, Typescript, or Python, and an extensive background in cloud computing, distributed systems, or micro services. Familiarity with Google's production environment or Google Cloud is required to help guide crucial design and trade-off decisions. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do -
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TITLE: Process Development Engineer
EMPLOYER: Corning
LOCATION: Tucheng City (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://corningjobs.corning.com/job/TuCheng-City-Process-Development-Engineer-236/1371264000/
EXCERPT: Process Development Engineer Tucheng City Role Purpose The Process engineer for Fiber Array Units (FAUs) will oversee the design, optimization, and implementation of manufacturing processes for fiber array products. This role involves working at the intersection of technology, engineering, manufacturing, and quality assurance to ensure the highest levels of efficiency, reliability, and product performance. The ideal candidate will have a strong technical background in fiber optics, micro-assembly processes, and materials science, as well as experience leading process development in high-tech or optical manufacturing environments. Key Responsibilities Process Design and Optimization: Develop, validate, and implement scalable manufacturing processes for fiber array units; Optimize processes to improve yield, cycle time, and cost-effectiveness; Design and conduct experiments to evaluate process reliability and performance. Cross-Functional Collaboration: Collaborate with R&D, engineering, and production teams to transition new product designs into full-scale production; Partner with supply chain and procurement teams to select materials, components, and equipment; Work closely with quality assurance to meet product specifications and compliance standards. Technology and Equipment Development: Identify and integrate new technologies and equipment to enhance manufacturing capabilities; Work with suppliers and vendors on the development and customization of specialized tools and fixtures. Process Documentation and Training
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TITLE: Senior Developer - Java/Cloud - SAP Cloud For Customer (Devanahalli Location)
EMPLOYER: SAP
LOCATION: Country India | Internal Posting Location Bangalore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Bangalore-Senior-Developer-JavaCloud-SAP-Cloud-For-Customer-%28Devanahalli-Location%29-KA-562149/1403686633/
EXCERPT: Senior Developer - Java/Cloud - SAP Cloud For Customer (Devanahalli Location) Country India | Internal Posting Location Bangalore We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll build Our team focuses on SAP Sales Cloud - Foundation topics, building core platform capabilities that power key business processes. The primary areas of responsibility include: Identity and Access Management (IAM) Mass Data Handling Event and Batch Processing Scheduling and Orchestration The solution integrates deeply with SAP Sales and Service Cloud core processes As a senior developer in the team the responsibility lies In designing and developing micro front ends for microservices. In resolving complex design problems and working in close collaboration with the team and guiding the team with solutions. Understanding SAP Cloud Product standards and building applications compliant with those standards. In developing microservice applications using open source frameworks. Working in continuous cloud delivery mode taking care of end to end lifecycle of the microservices starting from design, development (hands on with coding), testing (with Automation),
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TITLE: Mechanical Design Engineer
EMPLOYER: Corning
LOCATION: Tucheng City (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://corningjobs.corning.com/job/TuCheng-City-Mechanical-Design-Engineer-236/1371263700/
EXCERPT: Mechanical Design Engineer Tucheng City Role Purpose The Mechanical Design Engineer is responsible for the end‑to‑end design, development, and validation of precision mechanical components and assemblies used in photonic, fiber‑optic, and micro‑positioning applications. This role covers product mechanical design, as well as integration and assembly considerations, ensuring the product meets performance, manufacturability, and reliability objectives. Key Responsibilities Mechanical Product Design Design mechanical components and sub‑systems for photonic or fiber‑optic applications (alignment frames, holders, modules, etc.). Conduct full product development process: concept, design, prototyping, verification, and implementation. Opto ‑ Mechanical Assembly Integration Design precision alignment structures and assembly‑friendly mechanisms. Ensure mechanical designs support micron‑level optical alignment requirements. Prototype Build & Validation Support prototype fabrication and assembly. Validate design through mechanical/thermal/environmental tests. Fixture & Tooling Development Design precision fixtures, jigs, alignment tools, and assembly aids to support product build. Work with automation/assembly teams to ensure proper integration. Cross ‑ Functional Collaboration Work with Global R&D, manufacturing, and quality teams to transition designs into scalable production. Collaborate with suppliers on precision machining, tooling, and component fabrication. Troubleshooting & Improvement Support production with mechanica
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TITLE: Senior Silicon Physical Design Engineer
EMPLOYER: Google
LOCATION: Tel Aviv, Israel; +1 more (unspecified)
SALARY: Not disclosed
POSTED: 2025-12-18
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcEmKw3OqCFQjNCd4HdZzERM6VJ1TALxcKuWEl9dOcK-EjsAvkGZm1vEX_yavFl_ZfZQwpnAYOQ9dnoNy3uz_4XMKzM4htTphNwR5OQcsn_0LABreM6jIaV9Q-VSQQ%3D%3D_V2&loc=IL&title=Senior+Silicon+Physical+Design+Engineer
EXCERPT: Senior Silicon Physical Design Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements. Collaborate with cross-functional teams to debug failures or performance shortfalls and
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TITLE: Optical technician
EMPLOYER: Intuitive Surgical, Inc.
LOCATION: Parvomay, BULGARIA, Bulgaria (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 8 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 8 (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/Intuitive/744000119090272-optical-technician
EXCERPT: Optical technician Parvomay, BULGARIA, Bulgaria Company Description: It started with a simple idea: what if surgery could be less invasive and recovery less painful? Nearly 30 years later, that question still fuels everything we do at Intuitive . As a global leader in robotic-assisted surgery and minimally invasive care , our technologies-like the da Vinci surgical system and Ion -have transformed how care is delivered for millions of patients worldwide. We're a team of engineers, clinicians, and innovators united by one purpose: to make surgery smarter, safer, and more human. Every day, our work helps care teams perform with greater precision and patients recover faster, improving outcomes around the world. The problems we solve demand creativity, rigor, and collaboration. The work is challenging, but deeply meaningful- because every improvement we make has the potential to change a life. If you're ready to contribute to something bigger than yourself and help transform the future of healthcare , you'll find your purpose here. Job Description: Primary Function of Position: Production of small optical elements and assemblies of the highest standard and quality. He works closely with the other team members, the division and department manager to achieve the goals in the areas of quantities, efficiency, accurate time documentation and scrap. In each of these areas, the overall performance of the team is measured against these targets for each quarter. Roles and Responsibilities: Independent processing of small micro-optical parts and assemblies according to company-specific specifications Independent assessment of the work results by measuring
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TITLE: Account Partner Director - Travel, Transportation and Hospitality
EMPLOYER: Salesforce
LOCATION: Illinois - Remote; Texas - Remote; North Carolina - Remote; Washington - Remote; Massachusetts - Remote; Georgia - Remote; Pennsylvania - Remote (remote)
SALARY: $183K-$244K
POSTED: 2026-06-08
PARENTAL_LEAVE_WEEKS: 26 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://careers.salesforce.com/en/jobs/jr344803/account-partner-director-travel-transportation-and-hospitality/
EXCERPT: Account Partner Director - Travel, Transportation and Hospitality Illinois - Remote; Texas - Remote; North Carolina - Remote; Washington - Remote; Massachusetts - Remote; Georgia - Remote; Pennsylvania - Remote We are currently seeking Account Partner Directors to join our growing Professional Services sales team in Travel, Transportation and Hospitality. As a critical member of the Go-To-Market and Professional Services Team, you are responsible for building relationships with our license sales and extended functional teams (such as product, success managers, creative teams, legal, delivery and more) to understand, evaluate and strategically advise our internal teams and the customer on programs to execute on their vision and goals. You will be responsible as the deal originator, strategist and execution quarterback supported by our delivery organization. Responsibilities Drive thoughtful, strategic and enterprise level strategy for our most ambitious customers Facilitate qualification, deal cycle participation, account reviews and value assessments Drive awareness within a micro-vertical to develop repeatable motions Enable smooth transition and partnership into our delivery team with effective margins, staffing plans, approach and Salesforce methodology Serve as a key SME, leader, and professional services consultant to our license sales teams Serve as the liaison between internal teams and the customer From Operating Model: The Account Partner (AP) is accountable for creating and executing a strategy that builds mind-share and broad adoption of Salesforce technologies on his/her assigned accounts. The AP ensures alignment with Sales and is responsible for developing relationships within his/her account(s) to accelerate value and improve customer outcomes, and
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TITLE: Physical Designer Engineer, Google Cloud
EMPLOYER: Google
LOCATION: Tel Aviv, Israel; +1 more (unspecified)
SALARY: Not disclosed
POSTED: 2025-12-15
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTjuPS0bNVqiOcmm9XLK5b_cjaMtqVx38-yqsSFVWvqTEjsAvkGZm4qfFl5OGlQQ3f_F9wFHbZoabYM75WVlDohL6IYuq2K4zE9TdwKkCTJXy6dKUtSwTws8S9rDBA%3D%3D_V2&loc=IL&title=Physical+Designer+Engineer
EXCERPT: Physical Designer Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Drive to the closure of timing and power consumption of
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TITLE: (Senior) IT Risk Specialist (f/m/d)
EMPLOYER: SAP
LOCATION: Region Europe | Country Germany | Internal Posting Location Walldorf (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Walldorf-%28Senior%29-IT-Risk-Specialist-%28fmd%29-69190/1395663433/
EXCERPT: (Senior) IT Risk Specialist (f/m/d) Region Europe | Country Germany | Internal Posting Location Walldorf We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. All SAP locations in Germany as for example Walldorf, Hamburg, Berlin, Ratingen, Eschborn, Gerlingen, Garching are possible. What you'll build SAP SS&D (Sovereign Services & Delivery) is looking for an IT Risk Specialist (f/m/d) to operate and further develop the infrastructure at our Walldorf location. In this role, you will be responsible for the secure operation and risk-compliant management of the local IT environment, including the on-site Micro Data Center. This includes managing and maintaining the hardware infrastructure, performing preventive maintenance and troubleshooting, and applying regular updates and security patches to ensure a compliant and stable system landscape. You will also be responsible for the provisioning, rollout, and support of hardened clients at the site. Your tasks will involve both strategic and hands-on responsibilities: from installing and configuring systems, virtualization, and hardware lifecycle management, to ensuring compliance with relevant IT
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TITLE: Manager, FP&A
EMPLOYER: AbbVie Inc.
LOCATION: Shanghai, Shanghai, China (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.smartrecruiters.com/AbbVie/3743990013342126-manager-fp-a
EXCERPT: Manager, FP&A Shanghai, Shanghai, China Company Description: About AbbVie AbbVie's mission is to discover and deliver innovative medicines and solutions that solve serious health issues today and address the medical challenges of tomorrow. We strive to have a remarkable impact on people's lives across several key therapeutic areas including immunology, oncology and neuroscience - and products and services in our Allergan Aesthetics portfolio. For more information about AbbVie, please visit us at www.abbvie.com . Follow @abbvie on LinkedIn, Facebook , Instagram , X and YouTube. Job Description: KEY DUTIES AND RESPONSIBILITIES: Describe scope: % of Time or Importance Support strategy goal setting and Strategic financial objectives. 15% Drive business planning process and roll out Financial plans. Assure the quality and strategy alignment of China expansion and growth strategy plan, budget and forecasts. Coordinate with Intl./Global to ensure timely and high quality China consoled reporting deliverables. 25% Navigate, provide the financial guidance to Business Unit General Managers, and Marketing Directors to manage Performance and objectives of business plans. Propose intervention, early warning and risk control. 25% Analysis and decision support. Offer analytical support for decisions on new product/new business/ new channel, micro resource allocation, organization expansion/organization optimization, sample, and key contracts negotiation. 20% ROI assessment for strategic initiatives. 15% Qualifications: Bachelor's degree on Finance or Economics related subject. Minimum 8+ years track record in Finance field of Multinational companies, at least 4+ years in FP&A position prior to Allergan Healthcare or FMCG industry preferred. CPA, ACCA or CMA, MBA in equivalent
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TITLE: Senior CPU Performance Architect
EMPLOYER: Google
LOCATION: Mountain View, CA, USA; +3 more (unspecified)
SALARY: $163K-$237K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcDcgs4KibHM8gnqti7eRyV-VMbH_5YbBs3u7pKtMsbGEjsACxwdTMcCzwBhN48GztG1hEO3PTvD5y2M7YFpYpMj1zxD8CQ2pqQ5RXWSi3ioNtAkzsU2FfwOHJ9q5A%3D%3D_V2&loc=US&title=Senior+CPU+Performance+Architect
EXCERPT: Senior CPU Performance Architect Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan and evaluate ARM's architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and microarchitecture studies. Lead collaboration with design and verification teams to develop efficient CPU implementation. Define and write CPU subsystem architecture specifications. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer
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TITLE: Senior Silicon Architect
EMPLOYER: Google
LOCATION: Mountain View, CA, USA (hybrid)
SALARY: $218K-$237K
POSTED: 2026-06-09
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQaKsi24RJRhg3GecATEBh5jcY5FSQoF035Bkj_8FuNGEjsACxwdTDOPHNvHpVKhnNpqTI2KcAoL27KE1eCPEAWirn3e1fdGVp3FKUvzUtg6WuESPa5BOBiyOQUJfg%3D%3D_V2&loc=US&title=Senior+Silicon+Architect
EXCERPT: Senior Silicon Architect Mountain View, CA, USA The US base salary range for this full-time position is $218,000 - $237,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google . Position reports to the Google Mountain View, CA office & may allow for a hybrid schedule as per Google policy. Artificial intelligence will be one of humanity's most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Lead the definition of chip IP architectures, memory hierarchy, interconnect fabrics, and IP integration to meet product requirements. Utilize high-level performance and power models to guide architectural decisions and conduct detailed trade-off analyses to optimize for system-level goals. Create and maintain detailed architectural specification documents that guide micro-architecture and design teams throughout the project lifecycle. Collaborate with software, product management, and physical design teams to ensure the hardware architecture is feasible, aligns with software needs, and meets all product requirements. Drive the
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TITLE: Senior Manager, FP&A
EMPLOYER: AbbVie Inc.
LOCATION: Shanghai, Shanghai, China (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 12 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.smartrecruiters.com/AbbVie/3743990013342336-senior-manager-fp-a
EXCERPT: Senior Manager, FP&A Shanghai, Shanghai, China Company Description: About AbbVie At Allergan Aesthetics, an AbbVie company, we develop, manufacture, and market a portfolio of leading aesthetics brands and products. Our aesthetics portfolio includes facial injectables, body contouring, plastics, skin care, and more. Our goal is to consistently provide our customers with innovation, education, exceptional service, and a commitment to excellence, all with a personal touch. For more information, visit https://global.allerganaesthetics.com/. Follow Allergan Aesthetics on LinkedIn. Job Description: KEY DUTIES AND RESPONSIBILITIES: Describe scope: % of Time or Importance Support strategy goal setting and Strategic financial objectives. 15% Drive business planning process and roll out Financial plans. Assure the quality and strategy alignment of China expansion and growth strategy plan, budget and forecasts. 20% Navigate, provide the financial guidance to Business Heads, and Marketing Director to manage performance and objectives of business plans. Propose intervention, early warning, and risk control. 25% Analysis and decision support. Offer analytical support for decisions on new product/new business/ new channel, commercial policy, micro resource allocation, organization expansion, sample, and key contracts negotiation. 10% Product value chain management. Lead pricing strategy for both existing and new launch products, commercial policy framework, G2N process enhancement. Regularly update pricing structures in line with budget/forecast expectation. Ensure closely monitoring of price change and commercial policy implementation and identify gaps (if any) with mitigation plan. 10% Market intelligence preparation by analyzing market segmentations, strategic expansions, competitive dynamics analysis to help overall company strategy setting and execution tracking. 10% Lead and
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TITLE: Senior Physical Design Floorplan Engineer
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWhxsIxImoWtKNHpnAoW8ButUIHjkfgYIXpcS8NSYzltEjsACxwdTBYbU8NNPnxlskVb0ebwzcGzPVQdpDIXq0QoiGKFII34ZX7Y2Iy1Osr27ntt4rG01HfQamk6eg%3D%3D_V2&loc=IN&title=Senior+Physical+Design+Floorplan+Engineer
EXCERPT: Senior Physical Design Floorplan Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing SoCs used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive to the
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TITLE: Customer Service Analyst - Spanish required (evening shift)
EMPLOYER: Oracle
LOCATION: BUCHAREST, Romania, RO (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
PARENTAL_LEAVE_WEEKS: 14 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 14 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://careers.oracle.com/en/sites/jobsearch/job/331363/
EXCERPT: Customer Service Analyst - Spanish required (evening shift) BUCHAREST, Romania, RO As a member of the Support organization, your focus is to deliver post-sales support and solutions to the Oracle customer base while serving as an advocate for customer needs. This involves resolving post-sales non-technical customer inquiries via phone and electronic means, as well as, technical questions regarding the use of and troubleshooting for our Electronic Support Services. A primary point of contact for customers, you are responsible for facilitating customer relationships with Support and providing advice and assistance to internal Oracle employees on diverse customer situations and escalated issues. - 3-5 Years experience in hospitality industry or technical support - Database knowledge - Internet troubleshooting skills - Knowledge of operating systems - Excellent communicator with strong time management and prioritisation skills - Ability to work under pressure and multi-task - Strong analytical skills - Availability to work in shifts and during weekends - Previous experience of Micros Products would be advantageous - Multilingual proficiency is mandatory to support our diverse global customer base - Strong customer service skills As a member of the Support organization, your focus is to deliver post-sales support and solutions to the Oracle customer base while serving as an advocate for customer needs. This involves resolving post-sales non-technical customer inquiries via phone and electronic means, as well as, technical questions regarding the use of and troubleshooting for our Electronic Support Services. A primary point of contact for customers, you are responsible for facilitating customer relationships
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TITLE: Physical Design Engineer
EMPLOYER: Google
LOCATION: Sunnyvale, CA, USA (unspecified)
SALARY: $138K-$198K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXldy12fDsKHaDlGieRAaThLHHn4ayl_281ctyVFmDLHEjsACxwdTL6IPnRyQWCJFp8WxViQS-bCnKucylCwulIxMEZu87EbIvOMD9XySNgTkXqJ-MBZFGPr1Hdebg%3D%3D_V2&loc=US&title=Physical+Design+Engineer
EXCERPT: Physical Design Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro-architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub-chips. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping
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TITLE: Senior Software Engineer, Google Cloud Storage
EMPLOYER: Google
LOCATION: New York, NY, USA (unspecified)
SALARY: $174K-$253K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckbBNjnjwZfelLSsOxDDHgOpDjocfs6hc0gyTlk23IeRkEjsACxwdTHB6nc9daIqy2gRf2H4eYoa0feDVbEVpGsVjtA40yxerL1_YCTt0w3YPJPeaD9KGHE622oeGpw%3D%3D_V2&loc=US&title=Senior+Software+Engineer
EXCERPT: Senior Software Engineer, Google Cloud Storage New York, NY, USA Google Cloud's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google Cloud's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. You will anticipate our customer needs and be empowered to act like an owner, take action and innovate. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. In this role, you will drive the future of flash storage at Google. You will work on projects, designing and implementing advanced scheduling algorithms for improved user isolation and QoS, micro-optimizing server code for ultra-low latency. You will be responsible for enhancing data integrity through advanced error detection, collaborating with platform teams on design and qualification of new solid-state drive (SSD) hardware, and developing innovative technologies like SmartFTL and write amplification (WAF) reduction techniques. Google Cloud accelerates every organization's ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google's cutting-edge technology, and
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TITLE: Senior AI Developer / Architect - SAP Labs East Asia Singapore
EMPLOYER: SAP
LOCATION: Senior AI Developer / Architect - SAP Labs East Asia Singapore | Country Singapore | Internal Posting Location Singapore (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
PARENTAL_LEAVE_WEEKS: 6 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://jobs.sap.com/job/Singapore-Senior-AI-Developer-Architect-SAP-Labs-East-Asia-Singapore-117440/1386118033/
EXCERPT: Senior AI Developer / Architect - SAP Labs East Asia Singapore Senior AI Developer / Architect - SAP Labs East Asia Singapore | Country Singapore | Internal Posting Location Singapore We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. *SAP will be prioritizing candidates with full working rights in Singapore* What you'll do Your tasks include: Design and build production-grade conversational services - Joule and micro-services in Java and Python. Explore, understand, and implement most recent technologies and approaches for cloud platform and data pipelines. Design and define ADR, ACD for the solution on new features or integrations. Drive engineering across Architecture, Implementation, Testing, and Delivery of the Product. Producing high-quality, maintainable code with an emphasis on modularity, testing, and performance Build strong interpersonal relationships with internal and external stakeholders Mentoring junior engineers, performing code reviews, and contributing to a high-performance team culture. Solving complex integration and performance challenges across systems, often working across time zones in a global team set Right attitude: Team first attitude. Ensure
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TITLE: CPU Architecture and Performance Architect
EMPLOYER: Google
LOCATION: New Taipei, Banqiao District, New Taipei City, Taiwan (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckcc6-vUeEEArS2izVXTcX1RH7Yk4EWRI28rZfXwldVBfEjsACxwdTE-syAH_u01lrbYh1SeP8bVP0cIvBVE2mzL7TEJds9yXASCugow6wfr6UrMeepf7rPGIP4oanA%3D%3D_V2&loc=TW&title=CPU+Architecture+and+Performance+Architect
EXCERPT: CPU Architecture and Performance Architect New Taipei, Banqiao District, New Taipei City, Taiwan Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a CPU architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google's advanced SoC products. You'll have the opportunity to collaborate with talents in system performance and software teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you'll be guiding junior CPU architects and working with engineers in power, thermal, security, and physical design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development, pre-silicon performance correlation, and post-silicon performance analysis and debugging. Plan and evaluate CPU architecture features from both architecture and performance angles. Develop a performance model for
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TITLE: Senior Data Scientist, Search Growth
EMPLOYER: Google
LOCATION: Mountain View, CA, USA; +1 more (unspecified)
SALARY: $174K-$253K
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaqQnYalGPDQdMkWvVkjy3nZvJ9OJVxrYSGCEY6ODGKLEjoACxwdTBPlRpBhnQZgATBVsem_Rb4WQnemH2dBSLbmdGGxtzrSjGgdPFnpZGjuqm6a8VEQSTHMouAt_V2&loc=US&title=Senior+Data+Scientist
EXCERPT: Senior Data Scientist, Search Growth Mountain View, CA, USA; +1 more Search has entered a new era. On the one hand, user's needs have gone beyond info-seeking to problem-solving. On the other hand, Search faces severe competition from 3p apps. Growth is a top line goal for Search in this new era. The central Search growth data science team drives Search growth through data-driven growth strategies. We solve complex growth problems both at macro-level and micro-level, through growth measurement methodology development, growth data product development, and growth related analysis and insights. This is a high profile role with executive level visibility. In this role, you will get to work on all aspects of data science, from data science methodology to tooling, both at macro strategy level and at daily product development level. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $174000 - $253000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Search growth measurement methodology development (e.g., Empirical Bayes to conquer high uncertainty in live experiments, growth surrogates to connect short term live experiment signals with long-term growth). Launch based growth analysis and insights, understand different growth levers and their contributions to growth, and provide actionable insights on areas of investment. Work with 3p data to understand the competitive landscape, reason through its strategic implications, and make data-driven strategic action recommendations. Work with the Search growth engineering team to develop growth data
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TITLE: Senior CPU Design Verification Engineer, Emulation
EMPLOYER: Google
LOCATION: Austin, TX, USA; +3 more (unspecified)
SALARY: $163K-$237K
POSTED: 2026-06-09
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckV-Qg_cjRw75nG8ayY7-bHln_TIUxekLKzww-r2Gn5GVEjsACxwdTOQfWdeWXGJDaS9JMTt5mXniXJngpDM8BaO958zwudw6S4B5NtGBB24FK6Ej_573U700r_k1FQ%3D%3D_V2&loc=US&title=Senior+CPU+Design+Verification+Engineer
EXCERPT: Senior CPU Design Verification Engineer, Emulation Austin, TX, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis. Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches. Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation. Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers. Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in both Design
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TITLE: ASIC Power Management Architect
EMPLOYER: Google
LOCATION: San Diego, CA, USA; +1 more (unspecified)
SALARY: $163K-$237K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckfMIr5UXoBF-CXRwnni75OpRyImKX2xNfBO_x8wXaf_-EjsACxwdTClKr6TfKz7THQNVfGNA5_8c8aqCdrgZyzcTkAyKhfrPifHxmeUZ4BiihQ40mc0HFxvQxJalhg%3D%3D_V2&loc=US&title=ASIC+Power+Management+Architect
EXCERPT: ASIC Power Management Architect San Diego, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Drive architectural analysis for mempath traffic patterns, from collecting silicon traffic patterns for key tensor CUJs, to mapping them to pre-silicon CUJ estimates and closing correlation gaps. Oversee end-to-end correlation from pre-silicon micro benchmark power estimates to CUJ modeling estimates, with a focus on architectural assumptions used for modeling. Propose architectural features/requirements for mempath to improve overall Key Performance Indicators (KPIs). Perform algorithm development, modeling, and analysis of various architecture approaches. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with ASIC power management architecture. Experience
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TITLE: MicroLED Display Reliability Engineer, Augmented Reality, Raxium
EMPLOYER: Google
LOCATION: Fremont, CA, USA (unspecified)
SALARY: $188K-$275K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckfh8cBxLbH7zVPLdDutBKn16S1NPFKnodnkDUxbTuBXcEjsACxwdTOq4fUadcySndYIT5d-SD4FaqN7z4F5Ab-vpAqpVDZ4tH5KFDLbpzPA-Y0YNIQuuvetu3rgtBQ%3D%3D_V2&loc=US&title=MicroLED+Display+Reliability+Engineer
EXCERPT: MicroLED Display Reliability Engineer, Augmented Reality, Raxium Fremont, CA, USA As a MicroLED Display Reliability Engineer, you will own the direction and execution of reliability initiatives across the product lifecycle. You will drive transformational improvements in reliability for microLED based display products, covering multiple form factors - including on-chip (for Gallium Nitride (GaN)-on-Silicon based micro-LED emitter planes) and on-display. You will shape long-term strategy, and influence executive stakeholders both internally and externally. You will require technical expertise in optoelectronics reliability, cross-functional leadership, and the ability to operate in a dynamic environment. You will collaborate extensively with cross-functional partners in development (e.g., LED, Display Panel), Process Engineering, Manufacturing and Operations to embed design for reliability into the display panel lifecycle.Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop and implement reliability programs for various device and display product reliability tests including operational lifetests, device aging, environmental stresses and reliability
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TITLE: CPU Performance Architect, Silicon
EMPLOYER: Google
LOCATION: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdtuOMydu_YI4ABvNoKFaYXjpjqsG9fCmAF7eiArvXK1EjsACxwdTFZ6S_YMUM8rXniIk5sfg1AJGiACWwG8gV5Rsw0tkreaRrGuITB_kRTVsP6eKcVk0KUqU-MRkg%3D%3D_V2&loc=TW&title=CPU+Performance+Architect
EXCERPT: CPU Performance Architect, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more As a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google's advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM's) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience. 4 years of experience in microprocessor
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TITLE: ASIC RTL Engineer III, Silicon
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-19
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYpGadnwFrCxIRH2UMkhWyNCMxCjVAGVA6aWToBIpAPCEjsACxwdTFV479vqU9F4HM0FiVlOaWHkxUSgmkvseb_SWFfSDxd1pOKmRT3AsUAbimx9BACtuqm2yxWOjw%3D%3D_V2&loc=IN&title=ASIC+RTL+Engineer+III
EXCERPT: ASIC RTL Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical
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TITLE: Senior UX Designer, Search Design System
EMPLOYER: Google
LOCATION: Mountain View, CA, USA; +1 more (unspecified)
SALARY: $159K-$231K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcke5OyS6DBkdZhHP9yTdMJ4TCPNW2J18YrvMXaWuv3JNeEjsACxwdTJL_qgD4zMJYfni_yaI9DZuC30-Ix3lCw-ZmtzJq8aC4FJv3tYtZTI3se4WMCGYUs-AY99i4kQ%3D%3D_V2&loc=US&title=Senior+UX+Designer
EXCERPT: Senior UX Designer, Search Design System Mountain View, CA, USA; +1 more At Google, we "Focus on the user and all else will follow." Our Interaction Designers transform complex tasks into intuitive, easy-to-use experiences for billions of people. From creating user flows and wireframes to building mockups and prototypes, you will envision and bring product experiences to life with an inspired, refined, and magical feel. You will join our multi-disciplinary UX team, collaborating with Engineering and Product Management, leveraging user insights to create industry-leading products. As an Interaction Designer, you'll apply user-centered design methods to craft industry-leading user experiences from concept to execution, working with design partners to evolve the Google design language to build beautiful, innovative products. As a Senior UX Designer on the Search Design System team, you will serve as a design architect, balancing systemic structural thinking with a high-craft execution of fluid, native interactions. In this role, you will shape the living, cross-platform foundations that power the future of Search, infusing fluidity, delight, and a native-first mindset into a mature design system. You will seamlessly shift between defining macro-level component architectures and crafting micro-level interactive details. You will use high-fidelity prototyping and dynamic specifications to move the system beyond static layouts into adaptive, intelligent logic for both human teams and AI workflows. Beyond architecting tokens and components, you will act as a critical bridge to engineering and a cultural catalyst-converting native design best practices and up-skilling feature teams across the broader organization. In Google Search, we're
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TITLE: Senior ASIC RTL Engineer, Silicon
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-20
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSBRDDxQYFWWu0g0PTlndGqFDVjeSfl7R2ge6f47a7zAEjsACxwdTHwBgoE_-XkQRExGQxlgt_0MQOgz3OYVVPskQcR2CULp-irjTcYeNNpS9zb3ONMx7hfJoYUDRQ%3D%3D_V2&loc=IN&title=Senior+ASIC+RTL+Engineer
EXCERPT: Senior ASIC RTL Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in
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TITLE: Tech Lead, SoC Design
EMPLOYER: Google
LOCATION: Mountain View, CA, USA (unspecified)
SALARY: $192K-$279K
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWXZ1KKa6rTtyRBww19NH16gf62V8rGsRESGtn8Z-5h3EjsACxwdTNwJb-n_p9hdInYz6Jdc6sec-D03xtMFAnSxpbxT_UBIJUIZJJkBUbNYWCW_OLgNjWPqFGimGw%3D%3D_V2&loc=US&title=Tech+Lead
EXCERPT: Tech Lead, SoC Design Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead a team of RTL Design engineers performing tasks related to IP development and/or SOC Design. Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.). Participate with architecture and system design teams in architecture definition, die area estimation, power optimization, and performance enhancements. Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Define microarchitecture for a subsystem/SoC top-level. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related
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TITLE: ASIC RTL Design Engineer III, Silicon
EMPLOYER: Google
LOCATION: Bengaluru, Karnataka, India (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-29
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckctfJ07tUTpQeO5GkYokwYIhZWi6TNbHV7KE4oGmwV8DEjsACxwdTGqmzN6Yd366t4Wp4IUNC6G4RBm2IHsv2hWPhclDdrAb_VB71S9UwT5PBV3j0_GMaBOXXHjE9A%3D%3D_V2&loc=IN&title=ASIC+RTL+Design+Engineer+III
EXCERPT: ASIC RTL Design Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/ Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer
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TITLE: Senior Software Engineer
EMPLOYER: Oracle
LOCATION: Austin, TX, United States, US (unspecified)
SALARY: $79K-$210K
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 14 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 14 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://careers.oracle.com/en/sites/jobsearch/job/336139/
EXCERPT: Senior Software Engineer Austin, TX, United States, US Join Oracle Cloud Infrastructure's Compute team to design, build, and scale the next generation of bare-metal provisioning systems powering millions of servers worldwide. As a senior engineer, you will develop highly reliable and secure infrastructure, tackle complex distributed systems challenges, and help deliver the foundation for OCI's most performant compute services. Oracle Cloud Infrastructure (OCI) is building the next generation of cloud services to support the world's most demanding workloads. The Compute team is responsible for delivering bare-metal provisioning infrastructure that powers millions of servers and forms the foundation of OCI's rapidly expanding AI infrastructure. The Compute Bare Metal Provisioning team owns the critical infrastructure responsible for automating the full server lifecycle from new platform shape (AMD/Intel/Arm/Nvidia) creation, hardware bring-up to customer-ready instance provisioning and firmware management. The services operate at the intersection of bare metal hardware and full-stack orchestration frameworks, a unique combination where both distributed systems engineers and engineers with background in Linux and firmware are highly valued. The team interfaces directly with components like BMCs, NICs, SmartNICs, ILOMs, GPUs, and custom firmware stacks. The team builds high performance, scalable micro-services and tooling that provision, configure, secure, and validate server platforms across OCI's massive fleet of Compute and GPU Infrastructure. You will partner closely across other teams in Compute, Networking, Security, Data center Engineering, and Hardware Development to ensure OCI can launch, scale, and maintain new server platforms with minimal operational overhead and high reliability. You will work directly with
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TITLE: Technical Support Analyst – Oracle Hospitality OPERA Applications Support
EMPLOYER: Oracle
LOCATION: BUCHAREST, Romania, RO (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-03
PARENTAL_LEAVE_WEEKS: 14 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 14 (not source-backed)
K401_MATCH: yes (source-backed)
K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
APPLY_URL: https://careers.oracle.com/en/sites/jobsearch/job/331410/
EXCERPT: Technical Support Analyst – Oracle Hospitality OPERA Applications Support BUCHAREST, Romania, RO The Technical Support Analyst is responsible for 1st level support for Oracle Hospitality OPERA product suite (OPERA PMS, OXI, OWS, S&C, Reporting & Analytics) and associated hotel interfaces. Oracle Hospitality is looking for talented professionals, this is your opportunity to: Shape the future of a world-class support center from the very beginning, delivering 24x7 expertise across the Oracle Hospitality product suite. Work with global teams supporting leading hotels and F&B businesses across EMEA. Develop deep expertise in Oracle Hospitality solutions, including OPERA and MICROS, with continuous training and certification opportunities. Grow your career within Oracle - one of the world's most respected technology companies. At Oracle, we don't just support our customers - we build lasting partnerships. Duties & Responsibilities Provide voice and remote support for hotel customers worldwide. Troubleshoot OPERA PMS issues (reservations, check-in/out, billing). Document solutions and ensure accurate case records in ICCP tool. Collaborate with Oracle teams to escalate and resolve issues. Act as customer advocate for hotel users and escalate gaps. Provide technical assistance via phone, email, and remote tools. Assist in OPERA configuration, installation, and training when required. Stay updated on OPERA new releases. Knowledge, Skills & Abilities - Essential Minimum 2 years' IT or hospitality systems support experience. Experience with hotel PMS applications, ideally Oracle OPERA. Graduate degree in technical, hospitality, or business field. Understanding of hotel operations (front office, reservations, housekeeping). Customer service experience with direct client interaction. Familiarity with Microsoft
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