I'm looking for a job. I exported this list from FewerJobs.com - a curated job board.

Please:
1. Rank these jobs by fit for me, given my resume / skills.
2. Highlight the top 5 with a one-sentence rationale each.
3. Flag any concerns, including benefit values without source-backed evidence.
4. Suggest one or two filter changes I could make on FewerJobs to find more good matches.

Filters I applied:
- q: Cadence Design Systems, Inc.
- quality_floor: default
- match_401k_strict: true
- parental_strict: true
- non_birth_strict: true
- pto_strict: true
- include_older: false
- apply_url_verified: false
- page: 4
- per_page: 100
- sort: relevance

Jobs (100 total):

---
TITLE: Customer Engagement Director - PDK Enablement
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI 07 (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI-07/Customer-Engagement-Director---PDK-Enablement_R54594
EXCERPT: Customer Engagement Director - PDK Enablement SHANGHAI 07 posted: Posted 2 Days Ago
---
TITLE: SoC Design/Integration & Synthesis Engineer
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2025-10-08
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200624398/soc-design-integration-synthesis-engineer?team=HRDWR
EXCERPT: SoC Design/Integration & Synthesis Engineer Cupertino, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will be part of a group that defines flows and methodologies in all these fields that help Apple implement complex chips with the best QOR (quality of results) and PPA (power, performance, and area) using cutting-edge technologies. We are searching for a talented engineer to join our exciting team of problem solvers. As an SOC/ASIC Integration & Synthesis Engineer, you will have responsibilities spanning various aspects of SOC design: - Drive all front-end integration activities like Integration, Synthesis, UPF, Logical Equivalence, ECO, etc. - Work closely on methodology improvements for improving synthesis QOR. - Work on Low power design, writing UPFs, close on power intent verification at the chip level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams. Minimum Qualifications: BS degree
---
TITLE: Order Admin Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Order-Admin--Manager_R54484
EXCERPT: Order Admin Manager SAN JOSE posted: Posted 30+ Days Ago
---
TITLE: Software Engineer II - Compiler/LLVM
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-28
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CORK-01/Software-Engineer-II---Compiler-LLVM_R54826
EXCERPT: Software Engineer II - Compiler/LLVM 2 Locations posted: Posted 15 Days Ago
---
TITLE: Sr Principal AE in PCB
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: MILAN (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-24
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/MILAN/Sr-Principal-AE-in-PCB_R54224
EXCERPT: Sr Principal AE in PCB MILAN posted: Posted 19 Days Ago
---
TITLE: Software Engineer II: PCle VIP R&D
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Software-Engineer-II--PCle-VIP-R-D_R54275
EXCERPT: Software Engineer II: PCle VIP R&D BELO HORIZONTE posted: Posted 30+ Days Ago
---
TITLE: Software Engineer ΙΙ – Ansa Core
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: KATO SCHOLARI 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/KATO-SCHOLARI-01/Software-Engineer----Ansa-Core_R53997
EXCERPT: Software Engineer ΙΙ – Ansa Core KATO SCHOLARI 01 posted: Posted 30+ Days Ago
---
TITLE: Configuration Management Engineer II – Modeler (ST2)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BANGALORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-21
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Configuration-Management-Engineer-II---Modeler--ST2-_R53397-1
EXCERPT: Configuration Management Engineer II – Modeler (ST2) BANGALORE posted: Posted 22 Days Ago
---
TITLE: Product Validation Engineer II – Verisium Debug QA
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Product-Validation-Engineer-II---Verisium-Debug-QA_R52356
EXCERPT: Product Validation Engineer II – Verisium Debug QA BELO HORIZONTE posted: Posted 30+ Days Ago
---
TITLE: Product Validation Engineer II: Quality Assurance (QA) ChipStack AI
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Product-Validation-Engineer-II--Quality-Assurance--QA--ChipStack-AI_R53561
EXCERPT: Product Validation Engineer II: Quality Assurance (QA) ChipStack AI BELO HORIZONTE posted: Posted 30+ Days Ago
---
TITLE: Senior Principal Software Engineer - Compiler Development
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: Burlington, MA (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Burlington-MA/Senior-Principal-Software-Engineer---Compiler-Development_R54563
EXCERPT: Senior Principal Software Engineer - Compiler Development Burlington, MA posted: Posted 30+ Days Ago
---
TITLE: Intern: Application Engineering - Digital Verification Xcelium
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Intern--Application-Engineering---Digital-Verification-Xcelium_R54883-1
EXCERPT: Intern: Application Engineering - Digital Verification Xcelium BELO HORIZONTE posted: Posted 3 Days Ago
---
TITLE: Outbound Marketing Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Outbound-Marketing-Manager_R54196
EXCERPT: Outbound Marketing Manager SAN JOSE posted: Posted 30+ Days Ago
---
TITLE: Sr Account Technical Executive - Mechanical CAE
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Sr-Account-Technical-Executive---Mechanical-CAE_R52653
EXCERPT: Sr Account Technical Executive - Mechanical CAE 2 Locations posted: Posted 30+ Days Ago
---
TITLE: PRINCIPLE SOFTWARE ENGINEER
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: ZHUBEI 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/ZHUBEI-01/PRINCIPLE-SOFTWARE-ENGINEER_R54304
EXCERPT: PRINCIPLE SOFTWARE ENGINEER ZHUBEI 01 posted: Posted 30+ Days Ago
---
TITLE: Sr Education Application Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BANGALORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Sr--Education-Application-Engineer_R54372
EXCERPT: Sr Education Application Engineer BANGALORE posted: Posted 30+ Days Ago
---
TITLE: Mechanical / Design Engineer | Sensors and Systems
EMPLOYER: BETA Technologies INC
LOCATION: South Burlington, Vermont, United States (unspecified)
SALARY: $85K-$110K
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
APPLY_URL: https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4210993009
EXCERPT: Mechanical / Design Engineer | Sensors and Systems South Burlington, Vermont, United States At BETA Technologies, we apply our intellectual curiosity, passion for aviation, and commitment to sustainability toward a shared mission of revolutionizing electric aviation. Regardless of the position one holds, each team member brings their talent and desire to positively impact the environment and lives of others in a refreshing, vibrant, and inclusive culture. We are seeking a highly motivated and detail-oriented mechanical / design engineer. This engineer will work as part of the team developing, designing, and testing BETA's electric aircraft and supporting the Flight Control Systems team. Working on the Flight Control Systems team, you will be responsible for the development and design of the Flight Control System from component design to installation drawings, as well as supporting both certification and verification of flight control system components. You will play a key role in the support of Flight Control systems, testing, and integration. How you will contribute to revolutionizing electric aviation: Support production drawings and technical documentation release Perform GD&T (Geometric Dimensioning and Tolerancing) analysis Collaborate with cross-functional teams to resolve design challenges Participate in design reviews and system integration efforts Develop and execute design tests and test setups Create comprehensive test reports and technical documentation, and design documents Utilize CATIA CAD for detailed mechanical design and drafting Assist in the development of aircraft and test environment documentation Prepare briefing materials for technical meetings and program reviews Minimum Qualifications: B.S. (M.S. desired) in Mechanical Engineering or
---
TITLE: Quantum Product Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Quantum-Product-Engineer_R53469
EXCERPT: Quantum Product Engineer SAN JOSE posted: Posted 30+ Days Ago
---
TITLE: Sr HR Manager & HR Business Partner, Japan
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: YOKOHAMA (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/YOKOHAMA/Sr-HR-Manager---HR-Business-Partner--Japan_R54182
EXCERPT: Sr HR Manager & HR Business Partner, Japan YOKOHAMA posted: Posted 30+ Days Ago
---
TITLE: Software Engineer for SPICE (AI)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BEIJING (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Software-Engineer-for-SPICE--AI-_R53113-1
EXCERPT: Software Engineer for SPICE (AI) BEIJING posted: Posted 30+ Days Ago
---
TITLE: Sr Principal Verification Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-27
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Sr-Principal-Verification-Engineer_R54748
EXCERPT: Sr Principal Verification Engineer SHANGHAI posted: Posted 16 Days Ago
---
TITLE: Senior Technical Program Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Senior-Technical-Program-Manager_R53168
EXCERPT: Senior Technical Program Manager SHANGHAI posted: Posted 30+ Days Ago
---
TITLE: Intern - Digital Marketing
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BRUSSELS 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BRUSSELS-01/Intern---Digital-Marketing_R54231
EXCERPT: Intern - Digital Marketing BRUSSELS 01 posted: Posted 30+ Days Ago
---
TITLE: Senior Principal Software Engineer - Accelerated Verification IP
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Senior-Principal-Software-Engineer_R53133
EXCERPT: Senior Principal Software Engineer - Accelerated Verification IP SAN JOSE posted: Posted 30+ Days Ago
---
TITLE: Lead Software Engineer: ChipStack AI DevOps
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Lead-Software-Engineer--ChipStack-AI-DevOps_R53562
EXCERPT: Lead Software Engineer: ChipStack AI DevOps BELO HORIZONTE posted: Posted 30+ Days Ago
---
TITLE: Foundry Virtuoso Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI 08 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI-08/Foundry-Virtuoso-Engineer_R54576-1
EXCERPT: Foundry Virtuoso Engineer SHANGHAI 08 posted: Posted 30+ Days Ago
---
TITLE: ECAD Librarian for Cadence Allegro
EMPLOYER: Hewlett Packard Enterprise
LOCATION: Bengaluru, Karnātaka, India (hybrid)
SALARY: Not disclosed
POSTED: 2026-05-14
K401_MATCH: yes (not source-backed)
APPLY_URL: https://hpe.wd5.myworkdayjobs.com/Jobsathpe/job/Bengaluru-Karntaka-India/ECAD-Librarian-for-Cadence-Allegro_1206347-2/apply
EXCERPT: ECAD Librarian for Cadence Allegro Bengaluru, Karnātaka, India Join us as an ECAD Librarian and play a key role in developing and maintaining Allegro PCB footprints for cutting-edge hardware designs. Collaborate globally, work with advanced CAD tools, and contribute to innovative projects in a dynamic, hybrid work environment. Grow your career with a leader in enterprise technology.
---
TITLE: Product Marketing Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-04
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CESSON-SEVIGNE-01/Product-Marketing-Manager---Security-Protocol-Engines---Technologies_R54066
EXCERPT: Product Marketing Manager 2 Locations posted: Posted 8 Days Ago
---
TITLE: Lead FrontEnd Methodology Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BANGALORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-DDR-Verification-Engineer_R39669
EXCERPT: Lead FrontEnd Methodology Engineer BANGALORE posted: Posted 30+ Days Ago
---
TITLE: Data Warehouse Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Data-Warehouse-Engineer_R51065
EXCERPT: Data Warehouse Engineer SAN JOSE posted: Posted 30+ Days Ago
---
TITLE: Senior Systems Engineer, Hardware Architecture
EMPLOYER: Waymo
LOCATION: Mountain View, CA, USA (unspecified)
SALARY: $230K-$284K
POSTED: 2026-05-14
APPLY_URL: https://careers.withwaymo.com/jobs?gh_jid=7927507
EXCERPT: Senior Systems Engineer, Hardware Architecture Mountain View, CA, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is a diverse, innovative, and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and you will report to a Systems Architect You will: - Lead and conduct complex, multi-attribute trade studies to define the architecture of the next-generation Waymo Driver, balancing performance, reliability, cost, and other key factors - Develop and analyze architectural options for the overall Self-Driving System, with a strong emphasis on safety via robust fallback systems and high reliability - Collaborate with and drive alignment across diverse
---
TITLE: Mechanical Design Engineer (Tooling Design Focus)
EMPLOYER: Arista Networks
LOCATION: Santa Clara, CA, United States (unspecified)
SALARY: $110K-$175K
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/AristaNetworks/744000131197985-mechanical-design-engineer-tooling-design-focus-
EXCERPT: Mechanical Design Engineer (Tooling Design Focus) Santa Clara, CA, United States Company Description: Arista Networks is a global leader in data driven, client to cloud networking for large data center, campus, and routing environments. Our edge comes from relentless innovation-leveraging advancements in cloud computing, AI, and software defined networking to help customers stay ahead in an increasingly connected world. We believe diverse perspectives fuel creativity. Our inclusive culture empowers individuals from all backgrounds to contribute meaningfully, and our commitment to excellence has earned us recognition including Best Engineering Team, Best Company for Diversity, Best Compensation, and Best WorkLife Balance. We take pride in delivering industry leading quality and performance across everything we do. Job Description: We are seeking a Mechanical Design Engineer with a strong focus on tooling design and a passion for developing manufacturing focused solutions that enable high volume production. In this role, you will collaborate closely with Engineering, Platform Design, Contract Manufacturing (CM) partners, and cross functional teams to design and develop tooling, test fixtures, and jigs that support scalable, high throughout manufacturing environments. Who You'll Work With You'll join a highly collaborative team spanning Hardware Engineering, Platform Design, Reliability Engineering, and global CM partners. This role is deeply integrated with early stage product development, ensuring manufacturability and production success at scale. Precision, innovation, and proactive design collaboration are core to how we operate. What You'll Do You will lead the end to end design, development, and validation of custom tooling and fixtures that support New Product
---
TITLE: Facilities Manager II
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-05
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Facilities-Manager-II_R54977
EXCERPT: Facilities Manager II SAN JOSE posted: Posted 7 Days Ago
---
TITLE: Product Validation Engineer II
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BEIJING (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Product-Validation-Engineer-II_R24363-1
EXCERPT: Product Validation Engineer II BEIJING posted: Posted 30+ Days Ago
---
TITLE: Hardware System Design Engineer - Apple Vision Pro
EMPLOYER: Apple
LOCATION: San Jose, United States of America (unspecified)
SALARY: $147K-$272K
POSTED: 2026-03-27
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200653706/hardware-system-design-engineer-apple-vision-pro?team=HRDWR
EXCERPT: Hardware System Design Engineer - Apple Vision Pro San Jose, United States of America Apple is where individual imaginations gather together, committing to the values that lead to great work. Every new product we build, service we create, or Apple Store experience we deliver is the result of us making each other's ideas stronger. That happens because every one of us shares a belief that we can make something wonderful and share it with the world, changing lives for the better. It's the diversity of our people and their thinking that inspires the innovation that runs through everything we do. When we bring everybody in, we can do the best work of our lives. Here, you'll do more than join something - you'll add something. Apple Vision Pro is a revolutionary spatial computer that seamlessly blends digital content with your physical space. It will allow us to do the things we love in ways never before possible - all while staying connected to the people around us. Upon joining our team as a Hardware System Integrator, you will be directly applying your engineering expertise and working with many cross-functional teams to realize products that consumers will love! We collaborate with a large number of groups to bring a product from concept to mass production. Our goal is to help define exciting product features that will touch our customers. Therefore you'll have the ability to solve challenging engineering problems by selecting components, designing schematics, directing layout, and bringing up/ debugging circuits
---
TITLE: Product Engineer II -EMX
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Product-Engineer-II--EMX_R54551
EXCERPT: Product Engineer II -EMX SHANGHAI posted: Posted 30+ Days Ago
---
TITLE: Staff Hardware System Validation Engineer
EMPLOYER: Aurora Innovation, Inc.
LOCATION: Mountain View, California (unspecified)
SALARY: $154K-$224K
POSTED: 2026-03-22
APPLY_URL: https://aurora.tech/jobs/8467087002?gh_jid=8467087002
EXCERPT: Staff Hardware System Validation Engineer Mountain View, California Who we are Aurora's mission is to deliver the benefits of self-driving technology safely, quickly, and broadly. The Aurora Driver will create a new era in mobility and logistics, one that will bring a safer, more efficient, and more accessible future to everyone. At Aurora, you will tackle massively complex problems alongside other passionate, intelligent individuals, growing as an expert while expanding your knowledge. For the latest news from Aurora, visit aurora.tech or follow us on LinkedIn . Aurora hires talented people with diverse backgrounds who are ready to help build a transportation ecosystem that will make our roads safer, get crucial goods where they need to go, and make mobility more efficient and accessible for all. We're searching for a Staff Hardware System Validation Engineer . The team is responsible for the end-to-end validation of Autonomous Hardware that includes PCBA, modules and Integrated systems from early-stage design and bring-up to sustaining engineering and resolving field issues. In this role, you will - Define, develop and execute Test methodologies for verification and validation of autonomous hardware systems and components. - Collaborate with and influence key cross-functional partners, including Hardware Systems, Safety, Test organizations, Firmware and Electrical Engineering. - Perform requirements analysis, architecture studies and system characterization to derive clear performance metrics. - Drive cross-functional reviews and achieve consensus on key design validation decisions. - Drive sustaining engineering efforts, including root cause and corrective action (RCCA) for issues found in the field. -
---
TITLE: Product validation engineer Intern
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Product-validation-engineer-Intern_R45768
EXCERPT: Product validation engineer Intern SHANGHAI posted: Posted 30+ Days Ago
---
TITLE: Principal Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: PUNE 05 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/PUNE-05/Principal-Software-Engineer_R54111-1
EXCERPT: Principal Software Engineer PUNE 05 posted: Posted 30+ Days Ago
---
TITLE: Hardware Designer (Future Opportunities)
EMPLOYER: Syntronic
LOCATION: Kanata, ON (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
APPLY_URL: https://jobs.lever.co/syntronic/96fac845-c4c0-41eb-bd6f-1e43dc684f05
EXCERPT: Hardware Designer (Future Opportunities) Kanata, ON Join Syntronic: Where Your Innovation Shapes the Future At Syntronic, we don't just follow industry trends-we set them! Join us in partnering with visionary companies and the brightest minds to turn ground-breaking ideas into reality. Imagine working on cutting-edge telecom advancements, pioneering automotive tech, life-saving healthcare innovations, and next-gen industrial automation. Our projects are diverse, impactful, and at the forefront of technological innovation. Be a part of something extraordinary! Who are we?: Syntronic is a global leader in design and development, specializing in electronics, electro-mechanics, and software. We're not just a company; we're a community of innovators. Our teams work on projects that define the future-from creating state-of-the-art communication systems and autonomous vehicles to advancing IoT solutions that revolutionize everyday life. At Syntronic, your work will make a real difference. What we're looking for: We are seeking individuals who want to: · Collaborate with top-tier clients on transformative, cutting-edge projects. · Engage with and learn from industry leaders · Innovate from concept to completion, ensuring high standards. · Gain international experience on global projects. · Thrive in an entrepreneurial environment that supports new ideas. · Explore multiple sectors like telecommunications, automotive, healthcare, and industrial automation. What you'll do What you'll need to get the job done What will make us REALLY love you
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TITLE: Hardware System Design Engineer, Retail and Event Product Design
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2026-04-13
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200657550/hardware-system-design-engineer-retail-and-event-product-design?team=HRDWR
EXCERPT: Hardware System Design Engineer, Retail and Event Product Design Cupertino, United States of America Will you help us design the next generation of Apple products that integrate innovative technologies and provides excellent customer experience and seamless user interaction? Our team has developed and shipped a long list of products and merchandisers within retail space across the world. This includes specially designed MagSafe chargers and USB-C cables, security products, charging infrastructures and more. Apple is seeking a Hardware System Design Engineer for Retail and Event Product Design. We are searching for a driven and hardworking electrical engineer to work on electrical system design and develop hardware solutions for Apple product merchandisers. The successful candidate will join a detail-oriented team who works towards perfection and specialized in providing the best possible customer experience with newly announced products. You will become part of a hands-on development team that nurtures engineering excellence and creativity. On the team you will engage with a rewarding variety of responsibilities. Leading the product architecture and driving HW system design Leading system schematic design, PCB layout and component selection and being the technical champion for all design reviews. Collaborating with wide range of cross-functional teams involved in the product definition, industrial design, validation and manufacturing at Apple. Working with cross functional partners and external vendors to develop product FW. Working with leadership to define product schedules and allocate EE and FW resources Review, challenge, and creatively influence product concepts & roadmaps across groups. Regularly report project status to the
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TITLE: Security Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: KATO SCHOLARI 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/KATO-SCHOLARI-01/Security-Engineer_R54029
EXCERPT: Security Engineer KATO SCHOLARI 01 posted: Posted 30+ Days Ago
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TITLE: Sales Account Executive
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: HOME SINGAPORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-21
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HOME-SINGAPORE/Sales-Account-Executive_R54529
EXCERPT: Sales Account Executive HOME SINGAPORE posted: Posted 22 Days Ago
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TITLE: C++ Software Engineer for Mesh
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/C---Software-Engineer-for-Mesh_R54251
EXCERPT: C++ Software Engineer for Mesh SHANGHAI posted: Posted 30+ Days Ago
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TITLE: Software Engineer for SPICE (math)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BEIJING (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Software-Engineer-for-SPICE--math-_R53112
EXCERPT: Software Engineer for SPICE (math) BEIJING posted: Posted 30+ Days Ago
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TITLE: Sr Principal Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: HSINCHU (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HSINCHU/Sr-Principal-Software-Engineer_R54308
EXCERPT: Sr Principal Software Engineer HSINCHU posted: Posted 30+ Days Ago
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TITLE: Sr Revenue Accounting Analyst
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: DUBLIN (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-27
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/DUBLIN/Sr-Revenue-Accounting-Analyst_R54915
EXCERPT: Sr Revenue Accounting Analyst DUBLIN posted: Posted 16 Days Ago
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TITLE: Inventory and Logistics Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Inventory-and-Logistics-Manager_R54483
EXCERPT: Inventory and Logistics Manager SAN JOSE posted: Posted 30+ Days Ago
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TITLE: Senior Design Engineer
EMPLOYER: Meadow
LOCATION: New York, NY | Remote | United States (Remote) | San Mateo, CA (remote)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.ashbyhq.com/meadow/efdf30af-7e0d-447a-9ff8-4037617638a9
EXCERPT: Senior Design Engineer New York, NY | Remote | United States (Remote) | San Mateo, CA ABOUT MEADOW Meadow is the modern payments platform for higher education that simplifies the entire student financial experience. We're transforming the $600 Billion higher education payments industry in the United States - building for universities what Shopify built for retail businesses, and bringing the entire student financial experience online. The need for a platform like Meadow has never been greater. If you're passionate about our mission to empower students financially and strengthen economic mobility through higher education - and you're excited to join a highly ambitious, talented team - we'd love to hear from you. ABOUT THE ROLE OVERVIEW As a Design Engineer at Meadow, you'll sit at the intersection of Product Design and Front-End Engineering to conceptualize and ship product that powers the student financial experience. Design at Meadow is AI-first and builder-led. We're looking for a Design Engineer who is excited to 1) use AI as a core part of how they design - prototyping early, testing with real customers, and staying involved through launch and iteration, and to 2) design for AI - building products that assume the system can understand context, take initiative, and collaborate with the user. WHAT YOU'LL DO - Own Product Work End-to-End: You'll work in lockstep with Product and Engineering to define problems, explore solution spaces, validate concepts, and ship products. - Prototype Using AI Tools: You'll use Cursor, Claude, and/or other AI tools to build
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TITLE: Lead Technical Marketing Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: ZHUBEI 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/ZHUBEI-01/Lead-Technical-Marketing-Engineer_R54080
EXCERPT: Lead Technical Marketing Engineer ZHUBEI 01 posted: Posted 30+ Days Ago
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TITLE: SoC Design and Integration Engineer
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2026-06-02
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200666065/soc-design-and-integration-engineer?team=HRDWR
EXCERPT: SoC Design and Integration Engineer Cupertino, United States of America Do you love crafting sophisticated solutions to highly complex challenges? As part of our Silicon Technologies group, we would like you to help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and authoritatively handle the tasks that make t hem beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, we will enable our customers to do all the things they love with their devices. As a member of SoC design team, you will be at the center of a SoC design and integration with a critical impact on getting functional products to millions of customers. As a SOC Design and Integration Engineer, your responsibilities span various aspects of SOC design: Write microarchitecture and/or design specifications Design, implement, and debug complex logic designs Integrate complex IPs into the SOC Support all front-end integration activities like Lint, CDC, Synthesis, and ECO Work with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, Formal verification, STA, and Physical Design teams. Collaborate with software and systems teams to ensure a high-quality end product. Minimum Qualifications: Bachelor's Degree + 10 years of experience Preferred Qualifications: Hands on experience in all aspects of the chip development process with proficiency in front end tools and methodologies. Experience writing specifications and converting them to design. Experience with multiple clock domains and asynchronous
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TITLE: Tech Lead, SoC Design
EMPLOYER: Google
LOCATION: Mountain View, CA, USA (unspecified)
SALARY: $192K-$279K
POSTED: 2026-06-11
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWXZ1KKa6rTtyRBww19NH16gf62V8rGsRESGtn8Z-5h3EjsACxwdTNwJb-n_p9hdInYz6Jdc6sec-D03xtMFAnSxpbxT_UBIJUIZJJkBUbNYWCW_OLgNjWPqFGimGw%3D%3D_V2&loc=US&title=Tech+Lead
EXCERPT: Tech Lead, SoC Design Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead a team of RTL Design engineers performing tasks related to IP development and/or SOC Design. Provide technical leadership to engineers and model best design practices (i.e., micro-architecture specifications, design reviews, code reviews, design methodology, etc.). Participate with architecture and system design teams in architecture definition, die area estimation, power optimization, and performance enhancements. Work closely with the multi-site cross-functional teams: Verification, Design for Test, Physical Design and Software teams to make design decisions and represent project status throughout the development process. Define microarchitecture for a subsystem/SoC top-level. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related
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TITLE: Designer - Chassis Systems
EMPLOYER: Harley-Davidson
LOCATION: Wauwatosa, WI (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
APPLY_URL: https://jobs.harley-davidson.com/job/Wauwatosa-Designer-Chassis-Systems-WI-53208/1386237800/
EXCERPT: Designer - Chassis Systems Wauwatosa, WI Auto req ID: 53798 Title: Job Function: Job Category Engineering Location: Workplace Category: Company: Full or Part-Time: Shift: At Harley-Davidson, we are building more than machines. It's our passion and commitment to continue the evolution of this storied brand, and heighten the desirability of the Harley-Davidson experience. To keep building our legend and leading our industry through innovation, evolution, and emotion we need the best and brightest talent. We stand for the timeless pursuit of adventure. Freedom for the soul. Are you ready to join us? The Harley-Davidson Motor Company Product Development Center (PDC) located in Wauwatosa, WI is home to the mantra - You dream it. We build it. Join our team as a. Job Summary This position is responsible for the CAD design and delivery of motorcycle components and systems from concept through production release. The Designer - Chassis Systems serves as a CAD designer supporting various motorcycle systems. This role focuses on detailed CAD modeling, large assembly management, drawing creation, and release while collaborating closely with engineers and cross-functional partners to meet quality, cost, timing, and manufacturability objectives. Job Responsibilities Designs, integrates, and delivers chassis component and system designs from concept development through production release. Creates and maintains complex CAD models, large virtual assemblies, and detailed engineering drawings using Creo Parametric, including advanced
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TITLE: System Design Engineer
EMPLOYER: Apple
LOCATION: San Francisco Bay Area, United States of America (unspecified)
SALARY: $120K-$210K
POSTED: 2026-04-20
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200658956/system-design-engineer?team=HRDWR
EXCERPT: System Design Engineer San Francisco Bay Area, United States of America Do you love working on challenges that no one has solved yet? Do you like changing the game? Envision what you could do here. At Apple, we believe new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. In this role, you will own and drive the electrical and physical design of multi-layer boards for prototype systems, developing reference designs that meet stringent area, cost, and performance requirements for product development. Work with cross-functional team to understand system requirements, from both physical design limitations and performance requirements Develop physical design implementations meeting stringent power and signal integrity requirement Drive co-optimization of physical design on MLB and package Provide implementation guidelines and feedback to silicon, package, and system design groups Perform feasibility study, design verification, and sign-off. Create custom PDN and SI routing feasibility on the system level for product PI/SI performance verification and help develop droop requirements for the system. Work with cross functional teams to incorporate requirements and system constraints to MLB routing feasibility layouts. Use BKM to create layouts satisfying droop requirements for PI. Work with Package team on codesign areas between MLB and Package design. Minimum Qualifications: Bachelor's degree. Preferred Qualifications: 4+ years experience in physical design of multi-layer boards (MLBs). Experience in circuit design, schematic capture, and system integration. Strong physical understanding of power and
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TITLE: DevOps Sr Principal Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: AUSTIN (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/AUSTIN/DevOps-Sr-Principal-Software-Engineer_R54117
EXCERPT: DevOps Sr Principal Software Engineer AUSTIN posted: Posted 30+ Days Ago
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TITLE: Hardware Designer
EMPLOYER: Syntronic
LOCATION: Boston, MA (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
APPLY_URL: https://jobs.lever.co/syntronic/a6aa03ed-b247-45b0-a9b9-2d9849f49acf
EXCERPT: Hardware Designer Boston, MA
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TITLE: DSP Product Marketing Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-02
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/DSP-Product-Marketing-Manager_R54933
EXCERPT: DSP Product Marketing Manager SAN JOSE posted: Posted 10 Days Ago
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TITLE: Staff Mechanical Design Engineer
EMPLOYER: Aurora Innovation, Inc.
LOCATION: Mountain View, California (unspecified)
SALARY: $181K-$262K
POSTED: 2026-04-13
APPLY_URL: https://aurora.tech/jobs/8496731002?gh_jid=8496731002
EXCERPT: Staff Mechanical Design Engineer Mountain View, California Who we are Aurora's mission is to deliver the benefits of self-driving technology safely, quickly, and broadly. The Aurora Driver will create a new era in mobility and logistics, one that will bring a safer, more efficient, and more accessible future to everyone. At Aurora, you will tackle massively complex problems alongside other passionate, intelligent individuals, growing as an expert while expanding your knowledge. For the latest news from Aurora, visit aurora.tech or follow us on LinkedIn . Aurora hires talented people with diverse backgrounds who are ready to help build a transportation ecosystem that will make our roads safer, get crucial goods where they need to go, and make mobility more efficient and accessible for all. Aurora is seeking a Staff Mechanical Design Engineer for the Compute Product Engineering team within the HPE (Hardware Product Engineering) group. The HPE Mechanical Design team is responsible for the development of all custom hardware modules in the Aurora Driver Kit (ADK) including Compute modules, Sensor Pods, and Lidar. The team works cross-functionally with EE, layout, CAE, Reliability, EMC, NPI, Operations, and other R&D teams to deliver the robust, scalable electro-mechanical solutions that power the Aurora Driver. Our team starts development at the earliest stages of product scoping and technology exploration and carries products through mass production at scale with our manufacturing partners. Role Overview In this role, you will lead the development of our next-generation Aurora Driver Module, which consists of the integration of our
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TITLE: Revenue Accounting Senior Analyst
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Revenue-Accounting-Senior-Analyst_R55094
EXCERPT: Revenue Accounting Senior Analyst SAN JOSE posted: Posted 3 Days Ago
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TITLE: Hardware Design Engineer, High Speed Networking
EMPLOYER: Arista Networks
LOCATION: Nashua, NH, United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/AristaNetworks/744000126581919-hardware-design-engineer-high-speed-networking
EXCERPT: Hardware Design Engineer, High Speed Networking Nashua, NH, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: Who You'll Work With Working closely with cross-functional teams including software, product management, marketing, and manufacturing, our engineers innovate new system architectures and develop high-speed PCBs requiring state-of the-art signal integrity and power integrity design practices. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is
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TITLE: Physical Design Technical Leader
EMPLOYER: Cisco
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-07
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Caesarea-Israel/Physical-Design-Technical-Leader_2003308
EXCERPT: Physical Design Technical Leader 2 Locations Cisco Silicon One is seeking a Physical Design Technical Leader. Meet the Team Physical Design team within Cisco Silicon One is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. We demonstrate the latest silicon technologies and processes to build the largest-scale and most complex devices, pushing the boundaries of feasibility. Your Impact You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. You'll handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, Optimization, Timing Closure, Design Floor Planning. Minimum Requirements A VLSI Design with extensive experience in backend design B.Sc./M.Sc. in Electrical Engineering. Strong understanding of Place & Route flow. 7+ years of hands-on experience in a relevant domain Preferred/Adva ntageous Qualifications Deep understanding of all aspects of Physical construction and Integration. Knowledge in Physical Design Verification methodology LVS/DRC. Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.). Great teammate, self-learning skills, and ability to work autonomously. #li-as6 Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology work together across the physical and digital worlds. These solutions provide customers with unparalleled security, visibility, and insights across the entire digital
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TITLE: Lead Software Engineer (UI Engineer)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BANGALORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Lead-Software-Engineer--UI-Engineer-_R52294
EXCERPT: Lead Software Engineer (UI Engineer) BANGALORE posted: Posted 30+ Days Ago
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TITLE: Cyber Security Software Developer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CESSON-SEVIGNE-01/Cyber-Security-Software-Developer_R53252
EXCERPT: Cyber Security Software Developer 2 Locations posted: Posted 30+ Days Ago
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TITLE: Staff Systems Engineer, Motion Control
EMPLOYER: Waymo
LOCATION: Mountain View, CA, USA (unspecified)
SALARY: $230K-$284K
POSTED: 2026-05-07
APPLY_URL: https://careers.withwaymo.com/jobs?gh_jid=7905387
EXCERPT: Staff Systems Engineer, Motion Control Mountain View, CA, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and you will report to Systems Engineering Manager. You will: - Derive requirements on trajectories and motion control algorithms, from safety goals and product performance objectives. - Lead the sign-off of hardware and software subsystems for new releases and expanded scope - Build analysis tools (e.g. dashboards, database queries, scripts) for large-scale analyses of Waymo's massive datasets. - Write risk assessments that trade off performance and reliability. -
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TITLE: Founding Product Designer (UI/UX)
EMPLOYER: Lance
LOCATION: San Francisco | OnSite (onsite)
SALARY: Not disclosed
POSTED: 2026-06-10
APPLY_URL: https://jobs.ashbyhq.com/lance/5a84b228-961d-41e8-9f2b-af6a8713533f
EXCERPT: Founding Product Designer (UI/UX) San Francisco | OnSite About Lance Lance (YC W26) builds autonomous AI agents that run hotel operations end-to-end, from answering guest calls to managing workflows across systems. We work with leading hotel groups across brands like Marriott, Hilton, and Hyatt, and are already deployed across 50+ properties in the U.S. Our agents don't just assist, they execute. They integrate directly into existing hotel systems, make real-time decisions, and handle complex, multi-step operations. Role Overview We're hiring our Founding Product Designer to own the end-to-end user experience of our AI agents and the platforms our customers use to interact with them. You will be responsible for establishing Lance's design language from the ground up, translating complex AI workflows into intuitive, elegant interfaces. This is a high-ownership role for a product-minded designer who wants to define the look, feel, and function of a category-defining product. What You'll Do - Own the entire design process, from concept and wireframing to high-fidelity mockups and interactive prototypes. - Translate complex user needs and product requirements into beautiful, intuitive, and functional user interfaces. - Work directly with the founders, product managers, and engineers to define both the long-term design vision and the short-term tactical execution. - Establish and own Lance's design system, ensuring a consistent and high-quality user experience across all platforms. - Conduct user research and usability testing to validate design decisions and advocate for the user. - Collaborate closely with engineering to bridge the gap between design and front-end implementation,
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TITLE: FPGA Prototyping Design Engineer
EMPLOYER: Apple
LOCATION: Sunnyvale, United States of America (unspecified)
SALARY: $127K-$221K
POSTED: 2026-04-27
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200660229/fpga-prototyping-design-engineer?team=HRDWR
EXCERPT: FPGA Prototyping Design Engineer Sunnyvale, United States of America Come join Apple's growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborating with people across different functional areas, and thriving during crisis times, we encourage you to apply. As an FPGA Prototyping Design Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will integrate industry standard and custom hardware IP into SoCs. You will work closely with SoC architects, IP developers to develop SoCs that meets the power, performance and area goals for Apple devices. You will help define the processes, methods and tools for design and implementation of large complex SoCs. You will develop and maintain methodology and flows checks for your design. Interact with our verification team to ensure appropriate validation and coverage goals are met. You'll ensure security assumptions for the chip are accurately implemented within the block/s. Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the
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TITLE: Resident Engineer – Service Provider Routing and Switching Design Consultant (Mt Laurel, NJ)
EMPLOYER: Hewlett Packard Enterprise
LOCATION: All, New Jersey, United States of America (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-05
K401_MATCH: yes (not source-backed)
CHILDCARE_SUBSIDY: yes (not source-backed)
APPLY_URL: https://hpe.wd5.myworkdayjobs.com/Jobsathpe/job/All-New-Jersey-United-States-of-America/Resident-Engineer---Service-Provider-Routing-and-Switching-Design-Consultant--Mt-Laurel--NJ-_1204155/apply
EXCERPT: Resident Engineer – Service Provider Routing and Switching Design Consultant (Mt Laurel, NJ) All, New Jersey, United States of America Embrace the role of a Resident Engineer - Service Provider Routing and Switching Design Consultant, supporting and expanding your expertise in Juniper network design and switching. Leverage your hands-on experience with large-scale IP networks, automation tools, and customer engagement to drive innovative solutions and ensure seamless network operations for our clients.
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TITLE: Display System Engineer, Platform Architecture
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $172K-$258K
POSTED: 2026-01-23
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200642673/display-system-engineer-platform-architecture?team=HRDWR
EXCERPT: Display System Engineer, Platform Architecture Cupertino, United States of America Do you love working on state-of-the-art technologies? Are you a forward-thinker and love solving technological and architectural challenges? At Apple, our Platform Architecture team features a collaborative and hands-on environment that cultivates engineering excellence, creativity, and innovation! Join this team, and you'll collaborate with engineers across Apple to develop algorithms and architectures that help build the flawless technology experiences we're known for worldwide! In this highly visible role, you will lead the architecture of SoC display subsystem, including memory fabric interface, data pipe flow controls, memory compression, display interfaces, etc. The ideal candidate will be responsible for all aspects of SoC display subsystem architecture. Work closely with SoC and fabric architects, software, and system engineers to architect SoC display subsystem Architect display subsystems, including display pipe control, memory, and interfaces Provide detailed architectural guidance at all levels of design throughout the design process from concept through production Make recommendations on key design tradeoffs across architecture and performance Author and maintain the display subsystem architecture specifications Minimum Qualifications: BS degree Experience in chip architecture, display subsystem architecture and/or design Experience in SoC display subsystem architecture and micro-architecture Preferred Qualifications: 10+ years of relevant industry experience in signal/image processing MS or PhD degree Understanding of SoC display sub-system architecture, interface, performance and energy tradeoffs Understanding of display or image technology Expertise in memory subsystem, memory interface, and DMA Architectural modeling ability Communication skills with cross-functional teams
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TITLE: Senior Data Operations Manager
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-02
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Technical-Business-Development-Manager_R53706
EXCERPT: Senior Data Operations Manager SAN JOSE posted: Posted 10 Days Ago
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TITLE: Software Engineer II - AI Focused
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BELO HORIZONTE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BELO-HORIZONTE/Software-Engineer-II---AI-Focused_R54711
EXCERPT: Software Engineer II - AI Focused BELO HORIZONTE posted: Posted Today
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TITLE: SoC - Chiplet Design Lead
EMPLOYER: TensTorrent
LOCATION: Toronto, Ontario, Canada (unspecified)
SALARY: Not disclosed
POSTED: 2024-08-02
APPLY_URL: https://job-boards.greenhouse.io/tenstorrent/jobs/4442834007
EXCERPT: SoC - Chiplet Design Lead Toronto, Ontario, Canada Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. The SoC Chiplet Design Lead will drive the design and development of advanced System-on-Chip (SoC) architectures targeting AI, HPC and automotive markets that push the boundaries of performance, scalability, and efficiency. You'll lead cross-functional teams through the entire SoC lifecycle-from concept and architecture through RTL, verification, and tape-out-while ensuring design excellence and integration success. This role is hybrid , based out of Toronto, Ottawa, Boston, Austin, or Santa Clara , with potential for remote work within North America on a case-by-case basis. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - Deep background in SoC and chiplet design, with expertise in RTL design (Verilog/SystemVerilog) and digital architecture. - Experienced in cross-functional collaboration, partnering with system, verification, physical
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TITLE: Mechanical Design Engineer
EMPLOYER: Avery Dennison
LOCATION: Conway, AR, United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
PARENTAL_LEAVE_WEEKS: 8 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 8 (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/AveryDennison/744000130282339-mechanical-design-engineer
EXCERPT: Mechanical Design Engineer Conway, AR, United States Company Description: Avery Dennison Corporation (NYSE: AVY) is a global materials science and digital identification solutions company. We are Making Possible™ products and solutions that help advance the industries we serve, providing branding and information solutions that optimize labor and supply chain efficiency, reduce waste and mitigate loss, advance sustainability, circularity and transparency and better connect brands and consumers. We design and develop labeling and functional materials, radio-frequency identification (RFID) inlays and tags, software applications that connect the physical and digital and offerings that enhance branded packaging and carry or display information that improves the customer experience. Serving industries worldwide - including home and personal care, apparel, general retail, e-commerce, logistics, food and grocery, pharmaceuticals and automotive - we employ approximately 35,000 employees in more than 50 countries. Our reported sales in 2025 were $8.9 billion. Learn more at www.averydennison.com . At Avery Dennison, some of the great benefits we provide are: Health & Wellness benefits starting on day 1 of employment Paid parental leave 401K eligibility Tuition reimbursement Employee Assistance Program eligibility / Health Advocate Paid vacation and Paid holidays Job Description: Vestcom, an Avery Dennison Company, designs and builds its own converting and robotic equipment that supports the manufacture and production of our high-quality retail labeling and pricing solutions. We are seeking a Mechanical Design Engineer to join our Machine Group in Conway, AR. This role is responsible for the design, improvement, and support of our custom manufacturing and automation systems
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TITLE: Principal Software Engineer-Mesh
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SHANGHAI (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SHANGHAI/Meshing-Engineering-Developer_R51346
EXCERPT: Principal Software Engineer-Mesh SHANGHAI posted: Posted 30+ Days Ago
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TITLE: SoC Integration and Synthesis Engineer
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $147K-$272K
POSTED: 2025-10-30
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200629242/soc-integration-and-synthesis-engineer?team=HRDWR
EXCERPT: SoC Integration and Synthesis Engineer Cupertino, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, smart people and inspiring, innovative technologies are the norm here. Join us to help deliver the next phenomenal Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our dynamic group, you will be part of a group that defines flows and methodologies in all these fields that help Apple implement complex chips with the best QOR (quality of results) and PPA (power, performance, and area) using cutting-edge technologies. We are searching for a talented engineer to join our exciting team of problem solvers. As an SOC/ASIC Integration & Synthesis Engineer, you will have responsibilities spanning various aspects of SOC design: - Drive all front-end integration activities like Integration, Synthesis, UPF, Logical Equivalence, ECO, etc. - Work closely on methodology improvements for improving synthesis QOR. - Work on Low power design, writing UPFs, close on power intent verification at the chip level. - Work on RTL integration, timing constraints, and synthesis of designs. - Knowledge of FE flows like Lint & LEQ and scripting is a plus Work closely with other engineers that are members of the SOC Design, SOC Design Verification, Emulation, STA, Power, and Physical Design teams. Minimum Qualifications: BS degree
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TITLE: Scientific Software Developer - Affinity
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/Santa-Fe-New-Mexico/Scientific-Software-Developer---Affinity_R43349-1
EXCERPT: Scientific Software Developer - Affinity 2 Locations posted: Posted 30+ Days Ago
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TITLE: Mechanical Engineer, Cooling System Modular Design
EMPLOYER: Google
LOCATION: Reno, NV, USA; +4 more (unspecified)
SALARY: $144K-$209K
POSTED: 2026-06-04
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcYcYmiM6_czPsBla74x1YRl6JLAetZxpdGkkIzwT5mOEjoACxwdTLvsBzR98C93a3xjYlAw4SG2Y5f1c7kZhrnmx_HdMZpsY6B49bXK6HlD1LZZxt3kKYmmek1g_V2&loc=US&title=Mechanical+Engineer
EXCERPT: Mechanical Engineer, Cooling System Modular Design Reno, NV, USA; +4 more Our thirst for technology is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and development department -- cutting-edge strategies are born, tested and tested again. Along with a team of great minds, you take on complex topics like how we use power or how to run state-of-the-art, environmentally-friendly facilities. You're a visionary who optimizes for efficiencies and never stops seeking improvements -- even small changes that can make a huge impact. You generate ideas, communicate recommendations to senior-level executives and drive implementation alongside facilities technicians. With your technical expertise, you ensure compliance with codes and standards, develop infrastructure improvements and serve as an expert in your specialty (e.g., cooling, electrical). As a Mechanical Engineer within the Data Center Technology Systems team, you will serve as a technical lead for our global mechanical infrastructure. You will pioneer next-generation cooling systems, innovating custom components and integrating modular design and pre-fabrication strategies to accelerate construction. Collaborating across Planning, Operations, and Execution teams, you will lead new technologies to optimize future products for Google's machine learning fleet. You will leverage advanced software tools to conduct detailed thermal analysis, computational fluid dynamics, and hydraulic modeling of complex air and waterside systems. Your deep understanding of thermodynamics will drive the creation of critical engineering specifications and commissioning plans. A concise communicator, you will deliver actionable recommendations
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TITLE: IT- Staff Software Security Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: 2 Locations (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/NOIDA/IT--Staff-Software-Security-Engineer_R50275
EXCERPT: IT- Staff Software Security Engineer 2 Locations posted: Posted 30+ Days Ago
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TITLE: Lead C++ Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Lead-Software-Engineer_R44516
EXCERPT: Lead C++ Software Engineer SAN JOSE posted: Posted 30+ Days Ago
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TITLE: SoC Physical Design Engineer, STA/Timing
EMPLOYER: Apple
LOCATION: San Diego, United States of America (unspecified)
SALARY: $172K-$302K
POSTED: 2026-04-16
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200658163/soc-physical-design-engineer-sta-timing?team=HRDWR
EXCERPT: SoC Physical Design Engineer, STA/Timing San Diego, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it! Join us to help deliver the next groundbreaking Apple product. In this visible role, you will be directly responsible for the physical implementation of design partition(s) (from netlist to tapeout) for a highly complex SOC using state of the art process technology. - Work with design teams to understand and debug constraints and facilitate logic changes to improve timing. - Work with the Physical Design team, highlighting issues and best practices. - Help create timing ECO's for project tapeout. - Create and maintain scripts and methodologies for analysis and runs. - Create documentation and help with guidelines/specs. - Deep analysis of timing paths to identify key issues. - Implement timing infrastructure. Minimum Qualifications: Minimum BS and 10+ years of relevant industry experience. Experience with large design STA and Timing Closure. Programming skills with Perl and TCL. Preferred Qualifications: Hands-on experience in STA. Familiar with important aspects of timing of
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TITLE: Lead Software Engineer for Virtuoso ADE
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BEIJING (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Lead-Software-Engineer-for-Virtuoso-ADE_R51742
EXCERPT: Lead Software Engineer for Virtuoso ADE BEIJING posted: Posted 30+ Days Ago
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TITLE: Lead Software Engineer - AI/LLM for Virtuoso
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BEIJING (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BEIJING/Lead-Software-Engineer---AI-LLM-for-Virtuoso_R53270-1
EXCERPT: Lead Software Engineer - AI/LLM for Virtuoso BEIJING posted: Posted 30+ Days Ago
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TITLE: Circuits Physical Design Engineer - Library/Process Monitor
EMPLOYER: Apple
LOCATION: Beaverton, United States of America (unspecified)
SALARY: $142K-$259K
POSTED: 2026-05-05
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200661650/circuits-physical-design-engineer-library-process-monitor?team=HRDWR
EXCERPT: Circuits Physical Design Engineer - Library/Process Monitor Beaverton, United States of America Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Your efforts will be groundbreaking. Your efforts will be groundbreaking. Join us, and you'll help design the tools that allow us to bring customers experiences they've never before envisioned! We have an extraordinary opportunity for Physical Design Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with foundation IP developers on silicon validation, making a critical impact delivering products to market quickly. Imagine yourself at the center of our SOC design effort, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of hardworking engineers. As a Physical Design Engineer, you will be responsible for fully comprehensive library EDA view validation, by taking a P&R block through RTL to GDS steps. This will include physical synthesis, placement, CTS, routing, timing optimization, leakage recovery and closure & signoff. You will also be responsible for PT/spice correlation, signal and power EM analysis, IR analysis and PDV. You will also architect and compose
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TITLE: Group Director, HR M&A
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-09
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Group-Director---HR-M-A_R54905-1
EXCERPT: Group Director, HR M&A SAN JOSE posted: Posted 3 Days Ago
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TITLE: Principal Software Engineer (UI Engineer)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: BANGALORE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/BANGALORE/Principal-Software-Engineer--UI-Engineer-_R52292
EXCERPT: Principal Software Engineer (UI Engineer) BANGALORE posted: Posted 30+ Days Ago
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TITLE: System Integration Lead, Pixel Watch
EMPLOYER: Google
LOCATION: Mountain View, CA, USA (unspecified)
SALARY: $236K-$330K
POSTED: 2026-06-05
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdxVgqmA5QVhxJpEE4vAEkBsVAChoU0JsExYzEftLZfgEjsACxwdTLrC852RyCY_toYMbCtdCxcHIreo94mS36uXdIvgRQd7BhDip7Sk22-NXYlauivE5hvkTZkP4g%3D%3D_V2&loc=US&title=System+Integration+Lead
EXCERPT: System Integration Lead, Pixel Watch Mountain View, CA, USA As a member of a fast-paced multi-disciplinary team, you use your creativity and range of engineering experience to explore solutions to a variety of engineering problems. As a mechanical engineer, you participate in the design, analysis, and prototyping of new concepts. You work in a manufacturing and product oriented development environment and collaborate with vendors and outside sources in order to see parts through to manufacture. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $236000 - $330000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Identify, integrate, and validate cutting-edge technologies to enhance the next iteration of our products. Collaborate closely with a team of system architects, industrial designers, and product managers, contributing to the early definition of new products and the exploration of emerging technologies. Be able to maximize comfort and fit within an iconic design, all while delivering performance. Ensure seamless integration of these new technologies into the product line, encompassing module and system design, validation, and correlation. Partner with our operations teams during the early stages of system integration to establish and maintain high quality and yield standards. Minimum qualifications: Bachelor's degree in Mechanical Engineering, Product Design, or related field, or equivalent practical experience. 12 years of experience designing mechanical components such as plastic or metal parts, mechanical assemblies, printed circuit boards, or flexes. 12 years of experience using Computer-Aided
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TITLE: Cloud Support Engineer - Managed Cloud Services
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-11
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Cloud-Support-Engineer---Managed-Cloud-Services_R54644
EXCERPT: Cloud Support Engineer - Managed Cloud Services SAN JOSE posted: Posted Yesterday
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TITLE: Design Verification Engineer - SoC
EMPLOYER: Etched
LOCATION: Austin (unspecified)
SALARY: Not disclosed
POSTED: 2026-04-16
MENTAL_HEALTH_SUPPORT: yes (not source-backed)
APPLY_URL: https://jobs.ashbyhq.com/etched/33adf31c-e0ad-4080-bb83-1b3859f95d35
EXCERPT: Design Verification Engineer - SoC Austin About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are seeking a Design Verification Engineer to join our Systems/Performance Verification team. You will ensure the custom IPs powering Sohu - including systolic arrays, DMA engines, and NoCs - are robust, high-performance, and silicon-ready. This role demands creativity, deep technical ability, and the drive to tackle complex verification challenges. You will collaborate with architects, RTL designers, and SW/FW/emulation teams to validate correctness and performance across the full hardware-software stack. Key responsibilities - Work closely with architects and RTL designers on verifying the performance features of the design and correlating with performance models (both pre-silicon and post-silicon). - Work closely with software and application developers on identifying performance bottlenecks and tuning the software. - Develop test plans and test infrastructure/tools for performance tuning, correlation, and verification. - Improve and maintain the architectural performance models. - Develop tests in SystemVerilog, Python, or vectors to debug and correlate the RTL and performance model. - Develop SystemVerilog or Python-based checkers for verifying the performance
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TITLE: Lead MTS Physical Design/STA
EMPLOYER: Rambus INC
LOCATION: Bangalore, KA, IN (unspecified)
SALARY: Not disclosed
POSTED: 2025-10-29
K401_MATCH: yes (not source-backed)
APPLY_URL: https://careers-rambus.icims.com/jobs/22355/lead-mts-physical-design-sta/job
EXCERPT: Lead MTS Physical Design/STA Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Static Timing Analysis Engineer to join our STA team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Complete ownership of Static timing analysis at full chip level for high speed mixed signal design Experience doing multi-mode multi-corner (MMMC) timing and power analysis using primetime/Tempus. Experience in DMSA/Tweaker ECO flows for PPA improvements. Experience in manual timing fixes, ECO generation for MCMM mode corners. Good understanding of SDC constraints and able to translate timing requirements into constraints. Responsible for integrating the blocks, analog Ip's for full chip timing analysis. Well aware of place and route methodologies and hands on experience with timing convergence Good communication skill to negotiate with top level for convergence. Work closely with Project leader for creating schedule, tracking and raising issues / risks to project management. Participate in Mentoring new joiners in the group on technical skills. Provide inputs for CAD/DA team from Design Implementation perspective. Work closely with Logic design team and Analog teams to provide inputs from physical design and STA. Work closely with DFT team on scan aspects and provide inputs from physical design. Continuously work on methodology and productivity improvements. Qualifications Must have at least 10 - 12 years of experience, out of which
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TITLE: SoC Physical Design Methodology Engineer
EMPLOYER: Apple
LOCATION: Austin, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2026-04-08
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200656418/soc-physical-design-methodology-engineer?team=HRDWR
EXCERPT: SoC Physical Design Methodology Engineer Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! Come help us design the next generation of revolutionary Apple products. We're looking for a forward-thinking and unusually talented engineer. As a member of our dynamic group, you will have the rare and rewarding opportunity to craft and implement methodologies with a high impact on upcoming products that will delight and inspire millions of Apple's customers every single day. In this role, you'll be directly involved in our physical design methodology efforts, collaborating right alongside our internal multi-functional teams to ensure our SoCs achieve the optimal power, performance, and area (PPA) in the most efficient way possible. We account for every nanowatt, every nanometer, and every picosecond from theory to silicon. As a Physical Design Methodology engineer you will be an active participant in the team responsible for ensuring our physical design methodology is efficient, robust, and reliable. You will
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TITLE: Display System Architect, Platform Architecture
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $201K-$302K
POSTED: 2026-04-24
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200660008/display-system-architect-platform-architecture?team=HRDWR
EXCERPT: Display System Architect, Platform Architecture Cupertino, United States of America Do you love working on state-of-the-art technologies? Are you a forward-thinker and love solving technological and architectural challenges? At Apple, our Platform Architecture team features a collaborative and hands-on environment that cultivates engineering excellence, creativity, and innovation. Join this team, and you'll collaborate with engineers across Apple to develop algorithms and architectures that help build the flawless technology experiences we're known for worldwide! In this highly visible role, you will lead the architecture of SoC display subsystem, including memory fabric interface, data pipe flow controls, memory compression, display interfaces, etc. The ideal candidate will be responsible for all aspects of SoC display subsystem architecture. Work closely with SoC and fabric architects, software, and system engineers to architect SoC display subsystem Architect display subsystems, including display pipe control, memory, and interfaces Provide detailed architectural guidance at all levels of design throughout the design process from concept through production Make recommendations on key design tradeoffs across architecture and performance Author and maintain the display subsystem architecture specifications Minimum Qualifications: BS degree Experience in chip architecture, display subsystem architecture and/or design SoC display subsystem architecture and micro-architecture experience Preferred Qualifications: 20+ years of relevant industry experience in signal/image processing MS or PhD degree Understanding of SoC display sub-system architecture, interface, performance and energy tradeoffs Understanding of display or image technology Expertise in memory subsystem, memory interface, and DMA Architectural modeling ability Communication skills with cross-functional teams
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TITLE: Sr. Business Development Manager - Cloud
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: HSINCHU 05 (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/HSINCHU-05/Sr-Business-Development-Manager---Cloud_R51821
EXCERPT: Sr. Business Development Manager - Cloud HSINCHU 05 posted: Posted 30+ Days Ago
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TITLE: Hardware Systems Design Engineer, Platforms Infrastructure
EMPLOYER: Google
LOCATION: Sunnyvale, CA, USA (unspecified)
SALARY: $132K-$190K
POSTED: 2026-06-04
PARENTAL_LEAVE_WEEKS: 18 (not source-backed)
NON_BIRTH_PARENT_LEAVE_WEEKS: 18 (not source-backed)
K401_MATCH: yes (not source-backed)
APPLY_URL: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRZmtfRvVBjJ-7uhYzx3ufxX0quP83h2AHdpF8am0954EjsACxwdTG7uppRRMOr7lp1iz9xMcPkhZHUn95ROTB4osSDs4q_0XXa-MNkxSXjoHBZ7YHjPXCzZkRO7vA%3D%3D_V2&loc=US&title=Hardware+Systems+Design+Engineer
EXCERPT: Hardware Systems Design Engineer, Platforms Infrastructure Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Our team designs and builds the hardware, software, and networking technologies that power all of Google's services. As a Hardware Design Engineer, you will design and build the systems that are the heart of a large and powerful computing infrastructure. You will see those systems from concept all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users. As a part of the Board and System Design team, you will work on hardware systems projects to craft solutions for current and future data center deployments. You will work with product teams to ensure that customer goals are met with your systems, ASIC/FPGA, Software, and Verification teams to ensure proper verification of features in your systems, manufacturing teams to ensure that your designs are manufacturable and ready for volume production, and field teams to support systems that are deployed in the data center. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google
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TITLE: Staff Technical Solution Engineering
EMPLOYER: Databricks
LOCATION: McLean, Virginia (unspecified)
SALARY: $153K-$211K
POSTED: 2026-06-12
NON_BIRTH_PARENT_LEAVE_WEEKS: 12 (not source-backed)
APPLY_URL: https://databricks.com/company/careers/open-positions/job?gh_jid=8589169002
EXCERPT: Staff Technical Solution Engineering McLean, Virginia About Databricks At Databricks, we are passionate about enabling data teams to solve the world's toughest problems - from making the next mode of transportation a reality to accelerating the development of medical breakthroughs. We do this by building and running the world's best data and AI infrastructure platform so our customers can use deep data insights to improve their business. Founded by engineers - and customer obsessed - we leap at every opportunity to solve technical challenges, from designing next-gen UI/UX for interfacing with data to scaling our services and infrastructure across millions of virtual machines. And we're only getting started. The Role As data and Generative AI applications become increasingly foundational to public sector modernization and national security, safeguarding the infrastructure that powers them is paramount. Databricks is looking for a Staff Technical Solution Engineer to join our Cleared Engineering team in McLean, VA. This team sits at the critical intersection of core infrastructure operations and active platform reliability, ensuring our multi-cloud data enclaves and advanced AI software run flawlessly inside highly secure, air-gapped partitions. In this role, you will move beyond reactive ticketing to tackle complex system and network environment blocks, serving as a primary technical pillar for our secure GovCloud operations. This position offers a unique opportunity to own the operational integrity of high-side platform interactions. You will be responsible for executing sophisticated debugging, deep-dive environment analysis, and running specialized tooling and scripts to unblock internal engineering teams. Operating within
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TITLE: Senior Hardware Design Engineer, High Speed Networking
EMPLOYER: Arista Networks
LOCATION: Nashua, NH, United States (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/AristaNetworks/744000126582409-senior-hardware-design-engineer-high-speed-networking
EXCERPT: Senior Hardware Design Engineer, High Speed Networking Nashua, NH, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: Who You'll Work With Working closely with cross-functional teams including software, product management, marketing, and manufacturing, our engineers innovate new system architectures and develop high-speed PCBs requiring state-of the-art signal integrity and power integrity design practices. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team
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TITLE: Lead Hardware Design Engineer
EMPLOYER: PA Consulting
LOCATION: Melbourn, , United Kingdom (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-10
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.smartrecruiters.com/PAConsulting/744000130221939-lead-hardware-design-engineer
EXCERPT: Lead Hardware Design Engineer Melbourn, , United Kingdom Company Description: We believe in the power of ingenuity to build a positive human future. As strategies, technologies, and innovation collide, we create opportunity from complexity. Our teams of interdisciplinary experts combine innovative thinking and breakthrough technologies to progress further, faster. Our clients adapt and transform, and together we achieve enduring results. We are over 4,000 strategists, innovators, designers, consultants, digital experts, scientists, engineers, and technologists. And we have deep expertise in consumer and manufacturing, defence and security, energy and utilities, financial services, government and public services, health and life sciences, and transport. Our teams operate globally from offices across the UK, Ireland, US, Nordics, and Netherlands. PA. Bringing Ingenuity to Life. Job Description: We are looking for a Lead hardware design engineer with a broad skill set and a passion for creating electronic products.. Working closely with our clients and the wider PA team, you will be called upon to develop solutions at the system level as well as take on the detailed electronic design work required to realise your concept. Our primary industry sectors are Consumer, Defence and Security, Health and Life Sciences and we look for someone who is comfortable working across all of these sectors. Sharing ideas across sectors is embedded within our way of working. Become part of the team At PA, you will be working within one of the most successful UK organisations in technology and product development, with a team who have an exceptional reputation
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TITLE: Physical Design/CAD Engineer
EMPLOYER: Astera Labs
LOCATION: San Jose, California, United States (unspecified)
SALARY: $135K-$195K
POSTED: 2026-03-31
K401_MATCH: yes (not source-backed)
APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4679751005
EXCERPT: Physical Design/CAD Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key Responsibilities - As Physical Design CAD Engineer you will support and build flows for world class EDA tools. - Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. - Architect and recommend flow improvements and enhance existing methodology for high performance design. - Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. - Work with cross function teams to define requirements and specifications
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TITLE: iSE neo Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: CESSON SEVIGNE 01 (unspecified)
SALARY: Not disclosed
POSTED: 2026-06-08
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/CESSON-SEVIGNE-01/iSE-neo-Software-Engineer_R54024
EXCERPT: iSE neo Software Engineer CESSON SEVIGNE 01 posted: Posted 4 Days Ago
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TITLE: Watch Systems Architect
EMPLOYER: Apple
LOCATION: Cupertino, United States of America (unspecified)
SALARY: $181K-$318K
POSTED: 2026-03-14
K401_MATCH: yes (not source-backed)
APPLY_URL: https://jobs.apple.com/en-us/details/200651751/watch-systems-architect?team=HRDWR
EXCERPT: Watch Systems Architect Cupertino, United States of America The Watch Systems Architecture team is seeking a hands-on engineer to help shape the future of wearable technology. As a key member of our team, you'll support the development of next-generation products through a combination of architecture work, prototyping, analysis, and technical validation. You'll have the opportunity to dive deep into system-level challenges, work closely with architects and engineers across various disciplines, and contribute to a product that impacts millions of users worldwide. We are looking for a candidate with a strong foundation in Electrical and/or Computer Engineering, experience with system design and validation, and a passion for technical problem-solving. The ideal candidate will thrive in a collaborative environment and demonstrate the ability to translate system requirements into practical implementations, simulations, and test plans. System Design & Analysis: Contribute to the architecture and design of Watch systems, working alongside senior architects to define specifications and evaluate design trade-offs. Develop simulations and analytical models to predict system behavior and validate design decisions. Particular emphasis is paid to power consumption, and conversion, Definition of PMIC (Power Management IC) and peak power management. Technical Validation & Characterization: Build prototypes and develop test plans to validate new features and system improvements. Conduct measurements and analyses to characterize performance, identify optimization opportunities, and ensure robust system operation. Data Analysis & Modeling: Create and maintain analysis scripts and tools to process measurement data, generate insights, and support design decisions. Develop simulation models to explore design spaces and predict
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TITLE: Product Marketing Manager (Clarity Electromagnetic)
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Product-Marketing-Manager--Clarity-Electromagnetic-_R51954-1
EXCERPT: Product Marketing Manager (Clarity Electromagnetic) SAN JOSE posted: Posted 30+ Days Ago
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TITLE: Senior Principal C++ Software Engineer
EMPLOYER: Cadence Design Systems, Inc.
LOCATION: SAN JOSE (unspecified)
SALARY: Not disclosed
POSTED: 2026-05-12
K401_MATCH: yes (not source-backed)
APPLY_URL: https://cadence.wd1.myworkdayjobs.com/External_Careers/job/SAN-JOSE/Senior-Principal-C---Software-Engineer_R54404
EXCERPT: Senior Principal C++ Software Engineer SAN JOSE posted: Posted 30+ Days Ago
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