I'm looking for a job. I exported this list from FewerJobs.com - a curated job board. Please: 1. Rank these jobs by fit for me, given my resume / skills. 2. Highlight the top 5 with a one-sentence rationale each. 3. Flag any concerns, including benefit values without source-backed evidence. 4. Suggest one or two filter changes I could make on FewerJobs to find more good matches. Filters I applied: - q: Astera Labs - quality_floor: default - match_401k_strict: true - parental_strict: true - non_birth_strict: true - pto_strict: true - include_older: false - apply_url_verified: false - page: 2 - per_page: 100 - sort: relevance Jobs (100 total): --- TITLE: Principal Silicon Validation Engineer, SerDes/PAM4 EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $185K-$230K POSTED: 2026-02-18 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4662564005 EXCERPT: Principal Silicon Validation Engineer, SerDes/PAM4 San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers' requirements in the highest regard and is solely responsible for certifying a product's parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. Basic Qualifications: - Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred. - 8 + years' --- TITLE: Senior HR Business Partner, Engineering EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $133K-$185K POSTED: 2026-03-31 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4679389005 EXCERPT: Senior HR Business Partner, Engineering San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior HR Business Partner to join our People team in San Jose, CA. In this high-impact role, you will partner directly with engineering organizations-serving as a trusted advisor, coach, and strategic partner to engineering leaders, managers, and employees across our technical teams. You will bring deep HRBP/Generalist experience, strong employee relations expertise, and substantial knowledge of US labor and employment law to ensure our people practices are both effective and compliant as we scale. This role is critical to supporting the talent strategies, people leader development, and organizational health that enable our engineering teams to deliver world-class AI infrastructure connectivity products. Key Responsibilities 1. Engineering Partnership & Coaching - Serve as a trusted partner to engineering people leaders, providing hands-on coaching on people management, team dynamics, and leadership effectiveness - Build strong relationships across all levels ensuring employees and managers --- TITLE: Principal Product Application Engineer - Leo EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $175K-$230K POSTED: 2026-04-29 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4690430005 EXCERPT: Principal Product Application Engineer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners - owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp. Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams. This position is required onsite in San Jose, CA. Key Responsibilities - Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms - Develop, validate, and debug firmware using --- TITLE: Principal Silicon Validation Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $250K-$250K POSTED: 2025-12-23 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4613831005 EXCERPT: Principal Silicon Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product's parametric compliance. Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs. Basic Qualifications: - Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred. - ≥10 years experience --- TITLE: Category Sourcing Manager – Capital Equipment & IT (6-Month Contract) EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-05 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4703738005 EXCERPT: Category Sourcing Manager – Capital Equipment & IT (6-Month Contract) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Contract Sourcing Manager to support sourcing and procurement activities across capital equipment, IT hardware, and corporate services . This is a 6-month contract role designed to provide hands-on execution support during a period of rapid growth and infrastructure scaling. This role will focus on supplier sourcing, commercial negotiations, and procurement execution , working closely with engineering, IT, facilities, and operations teams. The ideal candidate brings 6+ years of diverse sourcing experience , with a strong emphasis on hardware, capital equipment, and technical environments . This role is highly execution-oriented and requires the ability to independently manage sourcing initiatives, drive timelines, and deliver cost-effective and scalable supplier solutions. High-performing individuals may be considered for full-time conversion based on business needs. Key Responsibilities - Lead sourcing and procurement activities across: - Capital equipment (lab, test, and infrastructure --- TITLE: Principal Engineer, STA EMPLOYER: Astera Labs LOCATION: Bengaluru, Karnataka, India (unspecified) SALARY: Not disclosed POSTED: 2026-06-03 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4700203005 EXCERPT: Principal Engineer, STA Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is hiring a Principal Engineer, Static Timing Analysis to own top-level timing closure and signoff for our next-generation connectivity silicon powering rack-scale AI infrastructure. In this role, you'll drive full-chip STA strategy across advanced process nodes, partner with physical design, RTL, DFT, and CAD teams, and ensure first-pass timing success on some of the most complex SoCs in the industry. This is a high-impact technical leadership role at a hyper-growth company purpose-built for AI connectivity. Your work directly enables the PCIe, CXL, UALink, and Ethernet platforms that hyperscalers depend on - and you'll have the ownership, influence, and tooling to do the best work of your career. Key Responsibilities - Full-Chip STA Signoff & Timing Closure - Own end-to-end top-level STA signoff across multiple modes, corners, and operating conditions (MMMC) for complex AI connectivity SoCs - Drive timing convergence on advanced process nodes (5nm/4nm/3nm and below) from --- TITLE: Sales Operations Specialist EMPLOYER: Astera Labs LOCATION: Taipei, Taiwan (unspecified) SALARY: Not disclosed POSTED: 2026-04-09 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4682576005 EXCERPT: Sales Operations Specialist Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Department: Sales Operations Reports To: Sales Operations Director Location: Taiwan Employment Type: Full-Time Position Overview: We are seeking a highly organized and detail-oriented entry-level candidate to support our sales operations in a fast-paced, high-tech environment. This role is responsible for processing customer purchase orders for Astera Labs product portfolio-ensuring compliance with internal policies, licensing terms, and revenue recognition guidelines. You will collaborate closely with Sales, Legal, Finance, Quality, Supply Chain and Logistics teams to ensure orders are booked, billed, and delivered accurately and on time. Key Responsibilities: - Review and enter orders into the order management system (e.g., Oracle ERP) including customer purchase orders (POs), samples and RMAs - Validate orders for accuracy, contract terms, licensing details, and revenue recognition compliance (SOX compliance and ISO) - Coordinate with Sales, Legal, and Finance to resolve order discrepancies, billing issue, payment term/incoterm compliance or missing documentation - Track order status, fulfillment timelines, and escalate --- TITLE: HR Operations & People Analytics Lead EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $125K-$155K POSTED: 2026-05-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4701246005 EXCERPT: HR Operations & People Analytics Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking an HR Operations & People Analytics Lead to help scale and strengthen our HR infrastructure during a period of rapid growth. This individual contributor role will report to the Director, HR Operations and will sit at the intersection of HR operations, systems, process execution, and workforce analytics. This role is ideal for someone who enjoys owning high-impact operational work end-to-end while also building the dashboards, reporting, and insights that help HR and business leaders make better decisions. The right candidate is highly detail-oriented, systems-minded, analytically strong, and comfortable working across both day-to-day execution and longer-term process improvement. You will partner closely with HR, Talent Acquisition, IT, Finance, and business stakeholders to improve employee lifecycle processes, strengthen HR data integrity, support system optimization, and develop meaningful people insights. This is an opportunity to play a key role in building a scalable, --- TITLE: Principal Package Thermal & Mechanical Engineer EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $185K-$230K POSTED: 2026-03-28 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4678609005 EXCERPT: Principal Package Thermal & Mechanical Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Principal Package Thermal & Mechanical Engineer at Astera Labs, you will serve as a technical leader driving the development and modeling of advanced IC packaging solutions that enable next-generation AI and high-performance connectivity systems. In this highly visible role, you will define and execute thermal and mechanical modeling strategies across the chip-package-board system, influencing package architecture, material selection, and reliability design. You will partner closely with package design, SIPI, silicon, system, and manufacturing teams to ensure robust thermal/mechanical performance and first-pass success. You will also drive modeling methodologies, correlation strategies, and best-known methods (BKMs), while engaging directly with customers to translate complex simulation insights into actionable system-level solutions. Key Responsibilities - Thermal & Mechanical Modeling Leadership - Define and drive thermal and mechanical modeling strategies for advanced packages (FCBGA, FCCSP, multi-die, and chiplet-based architectures) - Perform detailed thermal simulations including steady-state and --- TITLE: Principal Product Applications Engineer - Ethernet EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $158K-$230K POSTED: 2026-05-20 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697283005 EXCERPT: Principal Product Applications Engineer - Ethernet San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Principal Product Applications Engineer to join our Taurus Ethernet Smart Cable Modules team and drive customer success at the forefront of AI infrastructure connectivity. As data centers scale to meet explosive AI workload demands, our Taurus products are enabling the high-bandwidth, low-latency Ethernet fabric connections that power next-generation GPU clusters and disaggregated computing architectures. In this role, you'll be the technical expert customers rely on to successfully deploy Taurus Ethernet solutions in their most demanding environments. You'll work hands-on with hyperscalers, OEMs, and AI system builders to debug complex physical layer challenges, deliver technical enablement, and ensure seamless product integration. Your customer insights will directly influence how we evolve our products to meet the market's most pressing connectivity needs. This is a unique opportunity to combine deep Ethernet and physical layer expertise with meaningful customer impact at a hyper-growth --- TITLE: Senior Firmware Engineer - PCIe/CXL Memory Solutions EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $147K-$230K POSTED: 2026-05-09 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4692812005 EXCERPT: Senior Firmware Engineer - PCIe/CXL Memory Solutions San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking experienced Senior Firmware Engineer PCIe/CXL Memory Solution to lead the design and development of embedded firmware for cutting-edge PCIe/CXL memory expansion products tailored for AI and Cloud infrastructure. This role is pivotal in enabling next-generation memory devices that power high-performance computing platforms. This position will be required onsite. Required Experience: - Bachelor's degree in Electrical Engineering, Computer Science, or a related technical field. - 5+ years of hands-on experience in embedded firmware development using C. - Deep expertise in low-level firmware for hardware bring-up, traffic enablement, and RAS (Reliability, Availability, Serviceability) feature implementation. - Proven track record working with high-speed interfaces and protocols such as PCIe, CXL, DDR, and I2C. - Hands on experience in CPU to Device, Device to Device flows like MMIO, DMA, PCIe P2P. Key Responsibilities & Skills: - Firmware development, bring-up, and validation of PCIe/CXL/DDR interfaces at --- TITLE: Principal Digital Design Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $185K-$230K POSTED: 2026-03-12 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4672627005 EXCERPT: Principal Digital Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Join Astera Labs as a Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers. Key Responsibilities - Design Ownership & Execution - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design --- TITLE: Principal Product Application Engineer - PCIe EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $170K-$220K POSTED: 2026-05-20 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697866005 EXCERPT: Principal Product Application Engineer - PCIe San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Principal Product Applications Engineer to join our Aries PCIe Retimer team and serve as a critical technical bridge between our customers and engineering organization. As AI infrastructure demands explode, our Aries Smart Retimers are enabling the high-speed, low-latency PCIe connectivity that powers the world's most advanced data centers-and you'll be at the center of that growth. In this high-impact role, you'll work directly with hyperscalers, OEMs, and system builders to drive successful adoption of our Aries PCIe products. You'll combine deep technical expertise with customer-facing skills to solve complex system-level challenges, create compelling technical documentation, and influence product direction based on real-world customer needs. This is an opportunity to shape how next-generation AI and cloud infrastructure connects and scales. You'll collaborate cross-functionally with design engineering, validation, sales, and marketing teams while building strong relationships with customers who are defining --- TITLE: Senior Digital Design Engineer, IP and Methodology EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $135K-$195K POSTED: 2026-04-21 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4687603005 EXCERPT: Senior Digital Design Engineer, IP and Methodology San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Join Astera Labs as a Senior Digital Design Engineer to drive the design and implementation of next-generation digital designs for high-performance AI connectivity solutions. In this role, you'll focus on CPU subsystem development and security architecture, working on complex blocks from micro-architecture through silicon bring-up. You'll collaborate closely with verification, physical design, and DFT teams to deliver industry-leading products that power the world's most advanced data centers. This is an opportunity to shape the security and compute foundations of connectivity solutions enabling rack-scale AI infrastructure at hyperscale. Key Responsibilities - RTL Design & Implementation - Own the RTL implementation of complex digital designs from micro-architecture through sign-off - Design and implement CPU subsystems and embedded processor interfaces - Develop security-focused digital blocks including secure boot, cryptographic engines, and trusted execution environments - Verification & Quality - Collaborate with verification teams to review test plans and --- TITLE: Senior Principal Engineering Program Manager EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $205K-$250K POSTED: 2026-04-22 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4687560005 EXCERPT: Senior Principal Engineering Program Manager San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is looking for a Senior Principal Engineering Program Manager to lead end-to-end execution of advanced-node ASIC products from concept through production. This is a high-visibility role with direct accountability for delivering revenue-critical silicon on time, on spec, and at scale. Key Responsibilities - Program Ownership & Execution - Own full ASIC lifecycle execution: architecture, RTL, verification, physical design, tapeout, validation, customer sampling, qualification, and RTM - Serve as the single point of ownership for assigned ASIC programs - Drive program planning, schedules, budgets, resources, and risk management - Cross-Functional Leadership & Issue Resolution - Lead cross-functional teams across design, validation, product, test, firmware, software, and operations - Resolve complex pre-silicon and post-silicon issues through strong technical judgment - Stakeholder Management & Alignment - Manage scope, schedule, and cost trade-offs and communicate clearly with executives and stakeholders - Champion program execution while aligning engineering --- TITLE: Technical Lead Digital Design Engineer EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $160K-$195K POSTED: 2026-03-12 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4672633005 EXCERPT: Technical Lead Digital Design Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Join Astera Labs as a Technical Lead Digital Design Engineer to architect and implement next-generation digital designs for high-performance AI connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. This role offers the opportunity to work on cutting-edge technology at the forefront of AI infrastructure, taking ownership of critical design challenges in a fast-paced, collaborative environment where your contributions directly impact products deployed by the world's leading hyperscalers. Key Responsibilities - Design Ownership & Execution - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving RTL implementation with an exceptional power, performance and area trade-off using silicon technologies better than 7nm. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT) --- TITLE: Manager, Physical Design Engineer EMPLOYER: Astera Labs LOCATION: Toronto, Ontario, Canada (unspecified) SALARY: CAD 180K-220K POSTED: 2026-05-08 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4693903005 EXCERPT: Manager, Physical Design Engineer Toronto, Ontario, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Physical Design Engineering Manager to lead a team of physical design engineers at our Toronto site, driving the implementation of connectivity ASICs within our Signal Connectivity Group. This group is responsible for products that enable high-speed serial connectivity including PCIe retimers, Ethernet retimers, and signal conditioning solutions deployed across the world's largest AI clusters and hyperscale data centers. As an Physical Design Manager Engineering Manager, you will combine hands-on technical leadership with people management, owning physical design execution from RTL to GDSII while building and mentoring a high-performing team. You will drive floorplanning, place-and-route, timing closure, and sign-off for complex designs requiring deep understanding of high-speed physical layer interfaces and SerDes integration at TSMC advanced nodes. This role is fully on-site at our Toronto location . Basic Qualifications - Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field; Master's preferred. - --- TITLE: Senior Principal Technologist – Memory EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $205K-$255K POSTED: 2026-05-18 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4696478005 EXCERPT: Senior Principal Technologist – Memory San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Are you passionate about pushing the boundaries of system, memory, software, and chip architecture? Do you thrive when pitching cutting-edge technology solutions to customers and industry partners? We are seeking a creative customer facing Technologist to help facilitate Astera's development of data center memory solutions. In this role, you will play a pivotal role in driving the architecture and definition of future products by leveraging your expertise in system architecture, SOC memory sub-system architecture, PCIe/CXL technologies, DRAM/memory architecture, and hardware-software co-design. You will have the opportunity to directly engage with customers, influence product features and roadmap, and help drive innovation to better solve our customers' bottlenecks in hyperscale data centers. This role is fully in person, in San Jose. Some travel may be required. Basic qualifications - BS in Electrical or computer engineering, MS or PhD preferred. - ≥10 year's experience developing memory-related solutions and --- TITLE: Principal Package Signal & Power Integrity EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $203K-$230K POSTED: 2026-02-28 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4667442005 EXCERPT: Principal Package Signal & Power Integrity San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As a Principal Package Signal & Power Integrity Engineer at Astera Labs, you will serve as a senior technical leader responsible for architecting, optimizing, and signing off package SIPI solutions for next-generation connectivity products. You will drive package electrical architecture across high-performance IC packaging platforms, including FCBGA, coreless substrates, chiplet-based packages, 2.5D/3D integration, silicon interposers, bridge-based interconnect, and heterogeneous multi-die systems. In this role, you will lead SIPI strategy and execution for products supporting PCIe, CXL, Ethernet, 200G/400G+ SerDes, and die-to-die interconnect. You will partner closely with silicon architecture, SerDes/IP teams, package design, PCB design, hardware validation, manufacturing, substrate vendors, and OSAT partners to optimize signal integrity, power delivery, substrate/interposer routing, bump planning, and system-level electrical performance while balancing cost, manufacturability, reliability, yield, and schedule. You will also drive SIPI methodology, modeling standards, simulation-to-measurement correlation, and chip-package-board co-design frameworks to enable scalable execution across --- TITLE: Senior Principal Validation Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $255K-$255K POSTED: 2026-01-22 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4646293005 EXCERPT: Senior Principal Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: As a Senior Principal Validation Engineer , you will join a cutting-edge mixed-signal design team and lead the end-to-end post‑silicon validation and characterization effort. You will own the development and execution of comprehensive validation plans, design and implement test methodologies, and drive hands‑on lab work to verify silicon against specification and performance targets. You will collaborate closely with design, firmware, and system teams to translate architectural goals into measurable test strategies, build automated test frameworks, and analyze complex analog and digital interactions. Your work will include defining test requirements, creating characterization flows, debugging silicon anomalies, and delivering clear, data‑driven recommendations that influence product direction. This role requires deep technical expertise in mixed‑signal systems, strong problem‑solving skills, and the ability to mentor engineers across disciplines. You will be expected to champion best practices for validation, optimize test coverage and throughput, and ensure that products meet reliability, yield, and performance objectives --- TITLE: Principal Emulation Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $209K-$230K POSTED: 2025-09-09 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4600077005 EXCERPT: Principal Emulation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Principal Emulation Engineer with hands-on experience verifying protocols on complex ASICs and experience with or interest in emulation. The ideal candidate would be at ease creating environments to enable verification teams to stress test ASICs, as well as debugging design, environment, transactor, and code issues. The candidate must have good knowledge of communication protocols such as PCI-Express (Gen-3 and above), DDR, Ethernet, NVMe, or similar interfaces. Basic qualifications: - Strong academic and technical background in computer/electrical engineering. At a minimum, a Bachelor's in EE or Computer Science is required, and a Master's is preferred. - ≥8 years' experience supporting or developing complex SoC/silicon products for Server, Storage or Networking applications. - Experience working with logic designers to architect, specify, and verify hardware-software interfaces on complex SoCs. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks and to work with minimal guidance --- TITLE: Principal Integrated Circuit Designer EMPLOYER: Astera Labs LOCATION: Singapore (unspecified) SALARY: Not disclosed POSTED: 2025-01-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4515946005 EXCERPT: Principal Integrated Circuit Designer Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Integrated Circuit Designer, you will be part of a key team designing sophisticated advanced node CMOS products. Key Job Duties: - The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets]. - The management of manufacturing process of the products, including technology yield and performance of the products. - The development of test programmes and procedures to ensure the products meet their performance specifications. This will include [working on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB]. - The provision of advice on aspects of semiconductor process technology and maintain and repair semiconductor process equipment. Basic Qualifications - Strong academic and technical background in electrical engineering. A Master's or --- TITLE: Technical Lead Design Verification Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $147K-$195K POSTED: 2026-05-28 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697334005 EXCERPT: Technical Lead Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Technical Lead Design Verification Engineers with a flair for being a code breaker, ability to come up hybrid mechanisms for verification of complex ASICs. Experience with System Verilog, C, C++, Python or other scripting languages would be a plus. Using your coding and problem-solving skills, you will contribute to the functional verification of the designs. You'll be responsible for the full life cycle of verification, from planning to writing tests to debugging, collect and closing coverage. You'll also work with the software and system validation teams to come up with test plans and executing them in emulation platforms. Basic qualifications - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Masters is preferred. - ≥5 years' experience verifying and validating complex SoC for Server, Storage, and Networking applications. - Knowledge of industry-standard simulators, revision control --- TITLE: Senior Engineer, Analog Mixed Signal Layout EMPLOYER: Astera Labs LOCATION: Ho Chi Minh City, Vietnam (unspecified) SALARY: Not disclosed POSTED: 2026-03-31 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4678683005 EXCERPT: Senior Engineer, Analog Mixed Signal Layout Ho Chi Minh City, Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . The company seeks a highly motivated and team-oriented individual to work with both layout and design engineers across multiple time zones As an Integrated Circuit Designer - Layout, you will be part of a key team designing and developing sophisticated advanced node CMOS products. Key Job Duties: - The design and development of the layout for integrated circuits according to electronics engineering principles, using software to create design schematics and diagrams. This will include [floor planning, creating layouts of building blocks and integrating layouts for circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs in advanced CMOS nodes. Your focus will include minimizing parasitic and skew, matching, EMIR, and antenna rules on top of DRC and LVS] - The management of manufacturing process of the products, including technology yield and performance of the products. - The development of test programmes and procedures to --- TITLE: Principal Test Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $209K-$230K POSTED: 2025-12-19 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4637712005 EXCERPT: Principal Test Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Principal Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, Infiniband, DDR, NVMe, USB, etc. Basic Qualifications - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred. - ≥8-year experience releasing complex SoC/silicon products to high volume manufacturing. - Working knowledge of high-speed protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc. - Professional attitude with ability to execute on multiple tasks with minimal supervision. - Strong team player with good communication skills to --- TITLE: Analog/Mixed-Signal IC Design EMPLOYER: Astera Labs LOCATION: India (unspecified) SALARY: Not disclosed POSTED: 2026-03-12 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4672401005 EXCERPT: Analog/Mixed-Signal IC Design India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who thrives in a collaborative environment. --- TITLE: Principal Power and Board Design Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $209K-$230K POSTED: 2025-08-05 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4592489005 EXCERPT: Principal Power and Board Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Power and Board Design Engineer Overview: We are seeking a highly skilled and experienced Power and Board Design Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions. Key Responsibilities: - Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules. - Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance mismatches. - Develop and implement board-level designs, to meet electrical and mechanical requirements with a deep understanding of PCB layout rules and constraints. - Implement thermal solutions to maintain optimal operating temperatures for --- TITLE: Production Planner, Senior EMPLOYER: Astera Labs LOCATION: Aachen, North Rhine-Westphalia, Germany (unspecified) SALARY: Not disclosed POSTED: 2026-05-21 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697687005 EXCERPT: Production Planner, Senior Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Senior Production Planning is responsible for the efficient planning, control and preparation of the manufacturing processes as well as the availability of the necessary production material in the sense of on-time and economical production. Responsibilities and tasks Area of responsibility Job Description Production and work planning - Planning, control and monitoring of production orders, taking into account deadlines, capacities and resources - Detailed and rough planning of production capacities (machines, personnel, materials) - Coordination of appointments with sales, purchasing, logistics and production Documentation and master data maintenance - Creation and maintenance of work plans, parts lists and production documents - Support in the introduction and further development of ERP/PPS systems Material planning and logistics - Ensuring material availability in coordination with purchasing and sales on the basis of the quantity forecast. - Implementation of risk-based material requirements planning and adapted supplier strategy. - Participation in supplier selection and management as --- TITLE: Senior SoC Verification/Validation Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $165K-$195K POSTED: 2025-08-20 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4588342005 EXCERPT: Senior SoC Verification/Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Senior SoC Verification/Validation Engineer who are passionate about bringing next-generation SoCs to life on industry-leading emulation platforms. You will play a critical role in validating complex SoCs for AI connectivity and cloud infrastructure, ensuring functionality and performance well before silicon tape-out. Basic Responsibilities - Play a key role in developing complex SOCs for AI connectivity and cloud infrastructures - Bring up and validate high-speed serial interfaces such as PCIe, Ethernet and UALink, and overall SoC functionality - Collaborate closely with Architecture, Design, Verification, and SW/FW teams to define and execute functional/performance validation plans - Develop C/C++ FW and tests to validate and execute all test plan items - Build tools and methodologies to validate and debug all HW and SW/FW issues on the emulation platform Required Qualification - BS/MS in Electrical Engineering, Computer Engineering or related field. - 5+ years of hands-on experience in --- TITLE: FP&A Business Unit Controller EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $150K-$200K POSTED: 2026-04-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4691421005 EXCERPT: FP&A Business Unit Controller San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview As a FP&A Business Unit Controller you will be primarily responsible for managing the business partnering relationships for the R&D business units including their annual budgets and quarterly forecast updates and actual performance. The ideal candidate has a strong understanding of financial processes and complex transaction flows with a desire to grow and contribute in a high-growth, fast-paced environment. This role must communicate and organize tasks well to be effective. Primary Responsibilities - Establish strong partnership with leadership to help business owners manage their business effectively - Lead all forecasting and analysis activities for the business owners including: annual plan, quarterly forecast updates and strategic planning - Develop, analyze, and interpret financial data to evaluate operating results against budget and profitability metrics - Provide analytical insights, assess risks, and guide senior leadership in strategic decision-making - Collaborate with Corporate Finance on various projects as needed - Provide --- TITLE: Production Director EMPLOYER: Astera Labs LOCATION: Aachen, North Rhine-Westphalia, Germany (unspecified) SALARY: Not disclosed POSTED: 2026-05-21 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697682005 EXCERPT: Production Director Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . AsteraLabs Germany GmbH, located in Aachen, is part of the connectivity group and specialized in the design and production of highly scalable fiber-to-the-chip connector solutions, based on micro-optical components. As head of the entire production department, the Director Production is responsible for the overarching definition and control of all production processes for the micro-optical connector units as well as the management of the entire production team with the aim of safe, on-time, quality- and cost-efficient series production. Location: On-Site - Aachen, North Rhine-Westphalia, Germany. Area of responsibility Job Description Operational production control - Ensuring a smooth production process in compliance with labor regulations as well as relevant quality, safety and environmental standards. - Ensuring the relevant documentation of work results, deviations and corrective actions. - Determination and analysis of relevant production key figures as well as initiation and monitoring of relevant control measures. Organization and resource planning - Operational production planning --- TITLE: Principal Mixed Signal Design Verification Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: Not disclosed POSTED: 2026-03-03 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4668457005 EXCERPT: Principal Mixed Signal Design Verification Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Principal Design Verification Engineers with proven experience in all aspects of verification in UVM and C/C++. The candidate must have experience using high level programming languages such as C/C++ to communicate with System Verilog and/or UVM based environments to aid RTL simulation, CoSimulation and Emulation. Basic qualifications: - Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Maser's is preferred. - ≥8 years' experience supporting or developing complex high-speed SerDes/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, to plan and prepare for customer meetings in advance, and to work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind! - Authorized to work in US and start immediately. --- TITLE: Analog / Mixed-Signal Layout Engineer EMPLOYER: Astera Labs LOCATION: Singapore, Singapore (unspecified) SALARY: Not disclosed POSTED: 2026-05-12 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4666729005 EXCERPT: Analog / Mixed-Signal Layout Engineer Singapore, Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Analog / Mixed-Signal Layout Engineer to join our ASIC team working on the forefront of high-performance compute and networking standards in advanced CMOS process nodes. The ideal candidate will have an impeccable hardware engineering background with an emphasis on VLSI and/or computer architecture. We are looking for experience in design, verification, and validation of real-world systems. Exposure to high-speed interfaces PCIE, DDR, HBM, Serdes technologies would be great to have. Above all, curiosity and ability to learn is a must. In this position you will be responsible for design and/or verification of blocks using leading edge methodology and tools. Basic qualifications: - Pursuing BS or MS in EE/CS or related fields. - Hardware engineering background with an emphasis in VLSI or Computer Architecture. - Exposure to Digital design or verification, VLSI design and circuits, Computer Architecture. Required experience : - Hands-on and knowledge of RTL --- TITLE: Lead ATE Test Engineer EMPLOYER: Astera Labs LOCATION: Taipei, Taiwan (unspecified) SALARY: Not disclosed POSTED: 2026-03-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4677747005 EXCERPT: Lead ATE Test Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for Lead ATE Test Engineers with proven experience in developing and supporting complex mixed-signal silicon SoC products to lead ATE Test solutions. The ideal candidate will develop and oversee SoC test strategy, interact with manufacturing partners, define, and implement ATE programs and own the product from design, initial samples all the way through high volume production ramp. The candidate should have working knowledge of communication/interface protocols such as PCI-Express (Gen-4/5/6), Ethernet, DDR, NVMe, USB, etc. Basic Qualifications · Strong academic and technical background in electrical engineering. At minimum, a Bachelor's in EE is required, and a Master's is preferred. · ≥5-year experience releasing complex SoC/silicon products to high volume manufacturing. · Working knowledge of high-speed protocols like PCIe, Ethernet, DDR, NVMe, USB, etc. · Professional attitude with ability to execute on multiple tasks with minimal supervision. · Strong team player with good communication skills to work --- TITLE: Director, Digital Compute & Power Optimization EMPLOYER: Astera Labs LOCATION: Toronto, Ontario, Canada (unspecified) SALARY: CAD 200K-250K POSTED: 2026-05-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4695156005 EXCERPT: Director, Digital Compute & Power Optimization Toronto, Ontario, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are looking for a hands-on Digital Design Engineering Manager to drive high-speed connectivity solutions. You will build and lead a team responsible for delivering the micro-architecture and implementation of front-end digital design, including RTL development, synthesis, IP integration, and block-level verification for high-performance ASICs. The ideal candidate should have strong experience with low-power design techniques and a solid understanding of SerDes DSP design, including equalizer optimization for power and area efficiency. The candidate must also have a good knowledge of communication and interface protocols such as CXL/PCIe (Gen 3 and above), Ethernet, or DDR. Basic qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE is required, and a Master's degree is preferred. - 10+ years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - 5+ years' experience managing a team of RTL design engineers. --- TITLE: Technical Chief of Staff for ASIC Engineering EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $216K-$300K POSTED: 2025-11-20 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4632063005 EXCERPT: Technical Chief of Staff for ASIC Engineering San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Summary We are seeking a technically strong Chief of Staff to the Head of Engineering who will also lead Engineering Program Management across Silicon Engineering. This role is a force-multiplier for Engineering leadership - driving org scale, decision velocity, and execution rigor. The ideal candidate brings deep technical fluency, structured problem-solving, and the ability to drive outcomes through influence rather than hierarchy. The role is fully in person in San Jose. Responsibilities - What You Will Own 1) Chief of Staff to Head of Engineering • Drive operational cadence: engineering all hands, staff meetings, agenda/material prep, tech talks, university engagements, action follow-through, and leadership syncs. • Frame and resolve high-leverage decisions - proactively surface blockers (technical, operational, organizational) before they escalate. • Manage escalations and organizational friction - diagnose root causes, coordinate resolution paths, and ensure durable fixes. • Partner cross-functionally with Hardware, Product, and Quality --- TITLE: Technical Lead Product Engineer EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: $195K-$195K POSTED: 2026-04-01 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4680695005 EXCERPT: Technical Lead Product Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: We are seeking an experienced and hands-on Technical Lead Product Engineer to lead and develop next generation high-speed, high performance and low power semiconductor products in advanced process node. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives. Basic Qualifications: - Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation) - Experience in working with PCIe Gen3 and above - Have gone through at least one cycle of full product development life cycle - Strong academic/technical background in electrical or computer engineering; Bachelor's is required; MS preferred - Strong problem-solving skills that involve system level --- TITLE: Senior Analog Mixed-Signal CAD Engineer EMPLOYER: Astera Labs LOCATION: Vietnam (unspecified) SALARY: Not disclosed POSTED: 2026-01-27 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4654351005 EXCERPT: Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring --- TITLE: Sr. Principal DSP Architect (Optical Transceivers & PAM4) EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $210K-$260K POSTED: 2026-01-26 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4652764005 EXCERPT: Sr. Principal DSP Architect (Optical Transceivers & PAM4) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview As a Sr. Principal DSP Architect, you will be the technical visionary leading the definition and development of next-generation Digital Signal Processing (DSP) architectures. Your focus will be on high-speed PAM4 (Pulse Amplitude Modulation 4-level) systems and coherent/direct-detect optical transceivers. You will bridge the gap between theoretical communications theory and silicon implementation, driving the roadmap for 800G, 1.6T, and beyond. Key Responsibilities - Architectural Leadership: Lead the definition of DSP micro-architecture for high-performance ASICs, focusing on low-power, high-throughput data paths. - Algorithm Development: Design, model, and simulate advanced DSP algorithms for: - Adaptive Equalization (FFE, DFE, MLSE). - Forward Error Correction (FEC). - Clock and Data Recovery (CDR). - Chromatic Dispersion (CD) and Polarization Mode Dispersion (PMD) compensation. - Modeling & Simulation: Develop bit-accurate and performance-accurate models using Python, MATLAB, or C++ to validate architectural choices against Bit Error Rate (BER) targets. - Cross-Functional --- TITLE: Principal Analog Mixed-Signal Design Engineer EMPLOYER: Astera Labs LOCATION: Toronto , Canada (unspecified) SALARY: Not disclosed POSTED: 2026-01-20 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4610204005 EXCERPT: Principal Analog Mixed-Signal Design Engineer Toronto , Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Analog/Mixed-Signal IC Design Engineer, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: - Strong academic and technical background in electrical engineering. A Master's or PhD degree in EE is required, preferably from a top-tier university. - 8+ years of experience supporting or developing complex analog IC designs. Required Experience: - Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must - Have a deep understanding --- TITLE: Senior Analog Mixed Signal Design Engineer EMPLOYER: Astera Labs LOCATION: Vietnam (unspecified) SALARY: Not disclosed POSTED: 2026-03-10 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4671754005 EXCERPT: Senior Analog Mixed Signal Design Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking an experienced Analog/Mixed-Signal (AMS) Circuit Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5/3nm technology node. In this role, you will design high-speed analog and mixed-signal circuits used in multi-gigabit transceivers, collaborating with layout, verification, and system teams to ensure robust performance, power efficiency, and successful silicon validation at advanced process nodes. Key Responsibilities - Design critical AMS blocks such as PLLs, CDRs, LDOs, bias generators, and ADC/DAC components for wireline transceivers. - Perform transistor-level design, simulation, and optimization for performance, power, and area across process, voltage, and temperature (PVT) corners. - Work closely with layout engineers to guide floorplanning, matching-sensitive layout, and parasitic-aware design. • Perform design verification using pre- and post-layout simulations (transient, AC, noise, Monte Carlo, corner sweep). - Ensure robust operation under variation, jitter, power supply noise, and crosstalk conditions. - Create and maintain design --- TITLE: Senior Physical Design Engineer EMPLOYER: Astera Labs LOCATION: Singapore (unspecified) SALARY: Not disclosed POSTED: 2026-02-10 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4660309005 EXCERPT: Senior Physical Design Engineer Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role We are seeking a Senior Physical Design Engineer to join our high-performance design team working on next-generation transceiver IPs targeting the TSMC 5nm, 3nm technology node. In this role, you will take ownership of physical implementation from RTL to GDSII, ensure timing and power closure for ultra-high-speed designs, and collaborate closely with cross-functional teams to resolve challenges unique to advanced nodes and multi-gigabit transceiver architectures. Key Responsibilities - Perform full-chip and block-level physical implementation including floor planning, placement, clock tree synthesis (CTS), routing, and physical verification for high-speed designs in TSMC 3nm. - Collaborate with RTL and STA teams to ensure clean handoffs and convergent timing, area, and power. - Work on advanced physical design techniques to support multiple voltage/frequency domains, hierarchical design, and physical-aware synthesis. - Handle advanced physical design topics: - EM/IR analysis and power grid optimization - Congestion analysis and mitigation - Clock domain crossing and --- TITLE: Principal Digital Design Engineer (AI Fabric) EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $185K-$230K POSTED: 2025-12-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4645005005 EXCERPT: Principal Digital Design Engineer (AI Fabric) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Principal Digital Design Engineer to architect and implement next-generation digital designs for high-performance connectivity solutions. You'll own complex blocks from micro-architecture through silicon bring-up, driving RTL implementation and collaborating with verification, PD and DFT teams to deliver high performance products in a fast-paced, collaborative environment. Key Responsibilities - Develop and implement complex digital blocks and subsystems by defining micro-architecture and driving digital design. - Collaborate with verification teams to develop test plans, achieve coverage closure, and debug complex issues. - Lead efforts to achieve timing closure and implement Design-for-Test (DFT) features for optimal design performance. - Work closely with post-silicon teams to facilitate silicon bring-up and debug. - Mentor junior engineers to develop their technical skills and expertise. - Actively contribute to the development and improvement of silicon development processes. - Drive designs to production, ensuring accountability for quality, schedule, and overall design --- TITLE: Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026) EMPLOYER: Astera Labs LOCATION: Irvine, CA or San Jose, CA (unspecified) SALARY: $55-$65/hr POSTED: 2025-09-04 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4605619005 EXCERPT: Analog/Mixed-Signal Engineer - SerDes (PhD Intern 2026) Irvine, CA or San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Analog/Mixed-Signal IC Design Engineer Intern, you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: - Pursuing a Master's or PhD degree in EE is preferred Desired Experience: - Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must - Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits - Solid track-record for implementation of analog --- TITLE: Senior Foundry Engineer, Silicon Technology EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-04 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4700342005 EXCERPT: Senior Foundry Engineer, Silicon Technology San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description We are seeking a Senior Foundry Engineer, Silicon Technology to support foundry engagement, silicon-to-model correlation, tapeout readiness, and yield improvement for advanced semiconductor products. This person will work closely with internal design, CAD layout, product engineering, test, reliability, operations teams and external foundry partners to identify risks, assess product impact, and drive timely resolution of process, PDK, model, DRC/DFM, and silicon-related issues. Responsibilities Include - Silicon, process and yield correlation - Analyze process inline data, silicon test data, process drift and process correlation data - Fine tune processes to optimize power, performance and yield - Help identify process related contributors to parametric drift, yield loss, leakage, reliability risk - Work with foundry and internal teams to investigate yield issues and process excursions - Perform layout analysis where needed to understand process sensitivity, failures - Tapeout and DFM support - Support product tapeouts, tapeout readiness reviews --- TITLE: Optical Test Engineering, Senior Director EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-05 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4696245005 EXCERPT: Optical Test Engineering, Senior Director San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Senior Director, Optical Test Engineering Position Overview We are seeking an experienced Senior Director of Optical Test Engineering to lead the development, validation, and manufacturing support of advanced integrated optical interconnect solutions. This role focuses on optical-electrical integration at the module level, bridging transceiver and compute platform interfaces with comprehensive test strategy and execution. Key Responsibilities Strategic Leadership - Define and execute the optical test engineering roadmap for next-generation interconnect architectures - Establish testing methodologies and standards for tightly integrated optical-electrical assemblies - Lead cross-functional teams across optical design, electrical engineering, manufacturing, and quality - Develop partnerships with ecosystem partners on test protocols and validation requirements Technical Program Management - Oversee test strategy development for optical modules with embedded or adjacently mounted optical components - Drive creation of comprehensive test plans covering optical performance, electrical performance, thermal management, and reliability - Establish acceptance criteria and performance benchmarks --- TITLE: Optical Firmware Engineer, Principal EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-05-15 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4693807005 EXCERPT: Optical Firmware Engineer, Principal San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking to hire an Optical Firmware Engineer, Principal develop, optimize, and maintain embedded firmware for optical engines, photonic integrated circuits (PICs) optical modules. This includes control of lasers, modulators, photodetectors, thermal management, calibration, and high-speed link optimization in silicon photonics systems. The role sits at the intersection of embedded systems, photonics, and hardware. Key Responsibilities: - Design, develop, and debug real-time firmware for optical transceivers or PIC/EIC engines (e.g., in C/C++ for microcontrollers or embedded processors). - Implement algorithms for laser control, automatic power control (APC), temperature compensation, wavelength locking, and link training/adaptation. - Integrate firmware with hardware (DSP, drivers, ADCs/DACs) and higher-level software (e.g., via I2C, SPI, or custom interfaces). - Develop diagnostic, calibration, and telemetry features for manufacturing test, field monitoring, and reliability. - Optimize for low latency, power efficiency, and high reliability in high-speed (400G/800G/1.6T+) optical links. - Collaborate with optical, electrical, DSP, --- TITLE: Photonic Packaging Engineer, Principal EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-05-19 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4696246005 EXCERPT: Photonic Packaging Engineer, Principal San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking a visionary and technically strong Photonic Packaging Engineer, Principal to lead the design, development, and productization of advanced packaging solutions for advanced optics. This role will drive the intersection of photonics, high-speed electronics, thermal management, and mechanical integration to enable next-generation data center and networking platforms. You will guide a multidisciplinary team through all phases of product realization-from concept and design through manufacturing scale-up-working closely with silicon photonics, electrical packaging, systems, and supply chain teams to achieve world-class optical and electrical performance. Key Responsibilities - Lead the end-to-end development of photonic packaging strategies for Silicon Photonics Modules, including EIC/PIC co-packaging, optical coupling, fiber attach, and thermal and mechanical design. - Define technical requirements and package architectures that balance performance, manufacturability, and cost with compatibility with established electronic packaging flows. - Collaborate with IC packaging, optical connector, and silicon photonics teams to achieve co-design optimization - --- TITLE: Senior Digital Design Engineer (AI Fabric) EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $160K-$195K POSTED: 2025-12-30 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4644970005 EXCERPT: Senior Digital Design Engineer (AI Fabric) San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Join our team as Senior Digital Design Engineer to contribute to the design and implementation of next-generation digital designs for high-performance connectivity solutions. You'll work on complex blocks from micro-architecture through silicon bring-up, collaborating with verification, PD, and DFT teams to deliver high-performance products in a fast-paced, collaborative environment. Key Responsibilities - Own the RTL implementation of complex digital designs from micro-architecture through sign-off. - Collaborate with verification teams to review test plans and debug issues. - Support efforts to achieve timing closure and implement Design-for-Test (DFT) features. - Scripting and automation for ASIC methodology improvement. - Accountable for quality and overall design success with the support of senior engineers. Required Qualifications Education & Experience: - Bachelor's degree in electrical engineering or equivalent - 3-8 years of experience developing SoC/silicon products in Server, Storage, and/or Networking markets Digital Design Expertise: - Expertise in RTL coding with SystemVerilog --- TITLE: Technical Lead Power Engineer EMPLOYER: Astera Labs LOCATION: San Jose, CA (unspecified) SALARY: $170K-$195K POSTED: 2025-12-29 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4641495005 EXCERPT: Technical Lead Power Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: We are seeking a highly skilled and experienced Technical Lead Power Engineer to join our team. In this role, you will be responsible for designing and optimizing power delivery systems for our ASIC products, ensuring robust power integrity, and developing board-level designs. Your expertise will be crucial in selecting power components, collaborating with vendors, and utilizing industry-leading tools to deliver high-performance solutions. Key Responsibilities: - Develop and optimize power conversion circuits, including DC-DC converters, voltage regulators, and power modules. - Design high-efficiency, high-reliability power circuits including: - Buck / boost / buck-boost converters - Multiphase regulators - Hot-swap, protection, and sequencing circuits - Design and optimize power delivery for ASICs, ensuring stable voltage and current distribution across the board. Address power integrity challenges such as voltage ripple, noise, and impedance of mismatches. - Perform power integrity, transient response, stability, and thermal analysis. - Evaluate and select appropriate power components, --- TITLE: Analog/Mixed-Signal Engineer - SerDes EMPLOYER: Astera Labs LOCATION: Singapore, Singapore (unspecified) SALARY: Not disclosed POSTED: 2026-05-05 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4619972005 EXCERPT: Analog/Mixed-Signal Engineer - SerDes Singapore, Singapore Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Analog/Mixed-Signal IC Design Engineer , you will be part of a key team designing sophisticated advanced node CMOS products. Your responsibilities will include developing and verifying circuits such as PLL, DLL, ADC, regulators, amplifiers, TX, RX, and CDRs to meet performance targets. You will also work on analog and clocking blocks for connectivity applications, using industry-standard tools like Spectre and MATLAB. The company seeks a highly motivated designer for this role Basic Qualifications: - Pursuing a Master's or PhD degree in EE is preferred Desired Experience: - Hands-on experience in designing high-speed mixed-signal circuits including ADC/DAC data converters, RX front-end, TX driver/serializer, low-jitter PLLs, TX/RX calibration, low-jitter CLK distribution are other high-speed analog circuits is a must - Have a deep understanding of biasing, band-gaps, reference circuits, opamps, comparators and other analog circuits - Solid track-record for implementation of analog circuits high-speed data transmission. - Design and --- TITLE: Principal Engineer, Analog Mixed-Signal IC Layout EMPLOYER: Astera Labs LOCATION: Bengaluru, Karnataka, India (unspecified) SALARY: Not disclosed POSTED: 2026-03-10 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4663818005 EXCERPT: Principal Engineer, Analog Mixed-Signal IC Layout Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview: As an Analog Mixed-Signal IC Layout Lead Engineer, you will play a critical role in designing advanced node Bi-CMOS / CMOS products. You will be responsible for managing chip top-level layout and integration along with block level layout design and ensuring successful tapeout. You will work to build state-of-the art high speed circuits minimizing layout parasitics, while applying techniques to reduce skew and crosstalk. Meeting EM/IR compliance requirements is essential. You will ensure strict adherence to DRC, LVS, ANT, and density rules. Additionally, awareness of ESD and latch-up design practices is expected to ensure robust and reliable layout implementations. You will apply a solid foundation in device physics, along with demonstrating a strong three-dimensional understanding of device layout. You will collaborate with a dynamic, cross-functional team of analog designers and layout engineers across multiple time zones. We are looking for a highly motivated, team-oriented individual who --- TITLE: Principal Quality Engineer EMPLOYER: Astera Labs LOCATION: Aachen, North Rhine-Westphalia, Germany (unspecified) SALARY: Not disclosed POSTED: 2026-04-23 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4688304005 EXCERPT: Principal Quality Engineer Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Quality Engineer Role Summary As Principal Quality Engineer based in Aachen, you are the technical authority for quality across our optical product line and regional quality lead for European operations. You will bridge HQ (San Jose) and the Aachen manufacturing site, drive quality integration for in-house optical manufacturing, lead supplier quality for regional semiconductor and optical vendors, and support Asia-based RMA activities for in-region products. Key Responsibilities Quality ‑ System Integration: Lead ISO 9001 alignment between San Jose HQ, Aachen, and other regional locations to harmonize procedures, audit schedules, and corrective action processes across both semiconductor and optical product lines. Process Development & Implementation: Design, document, and roll out new quality processes, procedures, and work instructions needed to support emerging photonics products and manufacturing capabilities. In ‑ Process Inspection & Controls: Oversee in ‑ process inspection activities for the in ‑ house manufacturing operation, establishing SPC, go/no ‑ go --- TITLE: Active Electric Cable / Smart Cable Module Lead, AVP EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-03 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4702146005 EXCERPT: Active Electric Cable / Smart Cable Module Lead, AVP San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . AVP, AEC/SCM Lead We are seeking a highly experienced leader to drive high-speed product development and technology strategy across a portfolio of advanced interconnect solutions. This role is ideal for someone who combines deep technical expertise with strong cross-functional leadership, deep familiarity with cable manufacturing, and a track record of bringing complex products from concept through qualification and launch. Role Overview The AEC/SCM Lead will lead development across a range of high-speed electrical connectivity products, with primary focus on: - Active electrical cables (AEC) - Active copper cables (ACC) - Smart cable modules (SCM) - Linear re-driver cables This leader will own both technology roadmapping and execution, managing multidisciplinary teams spanning hardware, firmware, testing, and mechanical engineering. Key Responsibilities - Lead cross-functional engineering teams across Mechanical Engineering, Testing Engineering, Hardware Engineering, and Firmware Engineering. - Drive R&D and new product development for active --- TITLE: Finance and Administration Intern (Part-Time, Germany 2026) EMPLOYER: Astera Labs LOCATION: Aachen, North Rhine-Westphalia, Germany (unspecified) SALARY: Not disclosed POSTED: 2026-06-05 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4675837005 EXCERPT: Finance and Administration Intern (Part-Time, Germany 2026) Aachen, North Rhine-Westphalia, Germany Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Support the finance team across accounting, procurement, financial planning, and process improvement in an international environment. Key Responsibilities - Process invoices, create POs, and support vendor onboarding - Support OPEX planning and analyze production cost structures - Contribute to financial analysis and planning activities - Assist ERP migration and improve processes - Support automation initiatives (e.g., Power Automate, AI tools) Your Profile - Student in Finance, Accounting, Business, or similar - Strong analytical skills and attention to detail - Structured, reliable, and proactive way of working - Quick learner with ability to work independently - Good Excel skills; ERP/automation tools are a plus - Fluent in English and German We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, --- TITLE: Principal Electrical Engineer – Smart Cable Modules EMPLOYER: Astera Labs LOCATION: Shanghai Shi, China (unspecified) SALARY: Not disclosed POSTED: 2026-05-22 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4698851005 EXCERPT: Principal Electrical Engineer – Smart Cable Modules Shanghai Shi, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are looking for a Principal Electrical Engineer to take strategic ownership of our Smart Cable Module (SCM) hardware platform. This is a senior individual-contributor role that combines deep technical leadership with cross-organizational influence - you will define the electrical architecture of our next-generation active copper cable assemblies and pluggable modules in OSFP, QSFP-DD, and emerging form-factor enclosures targeting 400G, 800G, and beyond. As a Principal Engineer you will set design direction, establish engineering standards, and serve as the primary technical authority on module hardware across the full product lifecycle - from concept and architecture through production release and sustaining engineering. You will partner with cross functional team, contract manufacturers, firmware teams, and hyperscale customers to deliver differentiated, high-reliability products for data center AI/ML fabric and high-performance computing applications. Key Responsibilities Architecture & Technical Leadership - Define and own the end-to-end electrical architecture for smart cable modules, --- TITLE: Optical Validation Engineer, Tech Lead EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-05-28 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4693784005 EXCERPT: Optical Validation Engineer, Tech Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking an experienced Optical (EIC/PIC) Validation Engineer at the Senior to Principal level to lead the validation, characterization, and qualification of advanced photonic integrated circuits (PICs) closely integrated with electronic integrated circuits (EICs) multiple optical configurations. This high-impact role focuses on ensuring the performance, reliability, and manufacturability of next-generation optical engines for high-speed data center, AI/ML, and telecom applications. The ideal candidate has deep expertise in electro-optical testing, system-level validation, and multiple optical integration challenges. Key Responsibilities - Lead end-to-end validation and characterization of Optical Engines integrating EIC and PIC in multiple Silicon Photonic architectures. - Develop comprehensive test plans, methodologies, and automation frameworks for optical, electrical, and electro-optical performance metrics (e.g., BER, eye diagrams, insertion loss, extinction ratio, receiver sensitivity, transmitter power). - Perform detailed characterization of key building blocks: modulators, photodetectors, lasers, waveguides, couplers, and high-speed EIC/PIC interfaces. - Validate co-packaged optics performance --- TITLE: Principal AI Infrastructure & Hardware Program Management EMPLOYER: Astera Labs LOCATION: United States, Remote (remote) SALARY: Not disclosed POSTED: 2026-05-19 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4697312005 EXCERPT: Principal AI Infrastructure & Hardware Program Management United States, Remote Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role We are seeking a highly experienced and results-driven leader to drive our global AI, Storage, and Networking hardware design programs. This role will be responsible for end-to-end program leadership across complex, multi-disciplinary initiatives, ensuring successful delivery of cutting-edge products in a fast-paced, innovation-driven environment. You will work closely with executive leadership, Tier-1 customers, and cross-functional global teams to deliver next-generation infrastructure solutions, including advanced AI platforms. Key Responsibilities Program Leadership & Execution - Lead and manage global AI, Storage, and Networking hardware design programs, ensuring on-time delivery, scope control, and budget adherence - Drive program governance, risk management, and execution excellence across all phases of product development - Provide regular program updates, risk assessments, and financial reporting to executive leadership through structured reviews (e.g., Leadership Program Reviews) Product Innovation & Delivery - Oversee the successful launch of complex hardware platforms, including AI GPU-based systems --- TITLE: Optical Test Engineer, Tech Lead EMPLOYER: Astera Labs LOCATION: San Jose, California, United States (unspecified) SALARY: Not disclosed POSTED: 2026-05-19 APPLY_URL: https://job-boards.greenhouse.io/asteralabs/jobs/4696244005 EXCERPT: Optical Test Engineer, Tech Lead San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are seeking a world-class Senior Staff to Principal Optical Test Engineer to lead the development and execution of advanced test strategies for Co-Packaged Optics (CPO) solutions. This senior role drives optical and electro-optical testing for next-generation high-bandwidth CPO modules and optical engines integrated with ASICs for AI, hyperscale data centers, and high-performance computing. You will architect test methodologies, develop hardware/software platforms, and enable high-volume manufacturing while ensuring world-class performance, reliability, and yield. This is a high-impact technical leadership position at the forefront of silicon photonics and co-packaged optics innovation. Key Responsibilities - Lead the definition, development, and qualification of comprehensive test solutions for CPO optical engines, including wafer-level, die-level, package-level, and system-level testing. - Design and implement optical test hardware and automation systems (e.g., active alignment, fiber array attachment, high-speed optical I/O characterization). - Develop test programs and methodologies for key photonic parameters: insertion loss, eye --- TITLE: Product Marketing Manager EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-07 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/aaa9193c-cccd-49cb-bde1-44b830ebc900 EXCERPT: Product Marketing Manager Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. WHO WE'RE LOOKING FOR We're looking for a Product Marketing Manager who thrives on owning outcomes end-to-end and translating complex, technical products into clear stories that drive revenue. Freshpaint sits at the intersection of data, privacy, and performance, and our buyers need to quickly understand not just what we do, but why it matters and why we win. This is a highly cross-functional, high-ownership role on a lean team. --- TITLE: Senior Sales Engineer EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-07 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/20069cda-206d-453c-9483-e202ab16b709 EXCERPT: Senior Sales Engineer Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. WHO WE'RE LOOKING FOR We're looking for a Senior Sales Engineer who wants to fix how healthcare reaches the patients that need it most. First, we prioritize patient privacy, then we unlock smarter targeting, better measurement, and higher conversion rates. You think in funnels, and experiments. You're as comfortable talking about CAC and ROAS as you are pixels, events, and data flows. You provide direct answers, clear thinking, and --- TITLE: Support Engineer EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-07 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/d6f0af53-fbd9-400f-ba46-26f65ee26478 EXCERPT: Support Engineer Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. WHO WE'RE LOOKING FOR We're looking for a Support Engineer who thrives at the intersection of customer experience and deep technical problem-solving. You're someone who enjoys digging into complex systems, reading code, and figuring out how things work under the hood to resolve customer issues. You take full ownership from first report to final resolution, and you're driven to not just fix problems, but to improve the overall customer experience. --- TITLE: Senior Enterprise Account Manager EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-07 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/87e72e22-195c-4b38-8133-a8c805552b50 EXCERPT: Senior Enterprise Account Manager Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. What you'll be doing You will own the full lifecycle relationship for a book of Enterprise customers. You will help them navigate the healthcare data privacy landscape, adopt Freshpaint deeply across their stack, and expand their use of our platform over time. You will be directly responsible for net revenue retention across your accounts by driving adoption, renewals, and expansion while keeping customer outcomes at the center of --- TITLE: Head of Implementation EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-04 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/cd8da10e-4a19-49ca-bf4b-f30889f42046 EXCERPT: Head of Implementation Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. WHO WE'RE LOOKING FOR Freshpaint's success is defined by the success of our customers. As we scale our enterprise business, we are seeking a Head of Implementation to lead and evolve our implementation function. This is a director-level role responsible for building a world-class onboarding experience that accelerates time to value, ensures privacy-first excellence, and drives long-term customer outcomes. You will lead a team of Enterprise Implementation Engineers, define --- TITLE: Senior Enterprise Account Executive EMPLOYER: Freshpaint LOCATION: Remote - US | Remote (remote) SALARY: Not disclosed POSTED: 2026-06-07 PARENTAL_LEAVE_WEEKS: 16 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 16 (not source-backed) APPLY_URL: https://jobs.ashbyhq.com/freshpaint/5dc519d9-75b8-4331-8d02-fdf813061a63 EXCERPT: Senior Enterprise Account Executive Remote - US | Remote ABOUT FRESHPAINT: Healthcare is a $4+ trillion industry in the U.S. alone, and it's undergoing a rapid digital transformation. Hospitals, digital health companies, and life sciences organizations rely on analytics and advertising tools to reach patients, measure performance, and grow. But those tools weren't built for regulated healthcare data. That creates real compliance risk and forces teams to choose between growth and privacy. FRESHPAINT ELIMINATES THAT TRADE-OFF. We're a privacy-first data platform that helps healthcare organizations use modern marketing and analytics tools without exposing protected health information (PHI). Freshpaint sits between a company's website or app and the third-party tools they use, automatically detecting and controlling sensitive data before it's shared. In short: we let healthcare teams move fast, safely. BACKED BY TOP INVESTORS Freshpaint is backed by some of the most respected names in technology, including: - Y Combinator (OpenAI, Stripe, Airbnb, Coinbase, DoorDash) - Intel Capital (Broadcom, Astera Labs, VMware, RedHat, MongoDB) We've raised tens of millions of dollars in funding to build the privacy infrastructure layer for healthcare's digital future. WHAT YOU'LL BE DOING Freshpaint helps healthcare organizations modernize their data infrastructure so they can run world-class analytics and marketing while staying fully privacy compliant. As an Enterprise AE, you'll be responsible for driving new revenue, generating demand, navigating complex enterprise sales cycles, and representing Freshpaint's value to senior executives across Marketing, Product, Compliance, and Legal. This is a true builder role. You will be foundational to scaling --- TITLE: Lab Chemist - Cumming Lab (Cumming, GA) EMPLOYER: Tyson Foods LOCATION: Cumming Lab - Cumming, Georgia (unspecified) SALARY: Not disclosed POSTED: 2026-06-11 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://tysonfoods.wd5.myworkdayjobs.com/TSN/job/Cumming-Lab---Cumming-Georgia/Lab-Chemist---Cumming-Lab--Cumming--GA-_R0466916-2 EXCERPT: Lab Chemist - Cumming Lab (Cumming, GA) Cumming Lab - Cumming, Georgia posted: Posted Yesterday --- TITLE: Lab Technician (Analytical Lab) EMPLOYER: Boston Scientific Corporation LOCATION: | N/A (unspecified) SALARY: Not disclosed POSTED: 2026-06-12 APPLY_URL: https://bostonscientific.eightfold.ai/careers/job/563602812444139 EXCERPT: Lab Technician (Analytical Lab) | N/A --- TITLE: Lab Chemist, 1st Shift - Wilkesboro Lab (Wilkesboro, NC) EMPLOYER: Tyson Foods LOCATION: Corp Lab Services-Wilkesboro - Wilkesboro, North Carolina (unspecified) SALARY: Not disclosed POSTED: 2026-05-21 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://tysonfoods.wd5.myworkdayjobs.com/TSN/job/Corp-Lab-Services-Wilkesboro---Wilkesboro-North-Carolina/Lab-Chemist--1st-Shift---Wilkesboro-Lab--Wilkesboro--NC-_R0458023 EXCERPT: Lab Chemist, 1st Shift - Wilkesboro Lab (Wilkesboro, NC) Corp Lab Services-Wilkesboro - Wilkesboro, North Carolina posted: Posted 22 Days Ago --- TITLE: Lab Tech 1 EMPLOYER: Zoetis LOCATION: Denver Lab (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://zoetis.wd5.myworkdayjobs.com/zoetis/job/Denver-Lab/Lab-Tech-1_JR00020851-1 EXCERPT: Lab Tech 1 Denver Lab posted: Posted 2 Days Ago --- TITLE: Lab Supervisor - Core Lab EMPLOYER: Labcorp LOCATION: Knoxville TN (unspecified) SALARY: Not disclosed POSTED: 2026-05-15 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://labcorp.wd1.myworkdayjobs.com/External/job/Knoxville-TN/Lab-Supervisor---Core-Lab_267935 EXCERPT: Lab Supervisor - Core Lab Knoxville TN posted: Posted 28 Days Ago --- TITLE: Production Lab Assistant - Lab Ware EMPLOYER: Bio-Techne LOCATION: Minneapolis, MN (unspecified) SALARY: Not disclosed POSTED: 2026-05-12 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://biotechne.wd5.myworkdayjobs.com/biotechne/job/Minneapolis-MN/Production-Lab-Assistant---Lab-Ware_JR101152 EXCERPT: Production Lab Assistant - Lab Ware Minneapolis, MN posted: Posted 30+ Days Ago --- TITLE: Revenue Operations Coordinator I (Lab) EMPLOYER: DaVita LOCATION: 00303 - TRC Lab SGA (unspecified) SALARY: Not disclosed POSTED: 2026-05-27 PARENTAL_LEAVE_WEEKS: 6 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed) K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://davita.wd1.myworkdayjobs.com/DKC_External/job/00303---TRC-Lab-SGA/ROPS-Coordinator-I--Lab-_R0455765 EXCERPT: Revenue Operations Coordinator I (Lab) 00303 - TRC Lab SGA posted: Posted 16 Days Ago --- TITLE: Lab Manager, STAT & Physician's Office Labs EMPLOYER: Labcorp LOCATION: Birmingham AL (unspecified) SALARY: Not disclosed POSTED: 2026-06-01 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://labcorp.wd1.myworkdayjobs.com/External/job/Birmingham-AL/Lab-Manager--STAT---Physician-s-Office-Labs_2617379 EXCERPT: Lab Manager, STAT & Physician's Office Labs Birmingham AL posted: Posted 11 Days Ago --- TITLE: Medical Lab Technologist for Hospital Stat Lab EMPLOYER: Labcorp LOCATION: Issaquah WA (unspecified) SALARY: Not disclosed POSTED: 2026-05-27 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://labcorp.wd1.myworkdayjobs.com/External/job/Issaquah-WA/Medical-Lab-Technologist-for-Hospital-Stat-Lab_2617565 EXCERPT: Medical Lab Technologist for Hospital Stat Lab Issaquah WA posted: Posted 16 Days Ago --- TITLE: Research Lab Manager - Lab of Dr.Zachary Schug EMPLOYER: Jefferson Health LOCATION: Philadelphia, PA (unspecified) SALARY: Not disclosed POSTED: 2026-05-26 APPLY_URL: https://jeffersonhealth.wd5.myworkdayjobs.com/ThomasJeffersonExternal/job/Philadelphia-PA/Research-Lab-Manager_REQ-0030506-1 EXCERPT: Research Lab Manager - Lab of Dr.Zachary Schug Philadelphia, PA posted: Posted 17 Days Ago --- TITLE: Lab Engineer EMPLOYER: Enphase Energy LOCATION: Location not specified (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://jobs.jobvite.com/enphase-energy/job/ohk7zfw1 EXCERPT: Lab Engineer Lab Engineer --- TITLE: Lab Technician EMPLOYER: Atkore Inc LOCATION: Hobart IN (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://recruiting2.ultipro.com/ATK1000ATKOR/JobBoard/18eec16a-a1ec-458b-82c9-cb3af8866255/OpportunityDetail?opportunityId=88a76927-3ba6-4704-a2c5-cc62fc4a00e8 EXCERPT: Lab Technician Hobart IN Atkore, a recipient of a Great Place to Work© certification and a Top Workplaces USA award, is searching for a Lab Technician to be based out of our Hobart, IN facility. Reporting to the Lab Manager, this person will be responsible for testing each sample thoroughly, and aid in any maintenance, developmental projects, and calibration needed across the lab. --- TITLE: Lab Technician - Wet Lab - 3rd Shift EMPLOYER: Ttm Technologies Inc LOCATION: Chippewa Falls, WI (unspecified) SALARY: Not disclosed POSTED: 2026-06-08 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://ttmtech.wd5.myworkdayjobs.com/jobs/job/Chippewa-Falls-WI/Lab-Technician---Wet-Lab---3rd-Shift_R16371-1 EXCERPT: Lab Technician - Wet Lab - 3rd Shift Chippewa Falls, WI posted: Posted 4 Days Ago --- TITLE: Lab Associate - Dry Lab - 2nd Shift EMPLOYER: Ttm Technologies Inc LOCATION: Chippewa Falls, WI (unspecified) SALARY: Not disclosed POSTED: 2026-05-14 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://ttmtech.wd5.myworkdayjobs.com/jobs/job/Chippewa-Falls-WI/Lab-Associate---Dry-Lab---2nd-Shift_R15999 EXCERPT: Lab Associate - Dry Lab - 2nd Shift Chippewa Falls, WI posted: Posted 29 Days Ago --- TITLE: Photonics Lab Technician EMPLOYER: Xanadu LOCATION: Location not specified (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://xanadu.jazz.co/apply/ku7WvTj3mc/Photonics-Lab-Technician EXCERPT: Photonics Lab Technician Photonics Lab Technician --- TITLE: Lab Manager EMPLOYER: Atkore Inc LOCATION: Hobart IN (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://recruiting2.ultipro.com/ATK1000ATKOR/JobBoard/18eec16a-a1ec-458b-82c9-cb3af8866255/OpportunityDetail?opportunityId=d0d6f2cd-fd41-40cf-9f87-2cb5907c0144 EXCERPT: Lab Manager Hobart IN Atkore is currently searching for a Lab Manager to be based out of our Hobart, IN facility. Reporting to the Director of Industry Affairs, this person will be responsible for overseeing the testing and data recording for our electrical, safety, and infrastructure products to achieve third party certifications. Furthermore, this individual will manage a small team of direct reports that includes a Lab Engineer and a Lab Intern. --- TITLE: Senior Lead - Footwear Lab Standard & Method Engineer EMPLOYER: On Holding AG LOCATION: Ho Chi Minh City (unspecified) SALARY: Not disclosed POSTED: 2026-05-08 APPLY_URL: https://boards.greenhouse.io/onrunning/jobs/7907258?gh_jid=7907258 EXCERPT: Senior Lead - Footwear Lab Standard & Method Engineer Ho Chi Minh City In short You will work in a fast-paced environment that offers autonomy and opportunities for growth. As the Senior Lead - Laboratory for the Asia region, you will be instrumental in delivering world‑class laboratory operations aligned to global standards while driving localized execution, governance, and collaboration. You will act as the primary bridge between regional labs and the Zurich global lab leadership, ensuring consistency, data reliability, governance, and continuous improvement across all lab practices. You will champion standardization of processes, support local lab teams with training and operational excellence, and provide strategic input to enhance lab systems and reporting globally. Your Mission - Global Guidelines & Local Roll‑Out: Lead implementation and roll‑out of global lab guidelines, procedures, and standards across all labs in the Asia region. Translate global requirements into clear, actionable local practices, ensuring alignment with both global expectations and local realities. - Collaboration & Leadership: Act as a strong partner to the Zurich Global Lab Lead offering timely feedback, actionable insights, and strategic input into the development and refinement of global lab frameworks. Drive cross‑functional collaboration product development, sourcing, quality, and compliance stakeholders to ensure integrated lab processes. Leading central lab team members to work collaboratively with operation lab specialists on driving to the same business direction. - Supplier Representation & Transparency: Serve as the regional point of transparency for laboratory expectations and requirements across Tier 1 and Tier 2 business partners. Ensure structured escalation --- TITLE: Lab Product Owner - Customer Affordability & Data, Consumer Data Lab EMPLOYER: Lloyds Banking Group LOCATION: 3 Locations (unspecified) SALARY: Not disclosed POSTED: 2026-06-03 APPLY_URL: https://lbg.wd3.myworkdayjobs.com/LBG_Careers/job/Chester-Cawley-House/Lab-Product-Owner---Customer-Affordability---Data--Consumer-Data-Lab_157880-1 EXCERPT: Lab Product Owner - Customer Affordability & Data, Consumer Data Lab 3 Locations posted: Posted 9 Days Ago --- TITLE: Lab Buildout and Operations Manager, Integration & Test, Amazon Leo EMPLOYER: Amazon LOCATION: Redmond, Washington, USA (unspecified) SALARY: $126K-$165K POSTED: 2026-06-03 PARENTAL_LEAVE_WEEKS: 6 (not source-backed) NON_BIRTH_PARENT_LEAVE_WEEKS: 6 (not source-backed) APPLY_URL: https://www.amazon.jobs/en/jobs/10438123/lab-buildout-and-operations-manager-integration-test-amazon-leo EXCERPT: Lab Buildout and Operations Manager, Integration & Test, Amazon Leo Redmond, Washington, USA We are looking for a hands-on Lab Buildout and Operations Manager to own the deployment, readiness, and sustained operation of RF, networking, and system-integration lab environments. This role will manage lab infrastructure buildouts across Austin, San Diego, and Seattle, ensuring labs are built, instrumented, networked, documented, and operationally ready for engineering use. The ideal candidate has a strong mix of lab operations, RF test infrastructure, networking, procurement, vendor management, and hands-on systems experience. This person should be comfortable working across engineering, facilities, procurement, vendors, and site leadership to turn unclear lab requirements into executable build plans. Key Responsibilities Lab Buildout and Site Readiness - Own end-to-end lab buildout execution for RF and system-integration environments across Austin, San Diego, and Seattle. - Coordinate deployment of racks, benches, chambers, RF infrastructure, test equipment, control stations, cabling, power, grounding, cooling, and secure lab network access. - Drive readiness for RF test areas, integrated system test beds, hardware-in-the-loop environments, and production-representative lab setups. - Partner with Facilities, Networking, Security, Hardware, RF, Software, and Test teams to ensure lab spaces are usable, safe, scalable, and -operationally reliable. - Maintain lab bring-up schedules, punch lists, dependency trackers, and operational readiness checklists. RF, Network, and Test Infrastructure Operations - Support RF lab environments including chambers, antennas, attenuators, channel emulators, spectrum analyzers, signal generators, RF cabling, timing sources, and related instrumentation. - Support lab network design and operations, including VLANs, routing, switching, firewall access, remote --- TITLE: Lab Associate I EMPLOYER: Quest Diagnostics LOCATION: Chantilly, VA, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://hdox.fa.us6.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/requisitions/job/61231 EXCERPT: Lab Associate I Chantilly, VA, United States Lab Associate I --- TITLE: Lead Materials Science Lab (MSL) engineer and Lab Owner EMPLOYER: Hewlett-Packard LOCATION: Fort Collins, Colorado, United States of America (unspecified) SALARY: Not disclosed POSTED: 2026-06-12 APPLY_URL: https://hp.eightfold.ai/careers/job/42229729 EXCERPT: Lead Materials Science Lab (MSL) engineer and Lab Owner Fort Collins, Colorado, United States of America --- TITLE: Hospital Lab Supervisor EMPLOYER: Quest Diagnostics LOCATION: Bangor, ME, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-12 APPLY_URL: https://hdox.fa.us6.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/requisitions/job/61937 EXCERPT: Hospital Lab Supervisor Bangor, ME, United States Hospital Lab Supervisor --- TITLE: Lab Logistics Intern EMPLOYER: Garrett Motion Inc LOCATION: Shanghai, China (unspecified) SALARY: Not disclosed POSTED: 2026-06-04 APPLY_URL: https://ehth.fa.em2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_2001/requisitions/job/14524 EXCERPT: Lab Logistics Intern Shanghai, China Lab Logistics Intern --- TITLE: Lab Supervisor EMPLOYER: Intertek LOCATION: Kharagpur, West Bengal, India (unspecified) SALARY: Not disclosed POSTED: 2026-06-11 APPLY_URL: https://hcog.fa.em2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_2001/requisitions/job/15061 EXCERPT: Lab Supervisor Kharagpur, West Bengal, India Lab Supervisor - Softlines - Plastics - Kharagpur --- TITLE: Lab Technician (Non-Rep) - Path Lab Gen Histology Multi Site - Part Time, Night 8hrs EMPLOYER: Stanford Health Care LOCATION: PALO ALTO, California, United States of America (unspecified) SALARY: Not disclosed POSTED: 2026-05-28 APPLY_URL: https://stanfordmedicine.wd115.myworkdayjobs.com/SHC_External_Career_Site/job/3375-Hillview---Clinical---PALO-ALTO/Lab-Technician--Non-Rep----Path-Lab-Gen-Histology-Multi-Site---Part-Time--Night-8hrs_R2655758/apply EXCERPT: Lab Technician (Non-Rep) - Path Lab Gen Histology Multi Site - Part Time, Night 8hrs PALO ALTO, California, United States of America Embrace the role of a Lab Technician in our Pathology Lab, supporting multi-site operations on the night shift. Process specimens, maintain lab equipment, and ensure regulatory compliance while collaborating with a dynamic healthcare team. Ideal for detail-oriented professionals eager to contribute to innovative laboratory services in a leading medical institution. --- TITLE: Clinical Lab Scientist HLA Lab (Night Shift) EMPLOYER: Stanford Health Care LOCATION: PALO ALTO, California, United States of America (unspecified) SALARY: Not disclosed POSTED: 2026-06-05 APPLY_URL: https://stanfordmedicine.wd115.myworkdayjobs.com/SHC_External_Career_Site/job/3373-Hillview---Blood-Ctr---PALO-ALTO/Clinical-Lab-Scientist-HLA-Lab--Night-Shift-_R2655143/apply EXCERPT: Clinical Lab Scientist HLA Lab (Night Shift) PALO ALTO, California, United States of America Join us as a Clinical Laboratory Scientist at Stanford Blood Center's Histocompatibility Lab. Perform complex HLA antibody and crossmatching assays, lead technical training, and ensure regulatory compliance. Ideal for those with hands-on lab experience and a California CLS or CHS license. Grow your career in a high-impact, innovative environment. --- TITLE: Manager of Pathology and Lab Operations - Clin Lab Chem Hema Coag EMPLOYER: Stanford Health Care LOCATION: PALO ALTO, California, United States of America (unspecified) SALARY: Not disclosed POSTED: 2026-03-16 APPLY_URL: https://stanfordmedicine.wd115.myworkdayjobs.com/SHC_External_Career_Site/job/300P-Hospital---DEF-DiagTesting-500600---PALO-ALTO/Manager-of-Pathology-and-Lab-Operations---Clin-Lab-Chem-Hema-Coag-300P----Full-Time--8-Hour-Day-Shifts-_R2653955/apply EXCERPT: Manager of Pathology and Lab Operations - Clin Lab Chem Hema Coag PALO ALTO, California, United States of America Join our team as Manager of Pathology and Lab Operations at Stanford Health Care. Lead clinical labs, ensure regulatory compliance, manage budgets, and drive quality assurance. Collaborate with medical and laboratory leaders to optimize performance and deliver exceptional patient care. Grow your career in a dynamic, innovative healthcare environment. --- TITLE: Rel Lab Operator EMPLOYER: ON Semiconductor LOCATION: Dong Nai, Viet Nam (unspecified) SALARY: Not disclosed POSTED: 2026-05-20 APPLY_URL: https://hctz.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1001/requisitions/job/2505469 EXCERPT: Rel Lab Operator Dong Nai, Viet Nam Rel Lab Operator --- TITLE: Lab Assistant I EMPLOYER: Quest Diagnostics LOCATION: Grand Rapids, MI, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-11 APPLY_URL: https://hdox.fa.us6.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/requisitions/job/61323 EXCERPT: Lab Assistant I Grand Rapids, MI, United States Lab Assistant I --- TITLE: Lab Technician - Res. Biology (Contract) EMPLOYER: Biocryst Pharmaceuticals INC LOCATION: US_Alabama_Discovery Center (unspecified) SALARY: Not disclosed POSTED: 2026-05-12 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://biocryst.wd501.myworkdayjobs.com/External/job/US_Alabama_Discovery-Center/Lab-Technician---Res-Biology--Contract-_JR100125 EXCERPT: Lab Technician - Res. Biology (Contract) US_Alabama_Discovery Center JOB SUMMARY: This position will contribute to early R&D programs and clinical biomarker study programs in our Discovery Center of Excellence in Birmingham, Alabama. The Lab Technician has overall responsibility to maintain the organization of the Biology lab including managing laboratory supplies, updating compounds/biology reagents/kits inventories, lab notebooks, and specific lab equipment. The incumbent will also perform assigned duties to assist principal investigators in performing routine lab work. ESSENTIAL DUTIES & RESPONSIBILITIES: Assists with early research and development program studies including method development and compound testing. Assists with pharmacodynamic (PD) biomarker studies including sample login, storage, and organization. Assists with biological and biochemistry assays for compound testing and biomarker assessment. Supports the biologics program including antibody receiving, login, aliquot, storage, and inventory management. Performs preventive maintenance on specific lab equipment. Prepare reagents for routine work performed. Responsible for organizing, storing and maintaining compounds, biology reagents and kits (inventory) and general lab supplies (assisting with day-to-day organization of the biology lab). Responsible for lab cleaning and organization. Responsible for organizing laboratory notebooks. Manages the receipt, verification, and routing of incoming laboratory shipments within the biology lab. Provides timely assistance whenever needed in the laboratory. EXPERIENCE & QUALIFICATIONS: Bachelor's degree in biology or any relevant science-related field is required. Experience working in a lab is preferred. Good organization skills, attention to details, and willingness to help other lab members are essential. Ability to communicate effectively at all levels in the organization, verbally and in --- TITLE: Lab Manager EMPLOYER: Apple LOCATION: San Diego, United States of America (unspecified) SALARY: Not disclosed POSTED: 2026-06-02 K401_MATCH: yes (source-backed) K401_SOURCE_URL: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip APPLY_URL: https://jobs.apple.com/en-us/details/200665941/lab-manager?team=HRDWR EXCERPT: Lab Manager San Diego, United States of America At Apple, the tools we build with are just as important as the products we ship to the world. As an Electronics Lab Manager, you will be the backbone of our hardware engineering environment, ensuring our teams have everything they need to design, test, and iterate on the next generation of groundbreaking Apple products. If you thrive in a fast-paced, highly technical environment and take pride in building organized, efficient lab ecosystems, this role was made for you. What You'll Do You will own the full lifecycle of our EE lab operations, from day-to-day management to strategic planning and infrastructure buildout. Your work will directly enable engineers to move faster and build better. Lab Operations & Asset Management Oversee all aspects of EE lab operations including equipment, calibration, tools, materials, and device allocation Track lab assets, maintenance schedules, and calibration compliance to keep everything audit-ready Ensure full compliance with lab certifications and location-specific requirements Champion a culture of safety, security, and quality across all lab environments Equipment & Procurement Review test equipment specifications alongside the engineering team and partner with vendors to gather quotes and submit purchase orders Allocate EE benches and test equipment strategically based on project schedules and evolving team needs Lab Setup & Infrastructure Lead the setup and takedown of test stations and test racks as project needs demand Collaborate with Facilities teams on new lab buildouts from concept to completion Engineering Support Interpret schematics and manage sourcing of --- TITLE: Lab Technician EMPLOYER: Atkore Inc LOCATION: Hobart IN (unspecified) SALARY: Not disclosed POSTED: 2026-06-10 APPLY_URL: https://recruiting2.ultipro.com/ATK1000ATKOR/JobBoard/18eec16a-a1ec-458b-82c9-cb3af8866255/OpportunityDetail?opportunityId=e9496325-89bf-4389-bf4d-e03c9af7dc5a EXCERPT: Lab Technician Hobart IN We are currently looking for a Lab Technician to be based out of Hobart, Indiana, reporting to the Principal Engineer/Manager. The Lab Technician will be responsible for ensuring testing the parts are being produced at the production facility, working on sample preparation for metallurgical analysis, and helping failure analysis. --- TITLE: Lab Technician EMPLOYER: Intertek LOCATION: Kharagpur, West Bengal, India (unspecified) SALARY: Not disclosed POSTED: 2026-06-11 APPLY_URL: https://hcog.fa.em2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_2001/requisitions/job/15060 EXCERPT: Lab Technician Kharagpur, West Bengal, India Lab Technician - Softlines (Plastic) - Kharagpur (WB) --- TITLE: Lab Assistant II EMPLOYER: Quest Diagnostics LOCATION: Lewisville, TX, United States (unspecified) SALARY: Not disclosed POSTED: 2026-06-12 APPLY_URL: https://hdox.fa.us6.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/requisitions/job/62303 EXCERPT: Lab Assistant II Lewisville, TX, United States Lab Assistant II --- TITLE: Lab Lead Test Technician EMPLOYER: Garrett Motion Inc LOCATION: Hubei, China (unspecified) SALARY: Not disclosed POSTED: 2026-04-24 APPLY_URL: https://ehth.fa.em2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_2001/requisitions/job/14202 EXCERPT: Lab Lead Test Technician Hubei, China Lab Lead Test Technician --- [PASTE YOUR RESUME OR SKILLS HERE]