# FewerJobs export - 100 curated jobs Generated: 2026-06-20T09:12:50.080Z Source: https://fewerjobs.com ## Filters applied - **q**: Sumo Logic - **quality_floor**: default - **match_401k_strict**: true - **parental_strict**: true - **non_birth_strict**: true - **pto_strict**: true - **include_older**: false - **verified_benefits_only**: true - **apply_url_verified**: false - **page**: 1 - **per_page**: 100 - **sort**: relevance ## Jobs ### Field Engineer - Automated Logic (ALC) - Carrier Global - Location: CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM69-ALC---Mass-Canton-95-Shawmut-Road-Canton-MA-02021-USA/Field-Engineer---Automated-Logic--ALC-_30196801 - Excerpt: Field Engineer - Automated Logic (ALC) CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA posted: Posted 14 Days Ago ### Automated Logic- Associate Controls Engineer - Carrier Global - Location: CAF43: AL Florida (MCO), 7305 Greenbriar Parkway, Orlando, FL, 32819 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-04 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAF43-AL-Florida-MCO-7305-Greenbriar-Parkway-Orlando-FL-32819-USA/Automated-Logic--Associate-Controls-Engineer_30206906 - Excerpt: Automated Logic- Associate Controls Engineer CAF43: AL Florida (MCO), 7305 Greenbriar Parkway, Orlando, FL, 32819 USA posted: Posted 8 Days Ago ### Service Account Manager - Automated Logic - Carrier Global - Location: CAG11: ALC Other HG, 1025 Cobb Place Boulevard, Kennesaw, GA, 30144 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAG11-ALC-Other-HG-1025-Cobb-Place-Boulevard-Kennesaw-GA-30144-USA/Service-Account-Manager---Automated-Logic_30206913 - Excerpt: Service Account Manager - Automated Logic CAG11: ALC Other HG, 1025 Cobb Place Boulevard, Kennesaw, GA, 30144 USA posted: Posted 10 Days Ago ### Associate Controls Engineer - Automated Logic - Building Automation (BAS) - Carrier Global - Location: CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN79-Clifton-100-Delawanna-Avenue-Clifton-NJ-07014-USA/Associate-Controls-Engineer---Automated-Logic---Building-Automation--BAS-_30207246-2 - Excerpt: Associate Controls Engineer - Automated Logic - Building Automation (BAS) CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA posted: Posted 10 Days Ago ### Service Sales Representative- Automated Logic - Carrier Global - Location: CAA11: ALC West AZ, 4615 South 33rd Place, Phoenix, AZ, 85040 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAA11-ALC-West-AZ-4615-South-33rd-Place-Phoenix-AZ-85040-USA/Service-Sales-Representative--Automated-Logic_30204359 - Excerpt: Service Sales Representative- Automated Logic CAA11: ALC West AZ, 4615 South 33rd Place, Phoenix, AZ, 85040 USA posted: Posted 14 Days Ago ### Senior Sales Estimator - Automated Logic - Carrier Global - Location: CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-19 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN79-Clifton-100-Delawanna-Avenue-Clifton-NJ-07014-USA/Senior-Sales-Estimator---Automated-Logic_30206185 - Excerpt: Senior Sales Estimator - Automated Logic CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA posted: Posted 24 Days Ago ### Automated Logic – BAS/BMS Lead Field Technician - Carrier Global - Location: CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM69-ALC---Mass-Canton-95-Shawmut-Road-Canton-MA-02021-USA/Automated-Logic---BAS-BMS-Lead-Field-Technician_30201964-1 - Excerpt: Automated Logic – BAS/BMS Lead Field Technician CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA posted: Posted 14 Days Ago ### Owner Direct Sales Manager - Automated Logic - Carrier Global - Location: CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN79-Clifton-100-Delawanna-Avenue-Clifton-NJ-07014-USA/Owner-Direct-Sales-Manager---Automated-Logic_30205746 - Excerpt: Owner Direct Sales Manager - Automated Logic CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA posted: Posted 4 Days Ago ### Project Manager (Austin, TX) - Automated Logic - Carrier Global - Location: CAT89: ALC Austin, 11100 Metric Boulevard, Austin, TX, 78758 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT89-ALC-Austin-11100-Metric-Boulevard-Austin-TX-78758-USA/Project-Manager--Austin--TX----Automated-Logic_30199380 - Excerpt: Project Manager (Austin, TX) - Automated Logic CAT89: ALC Austin, 11100 Metric Boulevard, Austin, TX, 78758 USA posted: Posted 11 Days Ago ### Automated Logic – BAS/BMS Master Field Technician - Carrier Global - Location: CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM69-ALC---Mass-Canton-95-Shawmut-Road-Canton-MA-02021-USA/Automated-Logic---BAS-BMS-Master-Field-Technician_30192608 - Excerpt: Automated Logic – BAS/BMS Master Field Technician CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA posted: Posted 22 Days Ago ### Field Service Engineer - Automated Logic - Carrier Global - Location: CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAO06-CCS-Westerville-752-Brooksedge-Plaza-Drive-Westerville-OH-43081-USA/Field-Service-Engineer---Automated-Logic_30204957-1 - Excerpt: Field Service Engineer - Automated Logic CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA posted: Posted 9 Days Ago ### Automated Logic- Project Manager - Carrier Global - Location: CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-27 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN79-Clifton-100-Delawanna-Avenue-Clifton-NJ-07014-USA/Automated-Logic--Project-Manager_30204353 - Excerpt: Automated Logic- Project Manager CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA posted: Posted 16 Days Ago ### Automated Logic- Project Engineer - Carrier Global - Location: CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-04 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN79-Clifton-100-Delawanna-Avenue-Clifton-NJ-07014-USA/Automated-Logic--Project-Engineer_30204453 - Excerpt: Automated Logic- Project Engineer CAN79: Clifton, 100 Delawanna Avenue, Clifton, NJ, 07014 USA posted: Posted 8 Days Ago ### Field Engineer - Automated Logic - Carrier Global - Location: CAT98: ALC McAllen, 200 North Mccoll Road, Mcallen, TX, 78501 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT98-ALC-McAllen-200-North-Mccoll-Road-Mcallen-TX-78501-USA/Field-Engineer---Automated-Logic_30205201 - Excerpt: Field Engineer - Automated Logic CAT98: ALC McAllen, 200 North Mccoll Road, Mcallen, TX, 78501 USA posted: Posted 11 Days Ago ### Project Manager-Automated Logic - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Specialist--Project-Managment_30207185 - Excerpt: Project Manager-Automated Logic CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 14 Days Ago ### Lead Tech, Field Svc-Automated Logic - Carrier Global - Location: CAT78: Pasadena, 290 Beltway Green Boulevard, Pasadena, TX, 77503 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT78-Pasadena-290-Beltway-Green-Boulevard-Pasadena-TX-77503-USA/Lead-Field-Engineer_30206416 - Excerpt: Lead Tech, Field Svc-Automated Logic CAT78: Pasadena, 290 Beltway Green Boulevard, Pasadena, TX, 77503 USA posted: Posted 9 Days Ago ### Building Automation Specialist - Automated Logic - Carrier Global - Location: CAN05: CCS-Charlotte, 5900 Northwoods Business Parkway, Charlotte, NC, 28269 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN05-CCS-Charlotte-5900-Northwoods-Business-Parkway-Charlotte-NC-28269-USA/Building-Automation-Specialist---Automated-Logic_30205479 - Excerpt: Building Automation Specialist - Automated Logic CAN05: CCS-Charlotte, 5900 Northwoods Business Parkway, Charlotte, NC, 28269 USA posted: Posted 2 Days Ago ### Operations Manager - Automated Logic - Carrier Global - Location: CAT89: ALC Austin, 11100 Metric Boulevard, Austin, TX, 78758 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT89-ALC-Austin-11100-Metric-Boulevard-Austin-TX-78758-USA/Operations-Manager---Automated-Logic_30203373 - Excerpt: Operations Manager - Automated Logic CAT89: ALC Austin, 11100 Metric Boulevard, Austin, TX, 78758 USA posted: Posted 11 Days Ago ### Senior Associate Project Manager - Automated Logic - Carrier Global - Location: CAW62: 10419 & 10411 East Trent Avenue, Spokane, WA, 99206 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAW62-10419--10411-East-Trent-Avenue-Spokane-WA-99206-USA/Senior-Associate-Project-Manager---Automated-Logic_30206802 - Excerpt: Senior Associate Project Manager - Automated Logic CAW62: 10419 & 10411 East Trent Avenue, Spokane, WA, 99206 USA posted: Posted 10 Days Ago ### Associate Field Engineer - Automated Logic - Carrier Global - Location: CAT78: Pasadena, 290 Beltway Green Boulevard, Pasadena, TX, 77503 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT78-Pasadena-290-Beltway-Green-Boulevard-Pasadena-TX-77503-USA/Associate-Field-Engineer---Automated-Logic_30207406-1 - Excerpt: Associate Field Engineer - Automated Logic CAT78: Pasadena, 290 Beltway Green Boulevard, Pasadena, TX, 77503 USA posted: Posted 10 Days Ago ### Master Field Engineer - Automated Logic - Carrier Global - Location: CATX3: 1218 Arion Parkway, San Antonio, TX, 78216 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CATX3-1218-Arion-Parkway-San-Antonio-TX-78216-USA/Master-Field-Engineer---Automated-Logic_30195511-2 - Excerpt: Master Field Engineer - Automated Logic CATX3: 1218 Arion Parkway, San Antonio, TX, 78216 USA posted: Posted 10 Days Ago ### Business Manager - Logic Components - Rockwell Automation - Location: Milwaukee, Wisconsin, United States (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://rockwellautomation.wd1.myworkdayjobs.com/External_Rockwell_Automation/job/Milwaukee-Wisconsin-United-States/Business-Manager---Logic-Components_R26-1034-1 - Excerpt: Business Manager - Logic Components Milwaukee, Wisconsin, United States posted: Posted 30+ Days Ago ### Lead Logic Design Engineer - NXP Semiconductors - Location: Bangalore (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Bangalore/Lead-Logic-Design-Engineer_R-10063177 - Excerpt: Lead Logic Design Engineer Bangalore posted: Posted 30+ Days Ago ### Mission Critical Project Manager - Automated Logic - Carrier Global - Location: 5 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-05-19 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAFLO-Carrier-Home-Florida-Remote-Location-Remote-City-FL-33412-USA/Mission-Critical-Project-Manager---Automated-Logic_30206569 - Excerpt: Mission Critical Project Manager - Automated Logic 5 Locations posted: Posted 24 Days Ago ### Mission Critical Project Manager - Automated Logic - Carrier Global - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAFLO-Carrier-Home-Florida-Remote-Location-Remote-City-FL-33412-USA/Mission-Critical-Project-Manager---Automated-Logic_30206318 - Excerpt: Mission Critical Project Manager - Automated Logic 2 Locations posted: Posted Today ### Mission Critical Project Manager - Automated Logic - Carrier Global - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-05-26 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAFLO-Carrier-Home-Florida-Remote-Location-Remote-City-FL-33412-USA/Mission-Critical-Project-Manager---Automated-Logic_30206559 - Excerpt: Mission Critical Project Manager - Automated Logic 2 Locations posted: Posted 17 Days Ago ### Logic Design Engineer - NXP Semiconductors - Location: Kanata (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Kanata/Logic-Design-Engineer_R-10063873-1 - Excerpt: Logic Design Engineer Kanata posted: Posted 3 Days Ago ### Mission Critical BAS/BMS Master Field Engineer - Automated Logic - Carrier Global - Location: 5 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CANJO-Carrier-Home-New-Jersey-Remote-Location-Remote-City-NJ-07001-USA/Automated-Logic--Critical-Systems-BAS-BMS-Master-Field-Engineer_30203713 - Excerpt: Mission Critical BAS/BMS Master Field Engineer - Automated Logic 5 Locations posted: Posted 11 Days Ago ### Automated Logic- BAS/BMS Field Technician - Carrier Global - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAP27-ALC--Harrisburg-6345-Flank-Drive-Harrisburg-PA-17112-USA/Automated-Logic--BAS-BMS-Field-Technician_30197891 - Excerpt: Automated Logic- BAS/BMS Field Technician 2 Locations posted: Posted 2 Days Ago ### Sales Manager- Automated Logic - Carrier Global - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM69-ALC---Mass-Canton-95-Shawmut-Road-Canton-MA-02021-USA/Sales-Manager--Automated-Logic_30207254 - Excerpt: Sales Manager- Automated Logic 2 Locations posted: Posted 11 Days Ago ### Controls Field Service Engineer - Automated Logic - Carrier Global - Location: CAM27: St. Paul, 953 Westgate Drive, Saint Paul, MN, 55114 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM27-St-Paul-953-Westgate-Drive-Saint-Paul-MN-55114-USA/Controls-Field-Service-Engineer---Automated-Logic_30195859-2 - Excerpt: Controls Field Service Engineer - Automated Logic CAM27: St. Paul, 953 Westgate Drive, Saint Paul, MN, 55114 USA posted: Posted 23 Days Ago ### Automated Logic- BAS/BMS Master Field Technician - Carrier Global - Location: CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-05 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAM69-ALC---Mass-Canton-95-Shawmut-Road-Canton-MA-02021-USA/Automated-Logic--BAS-BMS-Master-Field-Technician_30206296 - Excerpt: Automated Logic- BAS/BMS Master Field Technician CAM69: ALC - Mass (Canton), 95 Shawmut Road, Canton, MA, 02021 USA posted: Posted 7 Days Ago ### Automated Logic- BAS/BMS Field Technician - Carrier Global - Location: CAN12: ALC West NM, 4020 Vassar Drive Northeast, Albuquerque, NM, 87107 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-04 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN12-ALC-West-NM-4020-Vassar-Drive-Northeast-Albuquerque-NM-87107-USA/Automated-Logic--BAS-BMS-Field-Technician_30196792 - Excerpt: Automated Logic- BAS/BMS Field Technician CAN12: ALC West NM, 4020 Vassar Drive Northeast, Albuquerque, NM, 87107 USA posted: Posted 8 Days Ago ### Lead Building Automation Specialist - Automated Logic - Carrier Global - Location: CAN81: AL N Carolina (GSO), 307 Pomona Drive, Greensboro, NC, 27407 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAN81-AL-N-Carolina-GSO-307-Pomona-Drive-Greensboro-NC-27407-USA/Lead-Building-Automation-Specialist---Automated-Logic_30202329 - Excerpt: Lead Building Automation Specialist - Automated Logic CAN81: AL N Carolina (GSO), 307 Pomona Drive, Greensboro, NC, 27407 USA posted: Posted 11 Days Ago ### Project Manager - Automated Logic (Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Project-Manager---Automated-Logic--Waco--TX-_30204070 - Excerpt: Project Manager - Automated Logic (Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 11 Days Ago ### Field Supervisor - Automated Logic (Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Field-Supervisor---Automated-Logic--Waco--TX-_30204069 - Excerpt: Field Supervisor - Automated Logic (Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 11 Days Ago ### Field Engineer (Columbus, OH) - Automated Logic - Carrier Global - Location: CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAO06-CCS-Westerville-752-Brooksedge-Plaza-Drive-Westerville-OH-43081-USA/Field-Engineer--Columbus--OH----Automated-Logic_30205475 - Excerpt: Field Engineer (Columbus, OH) - Automated Logic CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA posted: Posted 11 Days Ago ### Lead Field Service Engineer – Automated Logic - Carrier Global - Location: CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAO06-CCS-Westerville-752-Brooksedge-Plaza-Drive-Westerville-OH-43081-USA/Lead-Field-Service-Engineer---Automated-Logic_30204956 - Excerpt: Lead Field Service Engineer – Automated Logic CAO06: CCS-Westerville, 752 Brooksedge Plaza Drive, Westerville, OH, 43081 USA posted: Posted 9 Days Ago ### Mission Critical Associate Project Manager - Automated Logic - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-05 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Automated-Logic--Critical-Systems-Associate-Project-Manager_30205716 - Excerpt: Mission Critical Associate Project Manager - Automated Logic CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 7 Days Ago ### Automated Logic – Senior Field Engineer – Tampa Bay Area - Carrier Global - Location: CAF43: AL Florida (MCO), 7305 Greenbriar Parkway, Orlando, FL, 32819 USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAF43-AL-Florida-MCO-7305-Greenbriar-Parkway-Orlando-FL-32819-USA/Automated-Logic---Senior-Field-Engineer---Tampa-Bay-Area_30204021 - Excerpt: Automated Logic – Senior Field Engineer – Tampa Bay Area CAF43: AL Florida (MCO), 7305 Greenbriar Parkway, Orlando, FL, 32819 USA posted: Posted 14 Days Ago ### Automated Logic- BAS/BMS Field Technician- Dallas, TX - Carrier Global - Location: CATXO: Carrier-Home Texas Remote Location, Remote City, TX, 75001 USA (remote) - Salary: Not disclosed - Posted: 2026-05-28 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Hires in: TX - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CATXO-Carrier-Home-Texas-Remote-Location-Remote-City-TX-75001-USA/Automated-Logic--BAS-BMS-Field-Technician--Dallas--TX_30204454 - Excerpt: Automated Logic- BAS/BMS Field Technician- Dallas, TX CATXO: Carrier-Home Texas Remote Location, Remote City, TX, 75001 USA posted: Posted 15 Days Ago ### Associate Field Engineer - Automated Logic (Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Associate-Field-Engineer-Automated-Logic_30204650 - Excerpt: Associate Field Engineer - Automated Logic (Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 4 Days Ago ### Sr. Controls Sales Executive – Automated Logic - Carrier Global - Location: CANYO: Carrier-Home New York Remote Location, Remote City, NY, 13088 USA (remote) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Hires in: NY - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CANYO-Carrier-Home-New-York-Remote-Location-Remote-City-NY-13088-USA/Sr-Controls-Sales-Executive---Automated-Logic_30201834 - Excerpt: Sr. Controls Sales Executive – Automated Logic CANYO: Carrier-Home New York Remote Location, Remote City, NY, 13088 USA posted: Posted 22 Days Ago ### Associate Project Manager - Automated Logic(Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Associate-Project-Manager--Waco--TX----Automated-Logic_30204164 - Excerpt: Associate Project Manager - Automated Logic(Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 11 Days Ago ### Associate Project Manager - Automated Logic(Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Associate-Project-Manager-Automated-Logic_30204159 - Excerpt: Associate Project Manager - Automated Logic(Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 4 Days Ago ### Automated Logic- BAS/BMS Field Technician- Northern Virginia area - Carrier Global - Location: CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-04 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAV20-ALC---Virginia-4948-Dominion-Boulevard-Glen-Allen-VA-23060-USA/Automated-Logic--BAS-BMS-Field-Technician--Northern-Virginia-area_30203056 - Excerpt: Automated Logic- BAS/BMS Field Technician- Northern Virginia area CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA posted: Posted 8 Days Ago ### Automated Logic- BAS/BMS Associate Field Technician- Northern Virginia Area - Carrier Global - Location: CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-05 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAV20-ALC---Virginia-4948-Dominion-Boulevard-Glen-Allen-VA-23060-USA/Automated-Logic--BAS-BMS-Associate-Field-Technician--Northern-Virginia-Area_30206897 - Excerpt: Automated Logic- BAS/BMS Associate Field Technician- Northern Virginia Area CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA posted: Posted 7 Days Ago ### Material Procurement Associate Project Manager - Automated Logic(Waco, TX) - Carrier Global - Location: CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAT16-CCS-Dallas-1901-N-Glenville-Drive-Richardson-TX-75081-USA/Material-Procurement-Associate-Project-Manager--Waco--TX----Automated-Logic_30204166 - Excerpt: Material Procurement Associate Project Manager - Automated Logic(Waco, TX) CAT16: CCS-Dallas, 1901 N. Glenville Drive, Richardson, TX, 75081 USA posted: Posted 9 Days Ago ### Automated Logic- BAS/BMS Lead Field Technician- Harrisonburg, Charlottesville, Roanoke area, VA - Carrier Global - Location: CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAV20-ALC---Virginia-4948-Dominion-Boulevard-Glen-Allen-VA-23060-USA/Automated-Logic--BAS-BMS-Lead-Field-Technician--Harrisonburg--Charlottesville--Roanoke-area--VA_30206254 - Excerpt: Automated Logic- BAS/BMS Lead Field Technician- Harrisonburg, Charlottesville, Roanoke area, VA CAV20: ALC - Virginia, 4948 Dominion Boulevard, Glen Allen, VA, 23060 USA posted: Posted 9 Days Ago ### ASIC and Logic Design Engineering Manager (Teradyne, North Reading) - Teradyne - Location: North Reading, MA (unspecified) - Salary: $156K-$249K - Posted: 2026-06-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-ASIC-and-Logic-Design-Engineering-Manager-%28Teradyne%2C-North-Reading%29-MA/1376122700/ - Excerpt: ASIC and Logic Design Engineering Manager (Teradyne, North Reading) North Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview The Logic Design Manager is responsible for leading a team of developers in designing and verifying FPGA's for Teradyne Compute Test Division's next generation products. In this role you will lead a team of ~4 ### Principal Software Engineer - Oracle - Location: Austin, TX, United States, US (unspecified) - Salary: $100K-$223K - Posted: 2026-06-11 - Parental leave: 14 weeks (not source-backed) - Non-birth-parent leave: 14 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://careers.oracle.com/en/sites/jobsearch/job/334278/ - Excerpt: Principal Software Engineer Austin, TX, United States, US About You You work backward from users and operational needs. You care about building usable, reliable software that helps engineering and operations teams reason about complex physical infrastructure. You can learn and model domain concepts such as fabrics, devices, racks, ports, pluggables, patch panels, cable paths, data halls, and topology rules, while keeping the focus on clean software abstractions and maintainable systems. You have strong communication skills and can clearly explain complex technical concepts, tradeoffs, and system behavior. You work well across disciplines. You can lead conversations with engineers, product managers, infrastructure specialists, network engineers, and partner teams, and translate ambiguous requirements into practical software designs. You are comfortable with ambiguity. You have a strong sense of ownership and can drive projects from design through implementation, rollout, validation, and production support. You are comfortable working across different layers of the stack, including APIs, services, persistence, validation logic, tooling, and operational workflows. Responsibilities Design, build, and operate highly available services that support OCI Layer 1 network modeling and infrastructure lifecycle management. Drive development of core platform capabilities, including topology modeling, workflow orchestration, validation, reconciliation, API design, and integration with downstream systems. Work with large and complex data models representing infrastructure resources, physical topology, logical connectivity, network devices, ports, racks, rooms, cable paths, configurations, and operational state. Build software that converts network infrastructure intent into reliable, validated system state. Develop validation frameworks and tools that compare intended logical topology against physical cabling, generated connections, ### Controls Technician (Automatisierungstechniker/MSR-Techniker) (German) - Google - Location: Kronstorf, Austria (unspecified) - Salary: EUR 58K-60K - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWk5a9tS1j3DvfXND8KC5cKuhRFMBrQoWt1dMzNEbPUqEjsACxwdTN8kJ94LMarEqD3GCf5Vzzgu1sQBRVXgYSUK0H8Je0QlqKF8jCJWrRcUilk2SalR1cFSWqcOhA%3D%3D_V2&loc=AT&title=Controls+Technician - Excerpt: Controls Technician (Automatisierungstechniker/MSR-Techniker) (German) Kronstorf, Austria The Data Center team designs and operates some of the most sophisticated electrical engineering, mechanical engineering and Heating, Ventilation and Air Conditioning (HVAC) systems in the world. Facilities Technicians at Google data centers operate, monitor and support physical facilities conditions. Some of these duties will include heating and cooling of air and water, power supply, generators, UPS systems, electrical distribution and control and monitoring systems. You regularly help inspect, maintain and repair various data center systems such as piping and non-critical electrical or mechanical system components). You provide daily assistance to senior technicians as you read blueprints/schematics, conduct tours of systems and assess their working order. As an advocate for best practices, you develop creative approaches to reducing operational costs while improving overall data center efficiency. You ensure that environmental and safety standards are consistently met, identifying problems and making repairs quickly. In emergency situations or abnormal conditions, you manage data center performance issues and outages to minimize the recovery time from failures. As a Technician, you will ensure 24/7 reliability of our physical infrastructure, moving beyond general maintenance, your primary focus is the 'nervous system' of the data center: managing the Programmable Logic Controllers (PLCs), Supervisory Control and Data Acquisition (SCADA) interfaces, and critical alarm logic that control our power and cooling. You will provide technical support by interpreting ladder logic and sequence of operations, troubleshooting control anomalies, and managing the commissioning and integration of new controls equipment. In this role, you ensure ### Senior ASIC RTL Engineer, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSBRDDxQYFWWu0g0PTlndGqFDVjeSfl7R2ge6f47a7zAEjsACxwdTHwBgoE_-XkQRExGQxlgt_0MQOgz3OYVVPskQcR2CULp-irjTcYeNNpS9zb3ONMx7hfJoYUDRQ%3D%3D_V2&loc=IN&title=Senior+ASIC+RTL+Engineer - Excerpt: Senior ASIC RTL Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in ### Senior Research Scientist, Superconducting Digital Electronics, Quantum AI - Google - Location: Cambridge, MA, USA; +5 more (unspecified) - Salary: $174K-$253K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU9OdrBuwpSRBOIXEdYVplduLEyWqRGAKDUVO_nIFJqREjsACxwdTNV6erPcLK3AaQuSE58YIWPI7gePy-rGUNn7MjbcUmKTf4Rg8MqPcInQuHgOr5DOpm93d_N-CA%3D%3D_V2&loc=US&title=Senior+Research+Scientist - Excerpt: Senior Research Scientist, Superconducting Digital Electronics, Quantum AI Cambridge, MA, USA; +5 more As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as single flux quantum (SFQ) logic and adiabatic quantum flux parametron (AQFP) logic) for qubit control and readout. You will engage in co-design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and aim performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish IC design standards that are compatible for both the sensitive superconducting qubits and the co-located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computer. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computers. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant ### TPU RTL Design Engineer, Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRlx3V2kfLOXvYwfGD7xNXtbXJi14xxv4VIeqHESGFH6EjsACxwdTEmphvK_rqhhd94s3rfXRZD-xbrEHxChYMtX-elkfXMJi6KTWRQReCWEy58kwZPD4x9ZPDFC_A%3D%3D_V2&loc=US&title=TPU+RTL+Design+Engineer - Excerpt: TPU RTL Design Engineer, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. You will be responsible for the microarchitecture, design, and implementation of key digital logic blocks within the TPU. Your role requires collaborating with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver hardware. You will own critical design deliverables and contribute to the continuous improvement of our design methodologies and flows. This position offers the opportunity to manage technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers ### RTL Design and Integration Engineer, TPU and ML - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckW3HrwPAW6XFS0kaZT5Dh8Zu-xrameTBruIPMM9C7c06EjsACxwdTEIRn06AQPEAA86H7R-ozUW6Zn-SxJjoTQI2DaK0c_gd9nC2RfkhzUMunDL1Q2ywKVwKcVk-yg%3D%3D_V2&loc=US&title=RTL+Design+and+Integration+Engineer - Excerpt: RTL Design and Integration Engineer, TPU and ML Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including verification, physical design, validation, and firmware, to deliver hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough ### RTL Design and Integration Engineer - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $116K-$166K - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckR4BUKQ53z5jfRBgUqfjLXTgKNoxP5AC_sxqJ9Xg5mIeEjsACxwdTAxmgCiiIE8mdrkpFNTul_qHOIjieOf6Rkms9RO_EmQdcXX9AAG_o3AIt4_JqOMn78cIlYYD1w%3D%3D_V2&loc=US&title=RTL+Design+and+Integration+Engineer - Excerpt: RTL Design and Integration Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and ### Senior Staff Research Scientist, Quantum Error Correction, Quantum AI - Google - Location: Goleta, CA, USA (unspecified) - Salary: $262K-$365K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU0N6o_3h5uZmsR3pyV32c0kgR-QQRIUi6NRAQwxaDFkEjsACxwdTMlGpuSdI2UqCmnEvk2Nyc9IkMl2ZeNUJE0htEJVKoKKHEf-UnUBxcOdkCjHoReEuRL02kVudQ%3D%3D_V2&loc=US&title=Senior+Staff+Research+Scientist - Excerpt: Senior Staff Research Scientist, Quantum Error Correction, Quantum AI Goleta, CA, USA In this role, you will be a senior researcher on the quantum error correction team within Quantum AI, responsible for setting research agendas into new and improved forms of quantum error correction. You will explore exciting research directions including quantum LDPC codes and compact circuits for non-clifford gates such as magic-state cultivation. As a Research Scientist, you will actively contribute to the wider research community by sharing and publishing your findings, with ideas inspired by internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $262000 - $365000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop new quantum codes that achieve high encoding rate, high distance, or favorable layout in hardware. Develop new constructions for non-clifford logical gates. Analyze fault-tolerant circuits for syndrome measurement and logical operations. Minimum qualifications: PhD or equivalent experience in a domain relevant to quantum computing, such as math, physics, computer science, or electrical engineering. 10 years of experience ### Senior Design and Integration Engineer, Cloud TPU - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcYoH0HRbh82KuqBliMW9QkTPf8wTubHV35vD__Rus2pEjsACxwdTCAFWkOXs-0k-evitw1Gxp6FZ7oC2p3SFFsFuYJxEDmWjaU1NMFB8DDl4nIazbeA_1J8LF9toA%3D%3D_V2&loc=US&title=Senior+Design+and+Integration+Engineer - Excerpt: Senior Design and Integration Engineer, Cloud TPU Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering ### ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) - Teradyne - Location: North Reading Asicfpga Design Verification Engineer Teradyne N Reading, MA (unspecified) - Salary: $123K-$197K - Posted: 2026-06-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-ASICFPGA-Design-Verification-Engineer-%28Teradyne%2C-N_-Reading%2C-MA%29-MA/1378786900/ - Excerpt: ASIC/FPGA Design Verification Engineer (Teradyne, N. Reading, MA) North Reading Asicfpga Design Verification Engineer Teradyne N Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation, and delivers better business results. Opportunity Overview Our Logic Design Engineering (LDE) team is seeking a Digital Logic Verification Engineer, preferably with additional experience in FPGA design. The primary focus of this role is FPGA verification, working closely ### Full Chip Front-End DFT Engineer - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-04 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQmkGMNxEOLf5fszHuCRgysyUDjQcfqY4byMnLQI2BgXEjsACxwdTPQB1LJ0MmFugAgDm9vsquT2hri_nGQRdGkdTdujyF3UPmYh2_ryhsz6eTBASkWhAUbnXCgIow%3D%3D_V2&loc=IN&title=Full+Chip+Front-End+DFT+Engineer - Excerpt: Full Chip Front-End DFT Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits. Implement DFT logic, boundary scan, MBIST, scan chains, DFT compression, Clock Control block, and other DFT Internet Protocol (IP) blocks. Work with the Register Transfer Level (RTL) and Physical Design (PD) team at SoC level, and with the subsystem DFT teams. Write scripts to automate the DFT flow. Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow. Minimum qualifications: Bachelor's degree in Science or Electrical or Electronics Engineering or a related technical field or equivalent practical experience. 5 years of experience with ATPG, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. 3 ### LMTS - AI Automation Engineer - Offensive Security - Salesforce - Location: India - Hyderabad (unspecified) - Salary: Not disclosed - Posted: 2026-05-13 - Parental leave: 26 weeks (not source-backed) - Non-birth-parent leave: 12 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://careers.salesforce.com/en/jobs/jr332791/lmts-ai-automation-engineer-offensive-security/ - Excerpt: LMTS - AI Automation Engineer - Offensive Security India - Hyderabad We are looking for a Lead AI Automation engineer to design and build advanced AI-driven automation that supports offensive security and security research workflows. This is a deeply hands-on engineering role. You will work closely with the AI Automation Director and a small, agile team to implement orchestrated, agent-based automation-translating architectural direction into reliable, production-grade systems. The focus is on building automation that can reason over complex data, coordinate multi-step actions, and operate safely in real environments. This role is ideal for an experienced engineer who has built real AI systems, understands their limitations, and wants to apply them to complex, adversarial problem spaces. Key Responsibilities Design, implement, and maintain agent-based AI automation workflows under the technical direction of the AI Automation Director Build systems capable of: Reasoning over large and heterogeneous data sources Planning and executing multi-step workflows Grounding actions in real-world data Result-adaptive execution Implement core components, including: Agent logic and orchestration layers Tool interfaces and execution handlers State management, memory, and context handling Translate high-level automation designs into robust, testable implementations Integrate AI-driven workflows with existing services, data sources, and platforms Implement observability, logging, and debugging mechanisms for AI-assisted systems Participate in evaluation and iteration of prompts, workflows, and control logic Collaborate closely with security practitioners to ensure outputs are actionable and operationally relevant Contribute to engineering standards around safety, reliability, and change management Required Qualifications 9+ years of professional software engineering experience, with strong exposure ### Senior ASIC RTL Integration Engineer, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXIUI4oiiQS96O2ZETQ-CwsqXvmrJAwFa2k9ZeXarSeNEjsACxwdTMt8wl6OJaXQm9f5Vn_oGMk-NWe3aMMl_J8XA3txOEEVHZwHBKlObigM44E1Tq4SwsVS5V5AIw%3D%3D_V2&loc=IN&title=Senior+ASIC+RTL+Integration+Engineer - Excerpt: Senior ASIC RTL Integration Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering ### E&I Technician - Bunge - Location: Decatur, AL (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://jobs.bunge.com/job/Decatur-E&I-Technician-AL-35601-2678/1374790733/ - Excerpt: E&I Technician Decatur, AL Requisition Number: 44280 A Day in the Life: The Electrical & Instrumentation Technician installs repairs and removes various instruments and their component parts in an efficient manner with respect to safety, quality, and sanitation. They provide skilled mechanical and electrical/electronic support to all areas of production Position Details: Schedule to be determined. Be prepared to work a flexible, 8-, 10-, or 12-hour schedule that will include off shifts and weekends. Pay: $43.25 an hour Bunge offers a variety of benefits including health and wellness plans, retirement contribution and paid vacation/holidays. What You'll Be Doing: Install, troubleshoot and repair mechanical, hydraulic, pneumatic, automated, and electrical/electronic equipment including but not limited to PLCs, numeral controls, power supplies, drives, gauges and test equipment Conduct electrical planning, preventative maintenance, and programming for process logic control systems (PLC's) platforms, instrumentation, and human-machine interfaces (HMI) Install, repair, and calibrate electronic to pneumatic converters or pneumatic to electronic converters or a combination of both Repair electronic equipment instruments such as ultrasonic, radar, and other conventional level controls Repair electronic equipment instruments such as photo eyes, proximity controls, and associated equipment and controls Repair and calibrate temperature sensing instruments with capillary and bulb, instruments with thermocouple and ### Software Engineer (Teradyne, Singapore) - Teradyne - Location: Software Engineer (Teradyne, Singapore) (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://jobs.teradyne.com/Teradyne/job/Science-Park-Software-Engineer-%28Teradyne%2C-Singapore%29/1373009600/ - Excerpt: Software Engineer (Teradyne, Singapore) Software Engineer (Teradyne, Singapore) About Teradyne Teradyne is a leading supplier of Automatic Test Equipment (ATE) used to test complex electronics in the consumer electronics, automotive, computing, telecommunications, and aerospace and defense industries. Teradyne brings high-quality innovations in smart devices, life-saving medical equipment and data storage systems to market faster through its advanced test solutions for semiconductors and electronic systems. In 2023, Teradyne had revenue of $2.7 billion and today employs 6,500 people worldwide. The Semiconductor Test Division is the world's largest supplier of semiconductor test equipment for logic, RF, analog, power, mixed-signal, and memory technologies. The Nextest division is responsible for the Magnum family of memory test products. For more information, visit www.teradyne.com . Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are driven to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Organization & Role Nextest is looking for software engineers to join an exciting, dynamic, hardworking, engaging, and collaborative team. As an individual contribu ### Applied Senior/Staff Scientist with SAP S/4 Domain Expertise (T3/T4) (f/m/d) - SAP - Location: Region Europe | Country Germany | Internal Posting Location Garching (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://jobs.sap.com/job/Garching-bei-M%C3%BCnchen-Applied-SeniorStaff-Scientist-with-SAP-S4-Domain-Expertise-%28T3T4%29-%28fmd%29-85748/1371661933/ - Excerpt: Applied Senior/Staff Scientist with SAP S/4 Domain Expertise (T3/T4) (f/m/d) Region Europe | Country Germany | Internal Posting Location Garching We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you`ll do: As Applied Senior/Staff Scientist, you will lead the mission to evolve the SAP-RPT model family into experts of structured business data. You will tailor our foundation models to the unique complexities of real-world SAP applications, supercharging them with the deep-seated business process intuition and specialized reasoning required for the enterprise. Bridging the gap between research scientists focusing on model architecture and data experts, you will ensure our models are not just technically sound, but business-fluent. This is a hands-on role where you will directly implement the techniques that allow our models to navigate the intricacies of relational schemas and enterprise logic. This is the ideal role for a highly focused, ambitious individual with both a strong technical and coordinating background and your chance to contribute to one of the very few leading foundation models of ### Executive Support Agent, Senior Executive Services - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $128K-$188K - Posted: 2026-06-12 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckd7gLafRpuElvAWnYxgXKRW-X6Msg6tet4dd9H_aCmHsEjsACxwdTG4Zt5GA9r8N-Wv4oxOg0Yng6pTSuU0EZx-NCoxMLkdLeAac-S85wdkp7Bk_84BL46skeKu9ow%3D%3D_V2&loc=US&title=Executive+Support+Agent - Excerpt: Executive Support Agent, Senior Executive Services Mountain View, CA, USA Security is at the core of Google's design and development process: it is built into the DNA of our products. The same is true of our offices. You're an expert who shares our seriousness about security and our commitment to confidentiality. You'll collaborate with our Facilities Management team to create innovative security strategies, investigate breaches and create risk assessment plans for the future. You believe that providing effective security doesn't come at the expense of customer service - you will be our bodyguard (and our long lost pal). As an Executive Support Agent with Senior Executive Services, you are proactive, detail-oriented with operational skills and serious about security and our commitment to confidentiality. You have impeccable judgment and can quickly solve problems in a logical manner, while working independently and as a part of a team. You will provide the organizational, analytical, and physical skills necessary to ensure safety and security to support the Senior Executive Services (SES) team. Your focus area would be as a team member providing advance work, driving and physical security and logistical support to assigned clients. You would be responsible for client and staff liaison while coordinating with supporting or adjacent teams, agencies, or vendors to ensure clients security requirements are met in a timely and professional manner. You will collaborate and maintain relationships with cross-functional partners to support the SES team to provide time critical results. Additionally, you ensure quality control of all services ### Sr Quality Analysis - CAPA Mentor - Boston Scientific - Location: Valencia, CA (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://jobs.bostonscientific.com/job/Valencia-Sr-Quality-Analysis-CAPA-Mentor-CA-91355/1369124900/ - Excerpt: Sr Quality Analysis - CAPA Mentor Valencia, CA Recruiter: Sr Quality Analysis - CAPA Mentor About the role: This role provides site‑level CAPA mentorship, oversight, and approval support across the quality system. The CAPA Mentor partners with CAPA owners, project teams, and Quality leadership to ensure timely, compliant, and effective corrective and preventive actions, while driving continuous improvement and risk reduction. Your responsibilities will include: Key responsibilities include, but are not limited to, the following: Manage and oversee the CAPA portfolio, including monitoring, tracking, and reporting CAPA health, compliance, and performance metrics to Quality leadership. Serve as a CAPA Mentor by coaching and guiding cross‑functional teams through nonconforming events and the development, implementation, and verification of corrective and preventive actions. Provide subject‑matter expertise on structured problem‑solving methodologies and effective execution of the CAPA process across all phases. Partner with CAPA owners to ensure CAPA records are compliant with global and local procedures, clearly written, logically structured, and aligned with the intent of each CAPA activity, including appropriate documentation of rationale and decision‑making. Collaborate with Quality Assurance, Project Management, and functional leaders to identify systemic quality issues and drive continuous improvement initiatives. Provide CAPA status updates, milestone tracking, and risk assessments to Project Managers and stakeholders ### (Senior) Royalty Reconciliation Process & Automation Specialist - SAP - Location: Region Europe | Country Czech Republic | Internal Posting Location Prague (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://jobs.sap.com/job/Prague-5-%28Senior%29-Royalty-Reconciliation-Process-&-Automation-Specialist-158-00/1281412901/ - Excerpt: (Senior) Royalty Reconciliation Process & Automation Specialist Region Europe | Country Czech Republic | Internal Posting Location Prague We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. PURPOSE AND OBJECTIVES: We are seeking a motivated and detail-oriented (Senior) Royalty Reconciliation Process & Automation Specialist to join the team within Order-to-Invoice Revenue Assurance team. This role covers owning the design, standardization, and automation of reconciliation processes, while retaining a strong understanding of royalty reconciliation execution and underlying functions. The successful candidate will maintain deep end-to-end understanding of royalty agreements, data flows, and controls by managing a limited portfolio of reconciliation cases, and will leverage that expertise to develop scalable templates, process logic, and automation solutions using advanced Excel (macros/VBA) and SAP GUI automation. This role is critical to improving efficiency, consistency, and auditability across royalty reconciliation activities. WHAT YOU'LL DO: Execute end-to-end royalty reconciliations for a subset of cases to maintain deep process, data, and agreement-level expertise. D ### Technical Program Manager III, Tooling and Automation, Cloud Networking - Google - Location: Austin, TX, USA; +1 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka_twYjmBuUUKwE3HjQ2ZBzMen6vXew0kX1fLeo6iMYwEjsACxwdTGbvevwHCb0PXi2WFLwtorOCLqWPVPLCruTc0qqmyBxM7p9KuDKLUjT_WIkf-u8VRL6PPXAn5A%3D%3D_V2&loc=US&title=Technical+Program+Manager+III - Excerpt: Technical Program Manager III, Tooling and Automation, Cloud Networking Austin, TX, USA; +1 more A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. As a Technical Program Manager, you are responsible for the functional success of the systems that power our data center network rollouts. You act as the critical link between the Physical Delivery team (who build the network) and the software engineer/SRE teams (who build the tools). Your goal is to ensure that our delivery ecosystem covering capacity tracking, workflow management, and fiber design is technically sound, operationally efficient, and integrated with our global inventory. The role extends beyond oversight, you will architect the technical logic, validation rules, and automated workflows, and be directly involved in the direct coding and co-development with engineering teams to ensure precise implementation and delivery of new features. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next ### Senior PCB Design Engineer(Nextest, Philippines:Cebu) - Teradyne - Location: Senior PCB Design Engineer(Nextest, Philippines:Cebu) (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://jobs.teradyne.com/Teradyne/job/Basak%2C-Lapu-Lapu-City-Senior-PCB-Design-Engineer%28Nextest%2C-PhilippinesCebu%29/1386002300/ - Excerpt: Senior PCB Design Engineer(Nextest, Philippines:Cebu) Senior PCB Design Engineer(Nextest, Philippines:Cebu) Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview The Teradyne NBU PCB Design Engineering team is seeking a highly motivated, energetic, and technically driven Senior PCB Design Engineer to focus on the development of PCB designs for products within the division. This role operates in a dynamic and collaborative multi‑site development environment, working closely with cross‑functional engineering teams from concept through manufacturing release. Role Overview and Duties: Create schematics based on customer‑defined and system‑level specifications Develop component logical symbols and PCB footprints Set up Constraint Manager electrical, physical, and DFM design rules Perform routing assessments and project feasibility studies Define assembly specifications and documentation Create assembly and test packages for manufacturing Execute complete PCB design activities from data entry through fabrication file generation Generate cost estimates to enable marketing quotations Attend product developmen ### Electrical + Instrument Technician - Bunge - Location: Council Bluffs, IA (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://jobs.bunge.com/job/Council-Bluffs-Electrical-%2B-Instrument-Technician-IA-51503-6593/1292926601/ - Excerpt: Electrical + Instrument Technician Council Bluffs, IA Requisition Number: 43812 A Day in the Life: The Electrical & Instrumentation Technician is responsible for maintaining plant wide electrical troubleshooting and repair. Position Details: Monday through Friday day shift Pay: $34.67 an hour What You'll Be Doing: Maintain all automation throughout the facility (electric circuits of 480VAC or less) Troubleshoot and repair high voltage lighting, variable frequency drive (VFD) and alternating current / direct current (AC/DC) systems Troubleshoot and repair Programmable Logix Control (PLC) (Allen-Bradley) systems like SLC 500, MicroLogix, CompactLogix, PLC 5s, 5000 Logix Controllers and Panel Views Check output on DC controllers and replace printed circuit boards when needed Troubleshoot, locate, test, identify, or diagnose electrical malfunction and then adjust, repair, or replace Follow, interpret, and read blueprints or schematics Calibrate and/or troubleshoot process instrumentation Assigning IP addresses to new equipment Inspect for conformity to industry standards or specifications Rebuild, repair, and replace damaged, defective, or worn parts Maintain a clean and orderly work area and remove material and equipment from job site Troubleshoot and repair AC motor starter circuits Minimum Qualifications: Associates degree in electronics or 3-5 years of equivalent experience is required Ability to read and understand ladder logic Experience with networking systems such as Control Net, Ethernet, and Data Highway Familiarity with m ### Technical Program Manager II, Tooling and Automation, Cloud Networking - Google - Location: Addison, TX, USA; +3 more (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWDqg28tDXMA-k2K0PjB46g33soucvSzwjl7QxSM0VBZEjsACxwdTMwX_Nv8aXdU-ZGi57ICD-sSoWSjpOdf6MTHucNsR5miDUqZu20s8igO_BzWCzcEXBFdD4bR3Q%3D%3D_V2&loc=US&title=Technical+Program+Manager+II - Excerpt: Technical Program Manager II, Tooling and Automation, Cloud Networking Addison, TX, USA; +3 more A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. As a Technical Program Manager, you are responsible for the functional success of the systems that power our data center network rollouts. You act as the critical link between the Physical Delivery team (who build the network) and the software engineer/SRE teams (who build the tools). Your goal is to ensure that our delivery ecosystem covering capacity tracking, workflow management, and fiber design is technically sound, operationally efficient, and integrated with our global inventory. The role extends beyond oversight, you will architect the technical logic, validation rules, and automated workflows, and be directly involved in the direct coding and co-development with engineering teams to ensure precise implementation and delivery of new features. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next ### Principal Consultant - OpenText Support - Bunge - Location: Bhurai, IN (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://jobs.bunge.com/job/Bhurai-In-Principal-Consultant-OpenText-Support-PB-160059/1401078533/ - Excerpt: Principal Consultant - OpenText Support Bhurai, IN Requisition Number: 45962 Job Description Business Title Principal Consultant - OpenText Support Global Job Title Sr Anl Global Biz Operations Global Function Business Technology Global Department BT Global Business Operations Organizational Level 7 Reporting to Sameer Kulshreshth Size of team reporting in and type This is a individual contributor role. Role Purpose Statement Purpose of this role is to work on various rollouts, projects, and process improvement initiatives for OpenText VIM Main Accountabilities • Work on Rollouts, implementation projects. • Lead VIM team for minor projects like upgrade/migration etc. • Provide a deep understanding of the invoice management business logic, processes, organization and culture. • Identify opportunities for business process improvement; follow up implementation of these improvements into system configuration, considering their matching to the capabilities of SAP. • Evaluate the Reporting/ KP needs from business and improve existing ones and define new requirements. • Liaison with SAP for issue identified in core solution. Knowledge and Skills Behavior Use knowledge of Bunge's business, structure and strategy to develop innovative solutions to improve results or eliminate problems. Build partnerships, appropriately influence to gain commitment, foster talent and coach others to grow in current or future roles.. Drive results through high standards, focus on key priorities, organization, and preparing others for change. Technical • ### UX Writer and Content Designer, Google Ads - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $120K-$172K - Posted: 2026-06-04 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckbNiLGRVuagPq99ZTZtEcWSASW6Z7Dc4Umf3lJ3Nt-xeEjsACxwdTPFQWPlEtTujJ6Ys4fsNLpLhx7mBORMV9zIhpRCQAR26ylFF4bL7o5tKOwAhhyX05rBS_zvW6A%3D%3D_V2&loc=US&title=UX+Writer+and+Content+Designer - Excerpt: UX Writer and Content Designer, Google Ads Mountain View, CA, USA As a UX writer, you are an advocate for Google design, shaping product experiences by creating useful, meaningful text that helps users complete tasks. You help set the vision for content and drive cohesive product narratives across multiple platforms and touch points. As a stellar writer, your portfolio of work demonstrates content that simplifies and beautifies the overall user experience. You work with people in a variety of UX design-related jobs including researchers, product managers, engineers, marketing and customer operations. Collaborating with each, you strive to establish cohesive language and a unified voice across products and platforms. You regularly use empathy, logic and data to inform content choices and recommendations that include the right words and sometimes complementary data and images. Buying, Analytics and Measurement (BAM) UX is a group of impassioned designers, researchers and writers, defining the user experience of the Google Marketing Platform and critical pieces of the broader Google advertising ecosystem. We are looking for an enthusiastic UX writer and content designer, who is both a strategic product thinker and a strong writer, to work on advertiser safety within the Google Ads product. This is a unique team that solves deep product and business problems within Google Ads. Google Ads is helping power the open internet with the best technology that connects and creates value for people, publishers, advertisers, and Google. We're made up of multiple teams, building Google's Advertising products including search, display, shopping, travel ### Executive, Shipping - Bunge - Location: Pasir Gudang (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://jobs.bunge.com/job/Pasir-Gudang-Executive%2C-Shipping-01-81700/1402191433/ - Excerpt: Executive, Shipping Pasir Gudang Requisition Number: 45998 SUMMARY DESCRIPTION Executive on the booking to shipping line or agent base on shipment schedule and meeting customer expectation of ETS & ETA request rate from carriers upon request Coordinate Import and Export freight bookings including Air / Sea (FCL/LCL) / Cross Border Trucking / Inland Clearance & Trucking. Check and Verify the freight invoices. DETAILED DESCRIPTION Update the shipment transit times, delay, advance internally Ensure shipping team proceed booking with agent/ carriers and obtained the booking confirmation on time. Enter the shipment data enter into SAP and logistics systems. Update the detailed and accurate logistics data for daily, weekly, and quarterly reports. Co-coordinate with various other departments as needed to create comprehensive schedules for shipping in SNOP meeting book with selected carriers with right time, right cost and customer requirement such as free days REQUIREMENT Degree and above in related field. More than 2 years' experience on supply chain / documentation Supply chain knowledge Analytical skills Time management skills Capable, enthusiastic and strong communication skills Fluent in English speaking & writing (Arabic or Chinese will be advantage) Strong Analytical & logical thinking Problem solving skills At Bunge (NYSE: BG), our purpose is to connect farmers to consumers to deliver essential food, feed and fuel to the world. As a premier agribusiness solutions provider, our team of ~34,000 dedicated empl ### Senior Process Enablement Analyst, APAC Supply Chain - Boston Scientific - Location: Penang (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://jobs.bostonscientific.com/job/Penang-Senior-Process-Enablement-Analyst%2C-APAC-Supply-Chain/1362195300/ - Excerpt: Senior Process Enablement Analyst, APAC Supply Chain Penang Purpose Statement The Senior Process Enablement Analyst is responsible for end-to-end ownership of system requirement definition and delivery for assigned product areas across regional digital platforms and systems. This role drives translation of business processes into scalable system solutions, ensures delivery quality across design, build, testing, and rollout, and acts as the primary owner for solution outcomes across countries. Key Responsibilities Own end-to-end solution behavior for assigned regional business processes, ensuring alignment with operational priorities and harmonization goals. Translate regional business processes into scalable system workflows, business rules, validations, integrations, and operational controls. Define and prioritize the product backlog, balancing business value, country requirements, technical feasibility, and delivery timelines. Partner with Process Excellence Analysts, IT teams, and vendors to ensure operational processes are accurately reflected in system behavior and user workflows. Drive clarity on master data dependencies, transactional flows, operational controls, and integration behavior across end-to-end processes. Review and approve Functional Requirement Specifications (FRS), UI/UX designs, and solution proposals, ensuring alignment with business intent and long-term system sustainability. Drive clarity on workflow logic, master data dependencies, integrations, and end-to-end operational behavior. Lead User Acceptance Testin ### Silicon Senior uArch/RTL Engineer, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckY0pPyYYY6CTrUrB1t9oeR3UU0YP0HDQkOcu83kukfF7EjsACxwdTM1wlXYhgwHvyjKNX6Ryo-e6K3C1DC8Bk4imo_YM_0piTb2VhYmMZDIKWQykkP1cLyc93T9Qdg%3D%3D_V2&loc=IN&title=Silicon+Senior+uArch/RTL+Engineer - Excerpt: Silicon Senior uArch/RTL Engineer, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing SoCs used to accelerate Machine Learning (ML) computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Own microarchitecture and ### Senior UX Content Designer, Search - Google - Location: New York, NY, USA; +1 more (unspecified) - Salary: $144K-$209K - Posted: 2026-06-04 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdK4f9XAnLndtq5UVT7Szsq9WlIWQZtd_oHqmyXr6dQ6EjsACxwdTIgMCzaAONIjHlW9B3Nty5gIRUDDJOUCXDrQcFsW_PVNDUNad_Z5f53-IfcSIeGZkDWOkDDBMQ%3D%3D_V2&loc=US&title=Senior+UX+Content+Designer - Excerpt: Senior UX Content Designer, Search New York, NY, USA; +1 more As a UX writer, you are an advocate for Google design, shaping product experiences by creating useful, meaningful text that helps users complete tasks. You help set the vision for content and drive cohesive product narratives across multiple platforms and touch points. As a stellar writer, your portfolio of work demonstrates content that simplifies and beautifies the overall user experience. You work with people in a variety of UX design-related jobs including researchers, product managers, engineers, marketing and customer operations. Collaborating with each, you strive to establish cohesive language and a unified voice across products and platforms. You regularly use empathy, logic and data to inform content choices and recommendations that include the right words and sometimes complementary data and images. In this role, you will drive model behavior design efforts to shape the future of Google's generative AI experiences. You will create conversational response strategies that prioritize helpfulness, using natural language to build meaningful interactions within our AI-powered search environment. In Google Search, we're reimagining what it means to search for information - any way and anywhere. To do that, we need to solve complex engineering challenges and expand our infrastructure, while maintaining a universally accessible and useful experience that people around the world rely on. In joining the Search team, you'll have an opportunity to make an impact on billions of people globally. Individual pay is determined by factors including job-related skills, experience, and relevant education or ### TPU SoC Design Engineer, Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckY_U-kqH5fY5WDoC_zN7EpQpkng0kmrsSnmbElhgZ9nREjsACxwdTJec7wfOfBOAkaS_jHKFoS4YnWS2QP9z1jm0M62KdZ2akIAPyr67NQ4fAVz8K-BdBbsgqirhdA%3D%3D_V2&loc=US&title=TPU+SoC+Design+Engineer - Excerpt: TPU SoC Design Engineer, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will join a team working on SoC-level RTL design for data center accelerators. You will work on top-level RTL, architecture, design and implementation of global communication busses, and integration of complex ASIC designs, as this is a highly cross-functional and central role that will require interactions with numerous ASIC development teams. You will own deliverables to the cross-functional teams (i.e. Physical Design, Verification, Validation, Firmware...) at various project milestones. You will also be directly involved in defining and creating methodologies that enable a highly efficient design environment for all ASIC engineers. As a Soc Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. This position offers the opportunity to address challenging technical problems at the forefront of AI ### Lead Analyst, Supplier Data Management – AMER ( Spanish ) - Oracle - Location: BENGALURU, KARNATAKA, India, IN (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 14 weeks (not source-backed) - Non-birth-parent leave: 14 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://careers.oracle.com/en/sites/jobsearch/job/334066/ - Excerpt: Lead Analyst, Supplier Data Management – AMER ( Spanish ) BENGALURU, KARNATAKA, India, IN Key Responsibilities/Job Requirements: Reviewing approved Supplier add request and create supplier record in accordance with Oracle's Global Purchasing/Finance policy. Action on notifications for Supplier profile change request Analyze and resolve invoices on bank detail invalid and Installment holds Assist requesters in Oracle Procurement Cloud Assist supplier on Supplier portal issues Collaborate with the strategic team, requesters and support processes for end to end solutions Identify, propose and initiate implementation of process efficiencies/improvements. Provide first level functional support for system and process issues. Assist in training of new analyst and end users Act as a Buddy to new hires and end users Other duties as assigned Additional Details - Proficiency in Spanish language is must. Excellent English written and verbal communication skills. Strong computer skills including to MS Word, Excel, Power Point Presentation, e-Mail, etc. Detailed oriented with the ability to follow desktop procedures and work instructions closely. A customer driven approach and good customer management skills Ability to identify problems and apply creative solutions Ability to multi-task, be highly organized, and work independently Ability to work independently and under pressure. Logical thought process with the ability to follow guidelines and documented procedures. Good analytical skills. Career Level - IC2 ### ASIC Digital Design Engineer II, Silicon Engineering - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcHsrgwWN7Y2d6pNVVICVe2b0jfdsrwKnS2Duw_RfL4yEjsACxwdTM8PdhjKksREzrwUS05bAsHYIsnAM0j18suBmBOP_jXW3Qr7CK8ogRakyjXMqLc743ndvIUFPg%3D%3D_V2&loc=IN&title=ASIC+Digital+Design+Engineer+II - Excerpt: ASIC Digital Design Engineer II, Silicon Engineering Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will be a part of the team which designs the Tensor Processing Unit (TPU) core and sub-system. The TPU core is the heart of Google's Tensor SoC. You will be working through all phases of design and implementation. You will be working with Architects to come-up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/proto-typing experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical design (PD) team to take the design through PD cycle and eventual tape-out. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Use simulation/emulation/power analysis tools and techniques to ### Senior UX Writer and Content Designer, Chrome - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $144K-$209K - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXrSqHqj8erzXSK1IsEW6egxZoGCPQZafQEo7oUOTRRfEjsACxwdTC5RtT7EtRCRIMb9ryyBQLsyus8jaSc853HhFVStXHSNK9yGL4VNU1vb_vk7HPaatC83_wLxSA%3D%3D_V2&loc=US&title=Senior+UX+Writer+and+Content+Designer - Excerpt: Senior UX Writer and Content Designer, Chrome Mountain View, CA, USA As a UX writer, you are an advocate for Google design, shaping product experiences by creating useful, meaningful text that helps users complete tasks. You help set the vision for content and drive cohesive product narratives across multiple platforms and touch points. As a stellar writer, your portfolio of work demonstrates content that simplifies and beautifies the overall user experience. You work with people in a variety of UX design-related jobs including researchers, product managers, engineers, marketing and customer operations. Collaborating with each, you strive to establish cohesive language and a unified voice across products and platforms. You regularly use empathy, logic and data to inform content choices and recommendations that include the right words and sometimes complementary data and images. In this role, you will partner with fellow designers, product managers, and engineers to ideate, iterate, and deliver a cohesive content experience across the various AI Mode features within Chrome. Chrome is dedicated to building a better, more open web. We're focused on making a better browser (on both desktop and mobile) to help users take advantage of all the web has to offer in a safe and secure way.Chrome is available across all major platforms - iOS, Android, Windows, Mac, Linux and Chrome OS. We also built Chrome as an open source project so the entire web ecosystem could benefit from the latest innovations in speed, simplicity and security. Individual pay is determined by factors including job-related ### Silicon Micro-architecture and RTL Lead, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-04-28 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXiAZPQspEkwABvZ6BujZJltNS3E2m7WTxg4dUcXd9YtEjsACxwdTOYq9JSIqkGURs04FP8E5uhd97AQRZrIk6iLNW1H1k9NQg2lg39195nHmwKBIQxKVHgGCZBpRA%3D%3D_V2&loc=IN&title=Silicon+Micro-architecture+and+RTL+Lead - Excerpt: Silicon Micro-architecture and RTL Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to ### Data Center Facilities Engineer, Controls (Japanese) - Google - Location: Inzai, Chiba, Japan (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSlJRisa3MXHbRxfLDzWD-micnshPL0nAIHyPlXWCKZfEjsACxwdTEaF4tToTcUivfCSUCKFJiIIFxGMjcMM5ojd3Uhs2wDfOL1kBZOmdMqmGph4WP-9c6R35w7Rhw%3D%3D_V2&loc=JP&title=Data+Center+Facilities+Engineer - Excerpt: Data Center Facilities Engineer, Controls (Japanese) Inzai, Chiba, Japan The Data Center team designs and operates some of the most sophisticated electrical engineering, mechanical engineering and HVAC systems in the world. Facilities Technicians at Google data centers operate, monitor and support physical facilities conditions. Some of these duties will include heating and cooling of air and water, power supply, generators, UPS systems, electrical distribution and control and monitoring systems. You regularly help inspect, maintain and repair various data center systems such as piping and non-critical electrical or mechanical system components). You provide daily assistance to senior technicians as you read blueprints/schematics, conduct tours of systems and assess their working order. As an advocate for best practices, you develop creative approaches to reducing operational costs while improving overall data center efficiency. You ensure that environmental and safety standards are consistently met, identifying problems and making repairs quickly. In emergency situations or abnormal conditions, you manage data center performance issues and outages to minimize the recovery time from failures. The Data Center team designs and operates some of the most sophisticated electrical and HVAC systems in the world. We are an upbeat, creative, team-oriented group of engineers committed to building and operating powerful data centers. Inspect, maintain, and repair various data center systems such as servers, network equipment, Programmable Logic Controllers (PLCs), system administration, access control, alarm investigation, and Supervisory Control and Data Acquisition (SCADA) management. Provide daily assistance to technicians as you read blueprints/schematics/ladder logic/sequence of operations, conduct tours of systems, ### Silicon DFT Engineer, Cloud Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU2Jrh8H8FnUYwuT8lOXm8LHJC_JHTJUe5cb4dEPrm4NEjoACxwdTJssuQ62Nc90UTxsz3bG4GOGEIWpoxFZCgWVAjPmmOhB6S-zuT5KpR2t_1JQ6EEybSB6IVJb_V2&loc=IN&title=Silicon+DFT+Engineer - Excerpt: Silicon DFT Engineer, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, ### Data Center Controls Engineer, Global Data Centers - Google - Location: New York, NY, USA; +4 more (unspecified) - Salary: $144K-$209K - Posted: 2026-06-04 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdcVjDY1YX2mWLg1JCNodxIAj__sJkLnC5FQj3crV0q1EjsACxwdTMqyUmsa9_UPIS9Ayzf_fsPEw4JjImNKkV-iZmprUI9ARv2c7pmHMa8yNZ_4KjTOBIY0-qWkQQ%3D%3D_V2&loc=US&title=Data+Center+Controls+Engineer - Excerpt: Data Center Controls Engineer, Global Data Centers New York, NY, USA; +4 more Our thirst for technology is a part of everything we do. The Data Center Engineering team takes the physical design of our data centers into the future. Our lab mirrors a research and development department -- cutting-edge strategies are born, tested and tested again. Along with a team of great minds, you take on complex topics like how we use power or how to run state-of-the-art, environmentally-friendly facilities. You're a visionary who optimizes for efficiencies and never stops seeking improvements -- even small changes that can make a huge impact. You generate ideas, communicate recommendations to senior-level executives and drive implementation alongside facilities technicians. With your technical expertise, you ensure compliance with codes and standards, develop infrastructure improvements and serve as an expert in your specialty (e.g., cooling, electrical). Google is looking for a Controls or Systems Engineer with a mastery of Building Management Systems (BMS), Electrical Power Monitoring System (EPMS) and Industrial Control Systems (ICS) to execute and deliver the supply of third-party data center projects. As the primary on-site technical authority for automation, you will ensure that the "brains" of the facility-the integration of mechanical, electrical, and cooling systems-are installed and networked to perfection. You will serve as the Lead Technical Point of Contact (POC) for all BMS, EPMS, and PLC-related engineering questions during the construction phase, ensuring that the physical installation of sensors, controllers, and network architecture aligns with the logical design intent, enabling ### Tensor SOC Performance Design Verification Engineer - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYimJe0yWahAsUhEm1inLXqAEFfUq5w2jNInfDOdzV1MEjsACxwdTHo_glOJ9K36CEG8Hg_zzRA0wlA6jG6aHAkuZkDjBxu1eG3ZmqvTsRbYuopjhou5g3vpHTsCiw%3D%3D_V2&loc=IN&title=Tensor+SOC+Performance+Design+Verification+Engineer - Excerpt: Tensor SOC Performance Design Verification Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop simulators and architectural models of Google's Tensor SOC. Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements. Participate in architectural and design evaluation of Tensor SOC features studies. Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements. Communicate analysis results qualitatively and quantitatively. Minimum qualifications: Master's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience. 4 years of experience in the SOC design/verification. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level. Experience in mobile SOC performance model development, performance analysis, and workload characterization. Preferred qualifications: Experience in CPU microarchitecture innovation. Knowledge of system software components, such as Linux, drivers, and runtime. Knowledge of performance analysis tools. Knowledge ### Account Specialist - East Anglia (Dermatology) - AbbVie Inc. - Location: Remote | West Suffolk District, ENGLAND, United Kingdom (remote) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 12 weeks (not source-backed) - Non-birth-parent leave: 12 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://jobs.smartrecruiters.com/AbbVie/3743990013442236-account-specialist-east-anglia-dermatology- - Excerpt: Account Specialist - East Anglia (Dermatology) Remote | West Suffolk District, ENGLAND, United Kingdom Company Description: About AbbVie AbbVie's mission is to discover and deliver innovative medicines and solutions that solve serious health issues today and address the medical challenges of tomorrow. We strive to have a remarkable impact on people's lives across several key therapeutic areas including immunology, oncology and neuroscience - and products and services in our Allergan Aesthetics portfolio. For more information about AbbVie, please visit us at www.abbvie.com . Follow @abbvie on LinkedIn, Facebook , Instagram , X and YouTube. Job Description: Be the direct contact for key stakeholders to communicate the value proposition; be the main executor of the infield brand strategy. Develop customer relationships whilst maximising opportunities based on strong account plans. Customer selling and relationship management; Drive Sales - Own the customer engagement for target HCPs across channels, to reflect customer preferences, leveraging available content and multiple engagement channels Develops SMART pre call objectives in line with territory plans and aligned to brand strategy. Effectively handles objections or concerns. Consistently gains a logical, reasonable call to action/close on every sales call. Educates medical providers, other relevant decision makers and affiliated healthcare professionals. Identifies & develops disease state experts building advocacy aligned to territory plan. Continuously strive to gain market intelligence; Organise and manage stakeholder meetings Differentiates AbbVie's value proposition to physicians or other stakeholders assigned from any competitors Strong communication skills, ability to flex style based on customer insights Clinical and Market Knowledge ### Senior Silicon Physical Design Engineer - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2025-12-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcEmKw3OqCFQjNCd4HdZzERM6VJ1TALxcKuWEl9dOcK-EjsAvkGZm1vEX_yavFl_ZfZQwpnAYOQ9dnoNy3uz_4XMKzM4htTphNwR5OQcsn_0LABreM6jIaV9Q-VSQQ%3D%3D_V2&loc=IL&title=Senior+Silicon+Physical+Design+Engineer - Excerpt: Senior Silicon Physical Design Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements. Collaborate with cross-functional teams to debug failures or performance shortfalls and ### Senior Software Engineer, Generative AI, Core ML - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $174K-$253K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRQgf4B-j-aHJmv9ZUr5uI2yg0_6HyZdj-oGpEvfb1SQEjsACxwdTJsBwn9PgtkQV2tn2vi0rhNd28yGkGBRZxhxSl5C1j9iyQ7qqb8mPeMhx0PJ9MUW7sPXX0eVUg%3D%3D_V2&loc=US&title=Senior+Software+Engineer - Excerpt: Senior Software Engineer, Generative AI, Core ML Mountain View, CA, USA Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. As an engineer for these initiatives, you will transform the development of AI agents from an artisanal craft into an engineering discipline to achieve high-quality, reliability with multi-folds efficiency gains across Google. You will architect and productionize horizontal infrastructure, including generalized Knowledge Store libraries and self-reflection modules, to enable agents to learn and improve autonomously with every run. You will apply core design principles, lead deep audits of high-impact agents to extract deterministic logic from monolithic prompts into efficient, code-based workflows. You will scale automated prompt optimization and trace scanning tools to systematically eliminate waste and solve the "GenAI engineering gap" ### Staff Software Engineer, Cloud Security - Google - Location: Sunnyvale, CA, USA; +1 more (unspecified) - Salary: $207K-$301K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQ2XwL6klBpqpR-RDRHU7Je5APS9THnCPHsaqKBxwaQYEjoACxwdTOWSn640SgvU0EJTqXUKbAGvINq94to2Zv-OmqsQmbQWkp6QBYfApgDNbwKOI9rPa8MH5DkL_V2&loc=US&title=Staff+Software+Engineer - Excerpt: Staff Software Engineer, Cloud Security Sunnyvale, CA, USA; +1 more Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Regional Isolation aims to reduce the blast radius of security/control plane compromise, via any combination of logical or physical attacks, by guarding against propagation of compromise from one security region to another. Our mission is to eliminate global-by-default authorization patterns at Google, and provide controls for new authorization patterns in a centralized, safe and easy way. The team designs, develops, and deploys fundamental security infrastructure, primitives, and APIs for authenticating the physical origin of a connection. Furthermore, we provide insights and tooling to help us gauge our adoption, risks and success metrics. Google Cloud accelerates every organization's ability to digitally transform its ### Security Analyst, Threat Intelligence Operations (English) - Google - Location: Singapore (unspecified) - Salary: Not disclosed - Posted: 2026-05-28 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUglJzX4YdnRahZy66tJMpJorvMnurXUt92H5XKdZ_H5EjsACxwdTGuiMCCHUvAcZ9Orl-2Db3HCWEcEzEte5iAz7admuDsCBGu5ywCbX3nGbUhEsMTyl_I5E2PTcQ%3D%3D_V2&loc=SG&title=Security+Analyst - Excerpt: Security Analyst, Threat Intelligence Operations (English) Singapore In this role, you will be a key member of the newly established Threat Intelligence Operations (TIO) function. Your primary mission is to contextualize threat intelligence specifically for Alphabet. You will be responsible for providing actionable intelligence to proactively identify coverage gaps and strengthen the overall security posture of the organization. The Core team builds the technical foundation behind Google's flagship products. We are owners and advocates for the underlying design elements, developer platforms, product components, and infrastructure at Google. These are the essential building blocks for excellent, safe, and coherent experiences for our users and drive the pace of innovation for every developer. We look across Google's products to build central solutions, break down technical barriers and strengthen existing systems. As the Core team, we have a mandate and a unique opportunity to impact important technical decisions across the company. Combine public reporting with internal security data from sources such as threat scenarios consolidated in optimus and enterprise security intelligence . Evaluate known threats against current defensive and protective capabilities to identify coverage gaps, leveraging code reviews to assess the efficacy of technical defenses and detection logic. Conduct limited, focused manual hunting to ensure intelligence remains grounded in operational reality. Produce high-quality threat assessments to get threat scenarios integrated into threat catalogue and engineering roadmaps. Minimum qualifications: Bachelor's degree or equivalent practical experience. 2 years of experience in cyber security, threat intelligence, or threat analysis. Experience in intelligence aggregation, evaluating threat coverage ### DFT Engineer III, Cloud Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcTfj3r4d3SkBW4h86DXRjZga6p2DwbnkxUTHie32BD9EjsACxwdTND6-8pa1tS3dqGKUBWQom-0r0U2PctMGdcj18UuNKteTtI0A02BXgbolKcmd02lWWD9bAV1cw%3D%3D_V2&loc=IN&title=DFT+Engineer+III - Excerpt: DFT Engineer III, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, ### Physical Designer Engineer, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2025-12-15 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTjuPS0bNVqiOcmm9XLK5b_cjaMtqVx38-yqsSFVWvqTEjsAvkGZm4qfFl5OGlQQ3f_F9wFHbZoabYM75WVlDohL6IYuq2K4zE9TdwKkCTJXy6dKUtSwTws8S9rDBA%3D%3D_V2&loc=IL&title=Physical+Designer+Engineer - Excerpt: Physical Designer Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Drive to the closure of timing and power consumption of ### DFT Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckbHGgLSiu4Qw0Ctr5P48kdwR9d8Dmv09N_AsBULxBn6uEjsACxwdTPRUsrC2OBEfu463es0I3b-BPXtac0lEf6QAbqcNIDKE9b4YdhOFujhyQ07I2s7PxuTRj3IRcA%3D%3D_V2&loc=US&title=DFT+Engineer - Excerpt: DFT Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital or mixed-signal chips or IPs. You will define DFT architecture, and create DFT flows for complex next generation SoCs in partnership with the Design and Physical Design teams. You will also be responsible for design verification of test logic, test pattern generation and debugging and test coverage issues. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From ### Accounting Analyst - Salesforce - Location: Brazil - Sao Paulo (unspecified) - Salary: Not disclosed - Posted: 2026-05-11 - Parental leave: 26 weeks (not source-backed) - Non-birth-parent leave: 12 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://careers.salesforce.com/en/jobs/jr341908/accounting-analyst/ - Excerpt: Accounting Analyst Brazil - Sao Paulo We are seeking an Accounting Analyst to support our financial operations in Brazil. You will be responsible for the day-to-day execution of accounting activities, direct and indirect tax calculations, and ensuring that our local records align with corporate US GAAP standards. This role requires a professional who is comfortable working with external accounting partners and is eager to use technology to streamline financial processes. Key Responsibilities Tax Support & Execution: Review data for Direct Taxes (IRPJ/CSLL) and Indirect Taxes (ISS, PIS/COFINS). Work closely with our external accounting firm to ensure all tax filings are accurate and submitted on time. Accounting Operations: Process Manual Journal Entries and perform monthly Account Reconciliations for the Brazil entity. Ensure all documentation meets local and Sox audit standards. GAAP Coordination: Support the review of monthly results in IFRS/BRGAAP and assist in preparing the necessary adjustments for US GAAP reporting. Process Automation: Actively use Tableau and other digital tools to automate manual reports, reconciliations, and data validation tasks. Corporate Communication: Maintain daily communication in English with the global corporate team to explain local transactions and ensure alignment with global policies. Required Qualifications Experience: Previous experience in Accounting or Tax roles, preferably within a multinational company or a "Big 4" accounting firm. Technical Knowledge: Solid understanding of Brazilian tax logic and basic IFRS/US GAAP concepts. Technology Skills: Advanced Excel; experience or strong interest in learning Tableau for data automation. Languages: Advanced English (must be able to participate in meetings and write ### Senior Software Engineer - Google - Location: New York, NY, USA (hybrid) - Salary: $190K-$252K - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVFM6ydLyZzwphh29svHCql7snOCu2NbX_4jXb33tMD4EjsACxwdTMAqdJOwguu6WnIE1zlMaxb0p5U846rT_yZHYUXrLmdRCx31jBwhv6SrDepL2cyNTs3LE_ZFsA%3D%3D_V2&loc=US&title=Senior+Software+Engineer - Excerpt: Senior Software Engineer New York, NY, USA The US base salary range for this full-time position is $189,600 - $252,000 + 15% bonus target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google . Position reports to the Google New York, NY office & may allow for a hybrid schedule as per Google policy. Artificial intelligence will be one of humanity's most transformative inventions. At Google DeepMind, we are a pioneering AI lab with exceptional interdisciplinary teams focused on advancing AI development to solve complex global challenges and accelerate high-quality product innovation for billions of users. We use our technologies for widespread public benefit and scientific discovery, ensuring safety and ethics are always our highest priority. We are pushing the boundaries across multiple domains. Our global teams offer diverse learning opportunities and varied career pathways for those driven to achieve exceptional results through collective effort. Build and enhance serving solutions for Gemini models, tailoring configurations to meet diverse client needs and testing for optimal performance. Develop new infrastructure to support advanced capabilities, such as large-scale streaming and specialized audio logic within the orchestration framework. Guarantee the quality of Gemini models in production by triaging system issues, debugging code, and implementing robust monitoring systems. Collaborate with peers and stakeholders through design and code reviews to establish and maintain best practices in software development. Drive the short-term technical vision ### AI and Knowledge Strategist - Google - Location: Hyderabad, Telangana, India; +2 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaeFClJDxBfnXvV53IGVV-864wQc7IVQg1uaRTQELVfzEjsACxwdTHOLHLLBvteIlXrF11AgG56vxTe17EOIolGZEvKc7QoSkY4Hqq0HRkOfVqe6Ez66nChM0Wn4KQ%3D%3D_V2&loc=IN&title=AI+and+Knowledge+Strategist - Excerpt: AI and Knowledge Strategist Hyderabad, Telangana, India; +2 more Google Ads is helping power the open internet with the best technology that connects and creates value for people, publishers, advertisers, and Google. We're made up of multiple teams, building Google's Advertising products including search, display, shopping, travel and video advertising, as well as analytics. Our teams create trusted experiences between people and businesses with useful ads. We help grow businesses of all sizes from small businesses, to large brands, to YouTube creators, with effective advertiser tools that deliver measurable results. We also enable Google to engage with customers at scale. Own the content strategy within a specific product area, aligning content development with product roadmaps and prioritizing launches. Turn business goals into content solutions. Drive the success of AI-powered solutions by mapping user intent to specific content solutions. You will translate business requirements into precise AI instructions (prompts) and monitor model behavior to ensure responses are grounded in fact and aligned with Ads product logic. Develop and refresh high-quality content solutions (text, video, interactive AI) for top user issues and customer journeys within your priority product areas. Engage with cross-functional forums (Product Circles, CoE, etc.) to integrate content strategy with broader product-specific initiatives. Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience with the Google Ads ecosystem and its products. Experience using AI-powered tools for content creation. Preferred qualifications: Experience integrating content strategy with product and engineering roadmaps, with the ability to influence others and to communicate ### Senior Security Analyst, Threat Intelligence Operations (English) - Google - Location: Singapore (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckeWO_tQ0X8Y_LvvOHC5JXLIyyU1O4MaTQ4cv7IAWlNDlEjsACxwdTIEolWSJsEGEeMDTtyYdarizs8TpLM5qYCrCZatS9OIM3gGBLaPlJ9_yGAbmCq5-8DOPRHmjeA%3D%3D_V2&loc=SG&title=Senior+Security+Analyst - Excerpt: Senior Security Analyst, Threat Intelligence Operations (English) Singapore You will be a key member of the newly established Threat Intelligence Operations (TIO) function. You will contextualize threat intelligence specifically for Alphabet. You will be responsible for providing actionable intelligence to proactively identify coverage gaps and strengthen the overall security posture of the organization.The Core team builds the technical foundation behind Google's flagship products. We are owners and advocates for the underlying design elements, developer platforms, product components, and infrastructure at Google. These are the essential building blocks for excellent, safe, and coherent experiences for our users and drive the pace of innovation for every developer. We look across Google's products to build central solutions, break down technical barriers and strengthen existing systems. As the Core team, we have a mandate and a unique opportunity to impact important technical decisions across the company. Combine public reporting with internal security data from sources such as threat scenarios consolidated in Optimus and Enterprise Security Intelligence. Evaluate known threats against current defensive and protective capabilities to identify coverage gaps, leveraging code reviews to assess the efficacy of technical defenses and detection logic. Conduct limited, focused manual hunting to ensure intelligence remains grounded in operational reality. Produce high-quality threat assessments to get threat scenarios integrated into threat catalogue and engineering roadmaps. Minimum qualifications: Bachelor's degree or equivalent practical experience. 5 years of experience in cyber security, threat intelligence, or threat analysis. Experience in intelligence aggregation, evaluating threat coverage gaps, or threat modeling. Experience with automation --- Source-backed benefit claims include source links; other benefit values are labeled separately.