# FewerJobs export - 100 curated jobs Generated: 2026-06-19T02:31:27.152Z Source: https://fewerjobs.com ## Filters applied - **q**: Silicon Ranch - **quality_floor**: default - **match_401k_strict**: true - **parental_strict**: true - **non_birth_strict**: true - **pto_strict**: true - **include_older**: false - **verified_benefits_only**: true - **apply_url_verified**: false - **page**: 1 - **per_page**: 100 - **sort**: relevance ## Jobs ### Silicon DFT Engineer, Cloud Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU2Jrh8H8FnUYwuT8lOXm8LHJC_JHTJUe5cb4dEPrm4NEjoACxwdTJssuQ62Nc90UTxsz3bG4GOGEIWpoxFZCgWVAjPmmOhB6S-zuT5KpR2t_1JQ6EEybSB6IVJb_V2&loc=IN&title=Silicon+DFT+Engineer - Excerpt: Silicon DFT Engineer, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, ### Silicon Architect, AI Power and Performance - Google - Location: San Diego, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckT31T8N1WBEQdsHHqUU_lQbvcbGp2kp3GkpLjyvrFU4yEjsACxwdTHPMZtv8GlpjRcbaQDsEEpB9iSPAJ2Md93T4tj4iiVqHJMdMX5x949IZLsZoNRl2iVPqz0uLww%3D%3D_V2&loc=US&title=Silicon+Architect - Excerpt: Silicon Architect, AI Power and Performance San Diego, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. This role offers the opportunity to work on cutting-edge power management technologies for AI/ML workloads that directly impact the battery life and efficiency of Google's flagship Android devices and custom silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the analysis and implementation of architectural optimizations that span the full stack - from low-level silicon IP to high-level Android frameworks - to maximize AI performance per watt. Influence hardware and software roadmaps for SOC, AI accelerators, and emerging memory technologies to meet future Gemini and GenAI product requirements. Propose and drive the development of proof-of-concept prototypes for next-generation power management frameworks and specialized AI solutions. Act ### Senior Silicon Diagnostics Engineer - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRgTnRpfD0v4j-vkmDXiKpxOfR6Y7iOVq5ygAC4SoHssEjsACxwdTIS0vLBt8LpsJcrDUCPYpspTLumPzlvE-6Sp9Oy5np1vmx3WDGAM3Rq1oJ-Qsgfw1cIFhw7Jtw%3D%3D_V2&loc=IN&title=Senior+Silicon+Diagnostics+Engineer - Excerpt: Senior Silicon Diagnostics Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Silicon Diagnosis and Defect Isolation: Perform post-silicon electrical and physical fault isolation using production test results (e.g., error logs, flop mapping, and software-based diagnosis) to narrow down the cone of logic. Methodology Development: Develop, deploy, and automate volume diagnosis and data analysis flows. Generate and apply specialized diagnosis patterns for Soft-Defect-Location (SDL) or Laser-Voltage-Imaging (LVI). Cross-Functional Collaboration: Partner with Design, DFX, Verification, and Test teams to define requirements for highly diagnosable designs and to build layout databases for diagnosis and cross-probing. EFA and Root Cause Analysis: Define and execute Electrical Failure Analysis (EFA) workflows to root-cause yield issues, qualification failures, and customer returns. ATE and Pattern Debug: Lead silicon bring-up, debug, and validation of DFT features on Automated Test Equipment (ATE), debugging ATPG patterns, Compressed ATPG patterns, MBIST, and JTAG related issues. Minimum qualifications: Bachelor's degree in Electrical Engineering, ### Silicon Validation Engineer, HBM, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka8VIq_Xb4zmwhGkTVcfsfoPe26eT1COZOBji5niIMPEEjsACxwdTF4RkXftPlyNQ977lxpA-7nvt82U_NexbZkpyTWc7GWAuX3bLFZua9KftmZpVgJ45Inkn3IhUg%3D%3D_V2&loc=US&title=Silicon+Validation+Engineer - Excerpt: Silicon Validation Engineer, HBM, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role you will work on test design, bring-up, triage, and debug of the TPU High Bandwidth Memory (HBM) subsystem across emulation, test chip, and production silicon platforms. You will work closely with Silicon Validation, HBM technologists, and pre-silicon teams during the development phase of the ASIC life-cycle, ensuring proper features are in place for post-silicon validation and debug. Once silicon is in the lab, you will collect and help interpret data alongside system software and software test infrastructure developers to ensure the HBM subsystem has met the threshold for production release. You will help develop processes and tests to ensure smooth and reliable performance of HBM projects. You will be direct throughout the project lifecycle, from early pre-silicon planning and test development, through end-of-life characterization and failure debug. By leveraging silicon knowledge you will develop and operate software-based tests for full investigation of HBM operation. You will work closely with ### Silicon Engineering Intern, PhD, Summer 2026 - Google - Location: Bengaluru, Karnataka, India; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-04-01 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSXlUOuEO9gS15E17xZFqOMX1aCLf9XbjPonHM5m9DWGEjsACxwdTNhVNZ-4aJ0eQfxNOEWyI_XQEVsMjTdfaQBQefsaHS9cVFhZPJtVnZGWrDTLr1STg3wpm55vdA%3D%3D_V2&loc=IN&title=Silicon+Engineering+Intern - Excerpt: Silicon Engineering Intern, PhD, Summer 2026 Bengaluru, Karnataka, India; +1 more As a Silicon Engineering Intern, you will work in a team that is shaping the future of Google Cloud Silicon, including TPUs, arm-based servers, and network products. You will collaborate with hardware and software architects and designers to architect, model, analyze, define, and design next-generation Cloud Silicon. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The ML, Systems, and Cloud AI (MSCA) organization at Google designs, implements and manages the hardware, software, machine learning and systems infrastructure for all Google services (e.g., Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers, and people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest Cloud Silicon products to running a global network, while driving towards shaping the future of hyperscale computing. Google is and always will be an engineering company. We hire people with a broad set of technical skills who are ready to address some of technology's greatest challenges and make an impact on millions, if not billions, of users. At Google, engineers not only revolutionize search, they routinely work on massive scalability and storage solutions, large-scale applications and entirely new platforms for developers around the world. From Google Ads to Chrome, Android to YouTube, Social to Local, Google ### Silicon CAD Engineer, University Graduate, PhD - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXQEUI9XfOeK_3XYuXygggJ1a_miLVttYmMwabnENaQXEjsAvkGZm0RQKdLFnO2Ito9mFe48LB3Cgc6u1G-ovNbiOY28Hj0OLQ_BDRsxHklfEw1eaAGVmVZ00EMthw%3D%3D_V2&loc=US&title=Silicon+CAD+Engineer - Excerpt: Silicon CAD Engineer, University Graduate, PhD Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon CAD Engineer, you will collaborate closely with domain experts in various aspects of silicon development to architect, design, code, and test projects that will have immediate impact on chips powering the next generation of Google Cloud systems. You will work well both separately and as part of a team. In this role, you will work with CI2 Silicon Development teams and your peers in the Infrastructure, Tools, and Methodology team to develop and enhance design tools and design flows that speed the development of CI2's ground-breaking TPU, CPU, and networking chips and enable them to provide generational improvements in performance, power, and cost while enhancing reliability. You will weave your work into the deep tech stack of silicon design, composed of a mix of licensed Electronic Design Automation (EDA) tools, custom tooling, and emergent technologies from GDM and core. The AI and Infrastructure team is redefining what's possible. We empower ### Front-End CAD and IP Management Engineer, Silicon - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSx4-mzNqwjb8Gv7TiHHcGvnvnwjtx5wf2HM7NbT3sw-EjoACxwdTASVnZgTk45cKwMMc8pqAwhlGWzYPcybRtD9RPzSZbjj9xsT1aDmCC2lb78TqE5ZM6emf8EW_V2&loc=US&title=Front-End+CAD+and+IP+Management+Engineer - Excerpt: Front-End CAD and IP Management Engineer, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will serve as the critical link between IP development and SoC integration. You will be responsible for defining and executing the qualification standards that ensure third-party and internal IPs are ready for high-performance silicon designs. You will be developing automated front-end CAD flows, managing complex EDA tool collaterals, and collaborating with cross-functional teams to resolve technical integration bottlenecks. By streamlining the delivery process through advanced scripting and dashboarding, you will directly enable the team to hit dynamic tape-out schedules with high-quality, reliable silicon. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead the delivery of Silicon Internet Protocol (IP) to design teams to ### Silicon Validation Engineering Manager, Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckR2xo1tprTwme8PJLjli5Cg6Fz3vpfHHvSwV26HG_rm6EjsACxwdTEYOUu0GHaTcr-rFdQKfPWzqEpN9HCP6F0b3mDj5YZNsrIpyKtHwkwxOoLa7RPb-nUdmjkNQhA%3D%3D_V2&loc=US&title=Silicon+Validation+Engineering+Manager - Excerpt: Silicon Validation Engineering Manager, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Validation Engineering Manager, you will lead the group focused on custom TPU silicon. You will set strategy and co-ordinate resources, planning, and execution for the team. You will strategize, review, and execute test plans for silicon systems and subsystems. You will own silicon bringup, new product introduction (NPI), and sustaining efforts. You will serve as the central co-ordination point between your team and systems teams, including hardware, software, manufacturing, and supply chain. You will also manage relationships with vendors and contract manufacturers. You will verify that silicon meets functional and performance requirements and own qualification, characterization, and deliverables for post-silicon, including interfaces, compute cores, power, and performance. You will debug issues, suggest fixes, and ensure silicon meets quality and reliability requirements throughout the entire product life-cycle (PLC). The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure ### Head of Silicon Systems and Architecture, XR - Google - Location: San Jose, CA, USA; +1 more (unspecified) - Salary: $236K-$330K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSHxMJwIXJOd1maQp4Qx85NWEQolFxyHPqjXaoKqfStFEjsACxwdTAfb3vOLHObr9_YL6YBagpCdZ7k-6ueAF172aQvmnK0GvI1H4ASZD_g2ITjYWXy-v-9agezcWQ%3D%3D_V2&loc=US&title=Head+of+Silicon+Systems+and+Architecture - Excerpt: Head of Silicon Systems and Architecture, XR San Jose, CA, USA; +1 more The XR team at Google is building the future of immersive and augmented computing. We are a fast moving team with engineers, designers, and research scientists tasked to build the next generation technology to shape people's way of living in new imaginative ways. Through the development of Galaxy XR, Smart Glasses prototypes, and ARCore we are enabling augmented reality experiences around the world. But we aren't stopping there. We are working on really cool, technologies enabling the next generation of immersive and augmented experiences, through collaborations with teams across Google and our third-party partners. As the Head of Silicon Systems and Architecture, you will serve as the primary architect and multiplier for our silicon partnerships. You will define the hardware foundations through silicon for the next generation of headsets and glasses, ensuring that future chipsets are vertically integrated with Google's perception and software stacks to deliver user experiences. For decades, the computing revolution has reshaped our world driven by breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap - the convergence of AI and XR. This is more than just new devices - it's about reimagining how we interact with the world around us. We're building a future where lightweight XR devices like smart glasses and headsets pair with helpful AI to augment human intelligence, offering personalized, conversational, and contextually aware experiences. Individual pay is determined ### Silicon Validation Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka5PTdUfs1wloIR9r81GHVZElnQY504gy9d04eiFR4ayEjsACxwdTCB2ZP3pLkpqqk00vPsYs_ALHZcsqhUuqbzq2FnH8npUPaR8oluodDTBd5CkkDiNYkk46ky2vQ%3D%3D_V2&loc=US&title=Silicon+Validation+Engineer - Excerpt: Silicon Validation Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be helping in bringing custom Application-Specific Integrated Circuits (ASICs) from concept through to production. You will be a part of the silicon validation effort of the overall silicon product development lifecycle. Your efforts may center on power features, interfaces, HBM memory, compute functionality, or various aspects of system performance. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development ### Senior Silicon Validation Engineer, Volume Production and Yield - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcBv3c-mndogVhEkYE37Mk34x9dzHEEAb_KCUkQpBPgLEjoACxwdTHBQDojrv927YvHFR2nrwyS9Vp6wse0kSP1c0gzMmAi6rg2By5OndeMoQAIalDRWZ-M1S7GZ_V2&loc=TW&title=Senior+Silicon+Validation+Engineer - Excerpt: Senior Silicon Validation Engineer, Volume Production and Yield New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. We are seeking a highly motivated and experienced Silicon Engineer to drive our Volume Production and Yield efforts. In this pivotal role, you will be the primary technical owner for the transition of our silicon designs into high-volume factory manufacturing, delivering screening packages to factory partners and driving continuous silicon yield monitoring, failure analysis, voltage margin characterization, and improvement across the product lifecycle. You will leverage AI-driven data analytics and machine learning techniques to optimize yield, accelerate failure debug, and enhance overall silicon quality. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Provide technical guidance and expertise for volume productization and post-silicon yield enhancement. Define and deliver silicon screening packages to factory organizations. Execute and refine the silicon yield management strategy, leading failure analysis, root cause debug of limiters, and production data analysis. Leverage AI/ML tools ### DFT Engineer III, Cloud Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcTfj3r4d3SkBW4h86DXRjZga6p2DwbnkxUTHie32BD9EjsACxwdTND6-8pa1tS3dqGKUBWQom-0r0U2PctMGdcj18UuNKteTtI0A02BXgbolKcmd02lWWD9bAV1cw%3D%3D_V2&loc=IN&title=DFT+Engineer+III - Excerpt: DFT Engineer III, Cloud Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be responsible for defining, implementing, and deploying advanced Design for Testing (DFT) methodologies for digital, mixed-signal chips, or IPs. You will define silicon test strategies, implement, and create DFT specifications for the next generation System on a Chip (SoCs) while working with the DFT organization. You will design, insert, and verify the DFT logic, and will prepare for post-silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality, and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high test quality and support the post-silicon test team. Generate, simulate, and optimize high-quality manufacturing test patterns (stuck-at, transition, ### Senior Silicon Validation Engineer, CPU - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-14 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWW8AJoPNSPXIAGgb5ryvbway0dE468oviKvSbnx20vdEjsACxwdTBEft1b4lkA7fE08HHDco0KdK74auovTLj7qMGI3TTyCee99mknrOkgrETYXzgIi7nj7ZS5fMA%3D%3D_V2&loc=IL&title=Senior+Silicon+Validation+Engineer - Excerpt: Senior Silicon Validation Engineer, CPU Tel Aviv, Israel; +1 more Google's custom-designed machines make up one of the largest and most powerful computing infrastructures in the world. The Hardware Testing Engineering team ensures that this cutting-edge equipment is reliable. In the R&D lab, you design test equipment for prototypes of our machinery and develop the protocols used to scale these tests for the entire global team. Working closely with design engineers, you give input on designs to improve our hardware until you're sure it meets Google's standards of quality and reliability. As a Silicon Validation Engineer at Google Cloud, you will play a pivotal role in the validation of Google's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. With your expertise in post-silicon validation, you will be identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini ### Lead Engineer, Silicon and Software Integration, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcke_rYZmtmmfyuc6k515IcfXGNRmqzoX59TCER6Pr8orgEjsACxwdTNttFXATyxiDxBOc6JkaiguCDfROG06XdssJ59wlan7AAL9KWa99z4ZMUVOfbtd5eCeCxaw5HQ%3D%3D_V2&loc=US&title=Lead+Engineer - Excerpt: Lead Engineer, Silicon and Software Integration, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be working on ASIC development, validation, software, tools, and methodologies and will have the ability to push the boundaries of chip-development and hardware/software integration and validation. You will own cross-functional work streams focussed on end-to-end HW/SW integration and validation to demonstrate HW, SW, and system functionality and performance. You will help the chip team accomplish key silicon development criteria, meet chip and system schedules and achieve readiness for production in various silicon and system validation environments. You will serve as a key bridge between specification, design, and verification teams as well as compiler and performance teams with technical depth and breadth across the ML compute IP. As a lead, you will own strategy, planning, validating, and delivering hardware and software systems which are shown to be functional and performant. You will be responsible for coordination, debug, and enablement of the platform. The AI and Infrastructure ### Lead Technical Program Manager, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVTazclusinip1jBswYyzOvGc--D-4XgI-kE1LJGfvl_EjsACxwdTBQWoTT_K_yP3dQRErrX_bmulRS84Kmc_QHQjGPM1H0oB0-tNk9xGDRXVhAJpzWGc_FnQPohOw%3D%3D_V2&loc=IN&title=Lead+Technical+Program+Manager - Excerpt: Lead Technical Program Manager, Silicon Bengaluru, Karnataka, India A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. As a Senior Silicon Implementation Technical Program Manager (TPM) team, you will lead a team responsible for SOC development over the full product cycle from pre-silicon to commercialization. You will have a strong understanding of IP and SoC delivery in an exceptional silicon team. You will bring a breadth of expertise across silicon architecture, RTL, Design Verification (DV), Physical Design (PD), etc. to enable silicon productization. You will drive execution of multiple concurrent SoC projects, this includes coordination of deliverables across multiple geographies, managing overall program schedules at Power Performance Area (PPA) and quality, negotiations with stakeholders and escalation when needed to get decisions made and dissemination of program status across the team. You will need to have excellent written and verbal communication skills and relationship building across stakeholders. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the ### Junior Silicon DFT Engineer, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckR9UPsc5QchtDjZP3SQJQndmIgfGGaLoSzISQ5nemoB6EjsACxwdTKzR_OXeCkH_Qfb0baN0i7l7pO3YfOUZzT9KEJldwawsSmltOBOrd-JybSFrJkL0LhAV6kIzvg%3D%3D_V2&loc=IL&title=Junior+Silicon+DFT+Engineer - Excerpt: Junior Silicon DFT Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You will design and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), ### AI/ML Silicon Validation Lead, Google Cloud, TPU - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSOe87Wp06MCFJwPXNFNXy2afW3_gQ0cZAPhTXa2qX51EjsACxwdTGWyYfEXW2XqUcesPl26w7bc_S3uZ5dBtYu4xpSCBtjh6xZZdus2BzrW3047gEgmuNMmbOnvzg%3D%3D_V2&loc=IN&title=AI/ML+Silicon+Validation+Lead - Excerpt: AI/ML Silicon Validation Lead, Google Cloud, TPU Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The Platform Enablement team is responsible for the development, bring-up and qualification, deployment, sustaining the quality of our AI/ML custom silicon. We plan and integrate hardware and software stacks and operate them on emulation, simulation and post-silicon platforms. We work closely with silicon design, platform hardware, firmware and software teams to enable on-time delivery of high quality silicon products. As a Manager, you will be responsible for growing the team through hiring, developing a psychologically safe environment for the team to succeed, enabling people development through effective career conversations, mentoring and building a strong community. In this role, you will be working on building, managing and leading a team of engineers responsible for post-silicon validation of AI/ML SoC which uses technology, working closely with the architecture, design, verification, firmware, software and platform leads, ensure timely silicon bring-up, enablement and debug closures and driving the preparation of necessary tests and collaterals for effective ### Silicon Validation and Automation Engineer - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXE8Yp27kgEeVrebkRDNg_Bw0Usxh7qVMX8uydfHYVstEjsACxwdTGCuTAErXRfcyBAAGPhHaOi_ZUJEnRpKTFf2-7ZbfsEq8eXb70PmLS4mHLnHmcYd6H7L0JqogA%3D%3D_V2&loc=IL&title=Silicon+Validation+and+Automation+Engineer - Excerpt: Silicon Validation and Automation Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Run, monitor, and analyze nightly Continuous Integration (CI) regression results. Design and implement new regression methods and supporting infrastructure/Graphical User Interface (GUI). Identify, debug, and report issues while performing initial root cause analysis and routing to IP owners. Develop and maintain tools for silicon validation and debug. Maintain and enhance automation infrastructure for various regression cadences. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Physics, a related field, or equivalent practical experience. 1 year of experience in post-silicon validation, SoC debug, or a similar role. Experience with Continuous ### Staff Engineer, Post-Silicon Validation (AI-Enabled Workflows) - Analog Devices - Location: US, MA, Wilmington (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://analogdevices.wd1.myworkdayjobs.com/External/job/US-MA-Wilmington/Staff-AI-ML-Applications-Engineer---Product-Validation---Test_R260874 - Excerpt: Staff Engineer, Post-Silicon Validation (AI-Enabled Workflows) US, MA, Wilmington posted: Posted 23 Days Ago ### Lead Silicon Validation Engineer - NXP Semiconductors - Location: Pune (unspecified) - Salary: Not disclosed - Posted: 2026-05-25 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Pune/Silicon-Validation-Engineer_R-10063514 - Excerpt: Lead Silicon Validation Engineer Pune posted: Posted 18 Days Ago ### Lead CPU Design Verification Engineer, Silicon - Google - Location: Portland, OR, USA; +3 more (unspecified) - Salary: $192K-$279K - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVBiwAnyYDR5guGtlVKCyNChf_E-CiEDz314uQGIzJM4EjsACxwdTIpsjZKRVvSyJ_4t4cd32jnyM3xQL9w14th4qQblPQnh77_XgV_8ljhfCVYKz0EeTx-PrFr3HA%3D%3D_V2&loc=US&title=Lead+CPU+Design+Verification+Engineer - Excerpt: Lead CPU Design Verification Engineer, Silicon Portland, OR, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that sufficiently enable production of quality CPU's. Verify and validate performance for both pre-silicon and post-silicon. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Experience with processor microarchitecture. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis ### Senior Post-Silicon Validation Engineer, Networking - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckbwn2P2CShq6gVcyOBMg1Uha4jcuL5wGNCXSCbpgTy9iEjsACxwdTFXGzn9IJ49mnP8Ok8LEyJRTvVQNF9Z3CsKPPGt1fo_MQlNrckOcY8c_29gJ68YcmuEowGRcmQ%3D%3D_V2&loc=IL&title=Senior+Post-Silicon+Validation+Engineer - Excerpt: Senior Post-Silicon Validation Engineer, Networking Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. We are building a new team to lead the post-silicon validation efforts for our cutting-edge product. We're looking for highly motivated and talented engineers to join us in ensuring the quality and functionality of our next-generation networking silicon. This is a unique opportunity to be part of a foundational team and make a significant impact. As a Silicon Validation Engineer at Google Cloud, you'll play a pivotal role in the validation of Google's custom silicon solutions that power our cloud infrastructure bringing it to the highest quality level. Your expertise in post-silicon validation will be essential in identifying and resolving issues before they impact our customers, ensuring a seamless and high-performance cloud experience. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale ### Silicon Reliability Engineer - NXP Semiconductors - Location: Shanghai (JingAn) (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Shanghai-JingAn/Silicon-Reliability-Engineer_R-10063793-1 - Excerpt: Silicon Reliability Engineer Shanghai (JingAn) posted: Posted Today ### Personal Banker - Universal- East Highlands Ranch - The PNC Financial Services Group, Inc. - Location: CO - Highlands Ranch (80126) (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://pnc.wd5.myworkdayjobs.com/External/job/CO---Highlands-Ranch-80126/Personal-Banker---Universal--East-Highlands-Ranch_R223643 - Excerpt: Personal Banker - Universal- East Highlands Ranch CO - Highlands Ranch (80126) posted: Posted 11 Days Ago ### Personal Banker - Universal (Green Valley Ranch & Tower) - The PNC Financial Services Group, Inc. - Location: CO - Denver (80249) (unspecified) - Salary: Not disclosed - Posted: 2026-06-05 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://pnc.wd5.myworkdayjobs.com/External/job/CO---Denver-80249/Personal-Banker---Universal--Green-Valley-Ranch---Tower-_R225555-1 - Excerpt: Personal Banker - Universal (Green Valley Ranch & Tower) CO - Denver (80249) posted: Posted 7 Days Ago ### Personal Banker Stevens Ranch - The PNC Financial Services Group, Inc. - Location: TX - San Antonio (78253) (unspecified) - Salary: Not disclosed - Posted: 2026-05-22 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - Apply: https://pnc.wd5.myworkdayjobs.com/External/job/TX---San-Antonio-78253/Personal-Banker-Stevens-Ranch_R224004-1 - Excerpt: Personal Banker Stevens Ranch TX - San Antonio (78253) posted: Posted 21 Days Ago ### Relationship Banker II (Lakewood Ranch) - Regions Financial Corporation - Location: Bradenton, FL - South Lakewood Ranch Branch (St. Petersburg, FL) (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 12 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://regions.wd5.myworkdayjobs.com/Regions_Careers/job/Bradenton-FL---South-Lakewood-Ranch-Branch-St-Petersburg-FL/Relationship-Banker-II--Lakewood-Ranch-_R102655 - Excerpt: Relationship Banker II (Lakewood Ranch) Bradenton, FL - South Lakewood Ranch Branch (St. Petersburg, FL) posted: Posted 3 Days Ago ### Part-Time Truck Unloader (Required 5am Start) - Kohls CORP - Location: Yorba Linda-Savi Ranch (0755) (unspecified) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - Apply: https://kohls.wd1.myworkdayjobs.com/kohlscareers/job/Yorba-Linda-Savi-Ranch-0755/Part-Time-Truck-Unloader--Required-5am-Start-_R445467 - Excerpt: Part-Time Truck Unloader (Required 5am Start) Yorba Linda-Savi Ranch (0755) Yorba Linda-Savi Ranch (0755) ### Relationship Banker/SR - Lakewood Ranch - Truist Financial Corporation - Location: Bradenton, FL (unspecified) - Salary: Not disclosed - Posted: 2026-05-14 - Parental leave: 10 weeks (not source-backed) - Non-birth-parent leave: 10 weeks (not source-backed) - Apply: https://truist.wd1.myworkdayjobs.com/Careers/job/Bradenton-FL/Relationship-Banker-SR---Lakewood-Ranch_R0114539 - Excerpt: Relationship Banker/SR - Lakewood Ranch Bradenton, FL posted: Posted 29 Days Ago ### TPU Validation Manager - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckV5NOuKitZQbGcLV2TGm6EvodTzBK554QYvKVhms63WkEjsACxwdTK-92xxNevMd7S8-r2_tCQME7fBfS5qp-5Levd8hm86Sz6H49jsoq9cj0zLaU-A6AABiEBUfpQ%3D%3D_V2&loc=US&title=TPU+Validation+Manager - Excerpt: TPU Validation Manager Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead and manage the team responsible for the silicon validation of Tensor Processing Unit (TPU), Google's custom machine learning accelerator, in mobile SoC products. Drive the development of test plans and advanced verification frameworks for pre-silicon emulation and post-silicon validation. Oversee power and performance measurement, ensuring correlation with pre-silicon to meet product goals. Collaborate with Architecture, Design, Software, and Design Verification (DV) teams to resolve ### Staff Software Systems Architect, Silicon - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWB1Bg9dX1teAzO30GDz6uq6lL8RVO74JsspVnVfVxCYEjsACxwdTD_JziNRgyTO7xjjfWdfy5lAAmNBubJY5U2hS6GGnQPUB6FfDul3KTKPiV7WPsQDJT47Z3_tmQ%3D%3D_V2&loc=US&title=Staff+Software+Systems+Architect - Excerpt: Staff Software Systems Architect, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, as part of the Silicon System Architecture team, you will enable software/hardware co-design of System-on-a-Chips (SoCs) by leveraging your systems expertise and influence IP, SoC, and system software architecture. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Influence hardware decisions by thorough analysis of system and first-party software. Influence software architecture to leverage Silicon goodness. Collaborate closely with Google Research, Pixel, and Software teams to deliver product differentiating experiences. Architect solutions that meet power, performance, and area goals. Push the boundaries of innovation through radical approaches to address complex system challenges. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, ### Technical Program Manager III, Silicon Development, Technical Infrastructure - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUly1spj_poqKFUXKQpXlu634ipAbftBMeIcO3nixRajEjsAvkGZmyDHHrCCG7uDbgiOlXh5J6NBbL1F7lmS956BPlQebGPlF2cQjPTKomeHHNesr1QG8WhqA5tP-w%3D%3D_V2&loc=US&title=Technical+Program+Manager+III - Excerpt: Technical Program Manager III, Silicon Development, Technical Infrastructure Sunnyvale, CA, USA Google's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers. Using your extensive technical and leadership expertise, you manage projects of various size and scope, identifying future opportunities, improving processes and driving the technical directions of your programs. As the Silicon Development Technical Program Manager, you will support Google's custom silicon for AI by managing custom silicon development programs. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by factors including job-related skills, experience, and relevant education ### Lead, Advanced Silicon Sourcing and Strategic Investments - Google - Location: Austin, TX, USA (unspecified) - Salary: $240K-$334K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckV2TdtsKxnXCpEqhbqpEUeahw-ZfmL_BGflcYH1QraQiEjsACxwdTLbny4xubLVbAgowpSGpeTr-PIwhAExhCJE3GqoGD8xQ8SJ8loPF1s25Iajy2kgB9-jyQk5WBA%3D%3D_V2&loc=US&title=Lead - Excerpt: Lead, Advanced Silicon Sourcing and Strategic Investments Austin, TX, USA Google's projects, like our users, span the globe and require managers to keep the big picture in focus while being able to dive into the unique engineering challenges we face daily. As a Technical Program Manager at Google, you lead complex, multi-disciplinary engineering projects using your engineering expertise. You plan requirements with internal customers and usher projects through the entire project lifecycle. This includes managing project schedules, identifying risks and clearly communicating them to project stakeholders. You're equally at home explaining your team's analyses and recommendations to executives as you are discussing the technical trade-offs in product development with engineers. Using your extensive technical and leadership expertise, you manage various Engineering-specific programs and teams. As a Lead for Advanced Silicon Sourcing and Strategic Investments, you will direct the forward-scanning commercial pillar of Google's Silicon Sourcing Center of excellence. Your mandate is to secure Google's 5-year silicon roadmap through strategic venture investments, complex IP acquisitions, and proactive supply chain de-risking. While you will partner closely with engineering on ecosystem pathfinding (such as early test vehicles), your primary focus is structuring the financial and commercial agreements Joint Development Agreements (JDAs), Long-Term Agreements (LTAs), and partnerships that buy technical certainty and guarantee future capacity for Google's AI infrastructure. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google ### Senior Packaging Design Engineer, Silicon - Google - Location: Mountain View, CA, USA; +1 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVXMYAwoIfYyDP8ytjsh9kNzHL_CXxCKtYp-Oc1iVB1lEjsACxwdTN7OVxtHjGscf2_RldXJAQfb213bEE3IQIkgEoBvEvd6deIekz7rqSh9kukzdHboD28MbfJobA%3D%3D_V2&loc=US&title=Senior+Packaging+Design+Engineer - Excerpt: Senior Packaging Design Engineer, Silicon Mountain View, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Define, plan and execute end-to-end physical package substrate design of mobile SOC packages as a unique contributor, meeting performance/power/area requirements. Manage and drive co-design initiatives across silicon, package, and system levels, including securing production sign-off for package designs. Participate in the development of new silicon Internet Protocols (IPs) and packaging technology through system requirement analysis, feasibility studies and package test vehicle designs. Collaborate closely with Signal integrity (SI)/Power Integrity (PI), Test, New Product Introduction (NPI) and Mechanical Engineering teams to refine and optimize product package architecture and design. Develop, implement and debug package design methodology and CAD flow. Interface ### Post Silicon Advanced Packaging Engineer - Google - Location: Taipei, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-26 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWt1U1jPFLwp1NaN6nSRthRaWTkf0K6f4553J5MCBKHwEjsACxwdTAfQzVWgwXRL5rwhMAIsuXijrZBEqPQQ0s0KUDYj-RkZCvQsQg6WjsadQ1ezE_mNMHW-5nnYLg%3D%3D_V2&loc=TW&title=Post+Silicon+Advanced+Packaging+Engineer - Excerpt: Post Silicon Advanced Packaging Engineer Taipei, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Post Silicon Advanced Packaging Engineer, you will bridge the gap between post-silicon bring-up, foundry/OSAT manufacturing, and IC design. You will own the mass production yield, quality, and sustaining engineering for high-performance computing and AI products utilizing 2.5D/3D advanced packaging architectures. Your primary focus is maximizing package-level yield, resolving complex multi-die integration failures, and driving cross-functional engineering teams to optimize cost and reliability. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Monitor, analyze, and improve package-level yields for 2.5D/3D architectures. Track yield from ### Senior CMOS Test and Validation Lead, Analog Mixed-Signal, Raxium - Google - Location: Fremont, CA, USA (unspecified) - Salary: $240K-$334K - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTO68KqATPWDWgbfdWSF49r4M1vxQssjRvZnxJo9YTWZEjsACxwdTOW3paG-uR_2amQVoJ5M4S4urQI_FWj4tCKcDAB8GRXvk9_XzhqhbBqGiq3IvTr1puPwkYGBow%3D%3D_V2&loc=US&title=Senior+CMOS+Test+and+Validation+Lead - Excerpt: Senior CMOS Test and Validation Lead, Analog Mixed-Signal, Raxium Fremont, CA, USA As a Senior Test and Post-Silicon Validation Lead, you will drive the bring-up, characterization, and high-volume manufacturing (HVM) release of our next-generation Analog Mixed-Signal (AMS) ASICs. In this critical leadership role, you will bridge the gap between design, DFT, and product engineering, ensuring zero-defect quality and optimized cost-of-test for our upcoming product lines. You will architect ATE test strategies and guide a small team of engineers through complex yield and performance bottlenecks. Google's Raxium display group has established a revolutionary semiconductor materials display technology that enables new functionality in display products, bringing to users a closer and more natural linkage between the digital and physical realms in applications such as augmented reality (AR) and light-field display. With start-up roots and a state-of-the-art compound semiconductor fab in Silicon Valley, Raxium is seeking to build upon its engineering team with an aim to disrupt next-generation display markets. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $240000 - $334000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Lead and mentor a team of test and validation engineers through the entire post-silicon lifecycle, from first-silicon bench bring-up to ATE production release. Partner with IC Design and DFT teams during the pre-tapeout phase to define Post SIlicon Test Process and Design requirements. Design, develop, and debug multi-site ATE test programs (Advantest V93000 or Teradyne UltraFLEX) ### Senior Design Verification CAD Engineer, Silicon, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcML6pgvbv-KjSCalJvLONO_uoLjpjvIb7xHF6uVBIDKEjsACxwdTFy3OLQvo8wnHCylfMH8c6lcFEYjQfDIIiSBIb4Sw3NZoNon8TDw9yQuZN-0ZVuu6txGwRMbcw%3D%3D_V2&loc=US&title=Senior+Design+Verification+CAD+Engineer - Excerpt: Senior Design Verification CAD Engineer, Silicon, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Senior Engineer within Google's silicon team, you will help deliver products that have a substantive impact on the Technical Infrastructure that powers Google. You will provide leadership to a group of hardware engineers in a fluid environment with a focus on infrastructure for chip design. You will also lead the technical projects from the concept/planning stage through execution and closure. In this role, you will help your team deliver designs that work for the first time in a number of different application areas. Leveraging your technical and leadership expertise, you will lead the chip design process improvement projects in multiple areas of expertise. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the ### Silicon Design Verification Engineer, Quantum AI - Google - Location: Mountain View, CA, USA; +1 more (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZBrlSIJ2RP0JswxqGM5BOAeAy80x62shuzWXEYtvo9mEjsACxwdTDuhKmYc0SPC0qbjgg04TXclBqiPhj2OviUIuP9twM6BXqcXGSdAZKNtGIhuEt9RexYAzZiuLg%3D%3D_V2&loc=US&title=Silicon+Design+Verification+Engineer - Excerpt: Silicon Design Verification Engineer, Quantum AI Mountain View, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a vital member of the quantum electronics team, providing key technical contributions in the area of ASIC design verification (DV) as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital, DV, physical design, and radio frequency/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. As a Silicon DV Engineer, you will help drive the DV of all of Quantum's control and readout electronics. You will contribute to the entire verification lifecycle for our ASICs, collaborating with ASIC architects, digital designers to understand the chip functional requirements, plan out verification plans, and drive execution of those plans in collaboration with other DV engineers. You will build out and track coverage metrics to ensure thorough verification of designs. You will also work with external IP vendors, overseeing the DV work that they directly provide on their own IP and collaborating with these vendors to create suitable DV integration coverage. The full potential ### Senior CAD Engineer, RTL Design, Silicon, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUOn5MgjCXJTLY6gWQVc52BAMJ8ksdEzq30-JPL_oC9IEjsACxwdTDggnjPzdXYCWDRFH-wPhFpDKvQ7bHiSo8z4_MLAYwGrK5LtxoQkZNMwE7b1QBXRdiLZ0KLEFQ%3D%3D_V2&loc=US&title=Senior+CAD+Engineer - Excerpt: Senior CAD Engineer, RTL Design, Silicon, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Senior Engineer within Google's silicon team, you will help deliver products that have a substantive impact on the technical infrastructure that powers Google. You will provide leadership to a group of engineers in an innovative and changing environment with a focus on infrastructure for chip design. You will also lead technical projects from the concept/planning stage through execution and delivery. In this role, you will help the organization to accelerate delivery of designs for the next generation TPUs and other chips. Leveraging your technical and leadership expertise, you lead end-to-end chip design process improvement projects. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the ### Silicon Engineer, Platform and Devices, University Graduate, 2026 - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQ9FwAK0RaOP9w4ljDAsUXQ46JXKTdlFUxa4rh_PGf5DEjsACxwdTI9PELAQMcnJijhRyB1gz9Zrg9KXDR-r5BvOeBc8LvZiTuiODlJU5_hu87HwBMlL40qzv_q5Wg%3D%3D_V2&loc=IN&title=Silicon+Engineer - Excerpt: Silicon Engineer, Platform and Devices, University Graduate, 2026 Bengaluru, Karnataka, India Google engineers develop the next-generation technologies that change how users connect, explore, and interact with information and one another. As a member of an extraordinarily creative, motivated and talented team, you develop new products that are used by millions of people. We need our engineers to be versatile and passionate to take on new problems as we continue to push technology forward. If you get excited about building new things and working across discipline lines, then our team might be your next career step. Google's Consumer Hardware Silicon division builds chips optimized for Google-branded consumer devices. Our product areas include imaging, machine learning, video, and security. We aim to build a team with talent that resonates with Google's culture of innovation and fun. As a Silicon Engineer, you will design, develop, and deploy consumer hardware. As a member of a fast-paced multi-disciplinary team, you will use your creativity and various range of engineering experience to explore solutions to a variety of engineering problems. Additionally, you will participate in the design, analysis, and prototyping of new concepts. You will also work in a manufacturing and product oriented development environment and collaborate with vendors and outside sources in order to see parts through to manufacture. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams ### Senior Silicon Product Manager, TPU Hardware - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcpS8U0HbYWnxStvwWa1eKgYDhnNPMlwLF84L7LFF5TeEjsACxwdTOLpfhC4VYvDKN9pmuuuqmJufs8t1wE64d5P4trAjlc4y-fncQyDGnmNz2b_Uvv-ruynY3DyPA%3D%3D_V2&loc=US&title=Senior+Silicon+Product+Manager - Excerpt: Senior Silicon Product Manager, TPU Hardware Mountain View, CA, USA At Google, we put our users first. The world is always changing, so we need Product Managers who are continuously adapting and excited to work on products that affect millions of people every day. In this role, you will work cross-functionally to guide products from conception to launch by connecting the technical and business worlds. You can break down complex problems into steps that drive product development. One of the many reasons Google consistently brings innovative, world-changing products to market is because of the collaborative work we do in Product Management. Our team works closely with creative engineers, designers, marketers, etc. to help design and develop technologies that improve access to the world's information. We're responsible for guiding products throughout the execution cycle, focusing specifically on analyzing, positioning, packaging, promoting, and tailoring our solutions to our users. We are looking for someone with deep technical and product management experience to define and help deliver AI compute in the form of Tensor processing units. In this role you will help define ML hardware in collaboration with the silicon engineering team, compiler team and advanced research teams across the company as well as the device hardware/software groups. You will define an ML compute roadmap which will enable Pixel to bring to life key features that distinguish our first-party devices. We accomplish this with deep strategic and product insights rooted in silicon, software, systems and ML, which are all part of our full ### Staff Silicon Physical Design Engineer, Quantum AI - Google - Location: Mountain View, CA, USA; +1 more (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka6ynNv-mDgL43cCHuU-QcnkQeaVPfXvQdRR5qXxalNxEjsACxwdTJz6IPcZdARe4StyfvFv27I07rEtCUPBWqIO1af98KffnC2Z2GFag9fhjjmiLDiJZLrEJXVnUA%3D%3D_V2&loc=US&title=Staff+Silicon+Physical+Design+Engineer - Excerpt: Staff Silicon Physical Design Engineer, Quantum AI Mountain View, CA, USA; +1 more In this role, you will be a vital member of the quantum electronics team, providing technical leadership in the area of ASIC implementation as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital designers and RF/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. You will own the digital RTL-to-GDS2 process, developing standard ASIC implementation flows and using these flows to transform RTL-level designs into fabrication-ready GDS; this will involve leading external implementation teams through the ASIC digital implementation process. You will be involved in vendor selection, vendor program management, Statement of Work (SOW) documentation, and managing foundry and post-silicon vendor activities related to silicon quality. You will collaborate with adjacent teams and members of the quantum electronics team to contribute to the long-term ASIC strategy. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + ### Silicon Quality and Reliability Engineer, Google Cloud - Google - Location: Zhubei, Zhubei City, Hsinchu County, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaAU75i4_w2XWH9n124Pw_Te4B8Qqarg2I2Jt1JlqbmEEjsACxwdTEJgx-LCdkQPotP29fpSauah-bnUoRGwaRKkAEgeE3f70Yo4nwX20lbVWsIXk2X5NBQ1R1pKDQ%3D%3D_V2&loc=TW&title=Silicon+Quality+and+Reliability+Engineer - Excerpt: Silicon Quality and Reliability Engineer, Google Cloud Zhubei, Zhubei City, Hsinchu County, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will help to build the System-on-a-chip (SoCs) that power these facilities by driving quality and reliability processes in High Volume Manufacturing (HVM) from an Integrated Circuit perspective. You will partner with cross-functional teams to develop HVM quality and reliability specifications while collaborating with global hardware teams, silicon design, validation, and engineering groups to ensure fleet excellence. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Perform the electrical and physical failure analysis on Central Processing ### Senior CPU Design Verification Engineer, Silicon - Google - Location: Mountain View, CA, USA; +3 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU4zQvSjvLOqgv1TjVVF2htjJNAQfQA1ipbMxK_csNLGEjsAvkGZm4gGMTnIcx2G1GL9FomTflOr9_V0ui7uWi7uDZYPQVxtvoBj_RdKpSFZPWC-ouNr0u7vOlWyOA%3D%3D_V2&loc=US&title=Senior+CPU+Design+Verification+Engineer - Excerpt: Senior CPU Design Verification Engineer, Silicon Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Perform design verification for future CPU developments. Perform functional verification and performance validation for both pre-silicon. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 5 years of experience in verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Preferred qualifications: Master's degree or Phd in Electrical ### Product Engineer, Silicon - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckX-odLN69k7Uaha59go4aXEYe3xIPOy4WGgGuuYUrNozEjoACxwdTOXO27akjy1vHUAMwNVd8KDcHhVcIUPX0DFK-5rTUXIIKKOTg_7NtsQJ3P_wDPNR6a0ZywCZ_V2&loc=TW&title=Product+Engineer - Excerpt: Product Engineer, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will develop and deploy productization solutions while partnering with cross-functional teams to enable manufacturing at fabrication plants and assembly and test sites. You will help integrate System on a chip (SoC) technologies into devices and facilitate Automated Test Equipment (ATE)/System Level Testing (SLT) manufacturing testing of SoC to validate performance and screen out failing devices. You will work with cross-functional teams to ensure optimal test coverage and cost efficiencies in production to ensure quality SoCs. You will work with multiple groups to develop digital and mixed signal tests, automation methodologies, develop/support internal tools for data analysis, yield analysis, silicon debug, reliability qualification, manufacturing ramp and customer returns. You will also be a partner on releasing production test solutions into mass production. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform SoC Artificial Intelligence (AI)-centric product specifications ### Silicon Product and Failure Analysis Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdHzC1-bepjwhY32u7AqGa5U99dC1_kDyxnHy7q_j1xfEjsACxwdTIk9ErlXuNEIzEUAHcTJCI6UXPpmt6jY0ltWAIXq-yg8ahStuCodSeEBlUZAMIMmnXL5pgCoBA%3D%3D_V2&loc=US&title=Silicon+Product+and+Failure+Analysis+Engineer - Excerpt: Silicon Product and Failure Analysis Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Silicon Product and Failure Analysis Engineer, you will contribute experience in product development to lead and drive high performance product readiness. In collaboration with functional teams, you'll analyze and resolve problems by identifying failure modes of affected materials as part of a fast-paced environment. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI ### Platform and Chassis ASIC Architect, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckY04TBr7YLMiaF5vSpKZgN9goZeZtX2o_A4hQneKYAtCEjsACxwdTAjRoz5CJYZtgbAZU9bdyctZVsKiassU6Glvx1flJAFGI59HFTT_xUIOrVT7Tg9zgQLA59tRhw%3D%3D_V2&loc=IN&title=Platform+and+Chassis+ASIC+Architect - Excerpt: Platform and Chassis ASIC Architect, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will collaborate with software and hardware architects to explore Platform and Chassis trade-offs in Tensor SOC. You will develop and use analytical tools, simulation, emulation, and post-silicon measurements to perform holistic analysis of large complex ASIC designs. You will influence current and next generation SOCs in the product lineup, and play highly visible roles from ideation through mass production of our SOCs. As part of this work, you will participate in the development of exceptional technologies in fabric, memory, etc., and filing associated patents.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Impact and influence multiple stages of the SOC lifecycle, from ideation and concept through tapeout, bringup and mass production. Participate in architectural design and evaluation of future ASIC designs. Participate in creating architectural specifications for ASIC. Optimize top-level architectural definition to handle complex multi-IP flows. Communicate the analysis results in ### ASIC Design for Testability Engineer, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQoPfA80Ph6n6nw-gsFYkJ2uS0YV4a5IIppzAOakJ_NGEjsACxwdTLA4Bl9HjOS8oZzBY_mM11SsTia88G339R_-gVU8fqXpL2b8DWjb3tVBQ9t0deMHu8JcH34KMQ%3D%3D_V2&loc=IN&title=ASIC+Design+for+Testability+Engineer - Excerpt: ASIC Design for Testability Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Work with a team of DFT engineers, working with RTL, Physical Designer Engineers, SOC DFT and Product Engineering team. Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. Write basic to complex scripts to automate the DFT flow. Develop tests that can be used for Production in the ATE flow. Work with the members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC. Minimum qualifications: Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience. 4 years of experience in DFT/DFD flows and methodologies. Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. Experience with DFT EDA ### Silicon Validation and Debug Engineer - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSHDP4b6fwkyGDmSRdKx0JUBSN_JLXhTN57xAqjCoqsFEjsACxwdTE265wOd40vL4HezRlSb_xGfO2Bwvoqjrmef8sh1QeEATHN_RlEQIewfjOWwZD568i1HqS7ncA%3D%3D_V2&loc=IL&title=Silicon+Validation+and+Debug+Engineer - Excerpt: Silicon Validation and Debug Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Contribute to developing and improving post-silicon test content that exercises both IP and SoC levels workloads and other compute-intensive scenarios. Collaborate with architecture, design, and firmware teams to define comprehensive validation plans for SoC features, focusing on power consumption, thermal management, sensors behavior, and performance metrics. Work closely with design and firmware teams to propose and implement solutions for optimizing SoC power efficiency and performance, including tuning core-to-memory latencies and bandwidth, power control loops, thermal control loops, etc. Develop and maintain automated test scripts and frameworks (primarily in Python) ### Staff Front-End CAD Engineer, Silicon - Google - Location: San Diego, CA, USA; +1 more (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcken8ij5W_Kh3XMmz1jbl9ZBAN10Fgwmgx7s4lf1nLTATEjsACxwdTKysliKmgKuPRbfirPBZjsSCulpxsZj5NVLyBlA1xStkTzm6szSyNLpdkEd4cPWktNF6SC-Olw%3D%3D_V2&loc=US&title=Staff+Front-End+CAD+Engineer - Excerpt: Staff Front-End CAD Engineer, Silicon San Diego, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the Front-End CAD team, you will be responsible for developing CAD flows or tools for custom SoCs built for Google made devices. You will have a thorough understanding of very large scale Integration (VLSI) design and software skills and will be able to apply them to meet design goals. You will be working directly with designers to understand their needs and building efficient solutions that scale across multiple projects and nodes. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop front-end CAD tools and flows for Google Silicon SoC projects in various domains (RTL generation, design verification, AI-enabled CAD flows, design/IP quality assurance and release management, design spec management, internal CAD tool development, etc.). Work with design teams to understand requirements and enable scalable and efficient CAD solutions to improve design quality and productivity. Work across functional domains to enable development and validation of CAD flows. Drive EDA vendors to improve their tools to deliver custom solutions for Google. Understand ### ASIC Silicon Design Verification Engineer III - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWO3j1z1lKO6Zj608yfVOzSIYH1iGAw7ESi3dNtwZ4CXEjsACxwdTN60iH52gJ0_w30kg7IHVTJGJmeRocgxh3aUInkx4216lDIUPeuwTgdhcEYgxtxEbrlqkpvquQ%3D%3D_V2&loc=IN&title=ASIC+Silicon+Design+Verification+Engineer+III - Excerpt: ASIC Silicon Design Verification Engineer III Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As the ASIC Silicon Design Verification Engineer, you will lead the development of verification content and drive hardware-software co-verification strategies. You will focus on bridging the gap between RTL simulation and emulation platforms. The world is shifting from AI-enabled to AI-native, and this transformation lies in the Tensor Processing Unit (TPU) powering the Pixel phones. You will be the guardian of the compute power that fuels global innovation from Large Language Models (LLMs) to personalized AI assistants. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is easy to use. Minimum qualifications: Bachelor's degree in electrical engineering, computer engineering, computer science, a related ### SoC Input Output Architect, Silicon, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdDWKVaXP6SHQ1_oondP8yUFiWvNaf9qV0RTV6RD1vbcEjsACxwdTGFrJhNka3SSkoVym3LIHJj1LVJiOqtDryNrzlCt6u74jRO4YQATfV74pmdbDUyZZi1EMxCzTg%3D%3D_V2&loc=IL&title=SoC+Input+Output+Architect - Excerpt: SoC Input Output Architect, Silicon, Google Cloud Tel Aviv, Israel; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Google's Silicon team is driving the future of cloud data center computing. As a System on Chip Input Output (SoC IO) Architect, you will help define a new generation of Google's products. You will have pivotal responsibilities and serve as the organization Mobile Industry Processor Interface (MIPI) focal point. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of ### Imaging and Display Silicon Architect, Android XR Ecosystem - Google - Location: San Jose, CA, USA; +1 more (unspecified) - Salary: $188K-$275K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTZEtJC3kGdA1hn6NbFqT89ZMAbfVANDhH8jgUhTZmpDEjsACxwdTLZfb_XKPDCi6sIde7hw4Ni7UMHFddMJgofDUFIHcTRb-GyAp1Mc9fRVOSh4XKQHpJN9BSekNA%3D%3D_V2&loc=US&title=Imaging+and+Display+Silicon+Architect - Excerpt: Imaging and Display Silicon Architect, Android XR Ecosystem San Jose, CA, USA; +1 more The Android XR Ecosystem team is the engine responsible for accelerating the mass adoption of spatial computing. To win, software and silicon must evolve as one. In this role, you will be responsible for defining and architecting the overall architecture of camera systems, graphics, video, and display pixel processing across AR/XR products. You will provide thought leadership in architecting the end-to-end pixel processing pipeline subsystem including the platform architecture for ISP/Camera system, Display pipeline requirements, architect cutting edge Graphics and Video pipelines and addresses system level topics like camera synchronization, motion to render to photon latency, sensor road-maps and display re-projection hardware engines for next gen AR and XR products. You will ensure all components work together effectively to meet performance, power, and cost goals for all CUJs. You will be understanding the entire pixel processing pipeline, from sensor to final image/video output for human or AI consumption and cross-functional collaboration internally and externally with silicon vendors, technology partners and image sensor vendors. For decades, the computing revolution has reshaped our world driven by breakthroughs in compute, connectivity, mobile, and now, AI. Google's XR team is at the forefront of the next major leap - the convergence of AI and XR. This is more than just new devices - it's about reimagining how we interact with the world around us. We're building a future where lightweight XR devices like smart glasses and headsets pair with helpful ### ASIC Power Management Architect - Google - Location: San Diego, CA, USA; +1 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckfMIr5UXoBF-CXRwnni75OpRyImKX2xNfBO_x8wXaf_-EjsACxwdTClKr6TfKz7THQNVfGNA5_8c8aqCdrgZyzcTkAyKhfrPifHxmeUZ4BiihQ40mc0HFxvQxJalhg%3D%3D_V2&loc=US&title=ASIC+Power+Management+Architect - Excerpt: ASIC Power Management Architect San Diego, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Drive architectural analysis for mempath traffic patterns, from collecting silicon traffic patterns for key tensor CUJs, to mapping them to pre-silicon CUJ estimates and closing correlation gaps. Oversee end-to-end correlation from pre-silicon micro benchmark power estimates to CUJ modeling estimates, with a focus on architectural assumptions used for modeling. Propose architectural features/requirements for mempath to improve overall Key Performance Indicators (KPIs). Perform algorithm development, modeling, and analysis of various architecture approaches. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 8 years of experience with ASIC power management architecture. Experience ### CPU Performance Architect, Silicon - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdtuOMydu_YI4ABvNoKFaYXjpjqsG9fCmAF7eiArvXK1EjsACxwdTFZ6S_YMUM8rXniIk5sfg1AJGiACWwG8gV5Rsw0tkreaRrGuITB_kRTVsP6eKcVk0KUqU-MRkg%3D%3D_V2&loc=TW&title=CPU+Performance+Architect - Excerpt: CPU Performance Architect, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more As a CPU Performance Architect, you will be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and deliver Google's advanced SoC products. You will collaborate cross-functionally with android applications and AI teams to conduct applications and benchmark performance analysis and to project their performance at various design phases. You will be guided by architects and work with engineers in Power, Thermal, Security, and Physical Design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop and modify a performance model for performance analysis and microarchitecture study. Evaluate Advanced RISC Machine (ARM's) architecture features from both architecture and performance angles. Define and write CPU subsystem architecture specifications. Collaborate with Register-Transfer Level (RTL), design verification, and physical design teams to develop a high-performance and efficient CPU implementation. Manage performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering or Computer Science, with a focus on computer architecture, or equivalent practical experience. 4 years of experience in microprocessor ### Senior ASIC RTL Engineer, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSBRDDxQYFWWu0g0PTlndGqFDVjeSfl7R2ge6f47a7zAEjsACxwdTHwBgoE_-XkQRExGQxlgt_0MQOgz3OYVVPskQcR2CULp-irjTcYeNNpS9zb3ONMx7hfJoYUDRQ%3D%3D_V2&loc=IN&title=Senior+ASIC+RTL+Engineer - Excerpt: Senior ASIC RTL Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Own and execute the RTL design and micro-architecture for high-performance Fabrics and Network-on-Chip (NoC) subsystems from concept to tape-out. Write production-quality SystemVerilog code for complex logic including credit-based flow control, asynchronous bridges, and cache coherency controllers. Debug complex silicon issues and architectural bugs by digging into waveforms and gate-level simulations. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's degree or PhD in ### Senior ASIC RTL Integration Engineer, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXIUI4oiiQS96O2ZETQ-CwsqXvmrJAwFa2k9ZeXarSeNEjsACxwdTMt8wl6OJaXQm9f5Vn_oGMk-NWe3aMMl_J8XA3txOEEVHZwHBKlObigM44E1Tq4SwsVS5V5AIw%3D%3D_V2&loc=IN&title=Senior+ASIC+RTL+Integration+Engineer - Excerpt: Senior ASIC RTL Integration Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Clock Domain Crossing (CDC)/Formal Verification (FV)/Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience with digital logic design principles, RTL design concepts, and languages, such as Verilog or SystemVerilog. 8 years of experience with multiple IPs/SoCs with silicon success. Experience with logic synthesis techniques to optimize RTL code, performance and power, as well as low-power design techniques. Preferred qualifications: Master's or PhD degree in Electrical Engineering, Computer Engineering ### Performance Architect, Use Case and Workload Analysis - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYpvL4mtIbm0jlQqWAbSQXsWgl4kATNKnTubLHhLfkjXEjsACxwdTHoMBTAhM8hgxlLg8ytVVcozQoMW2tuy_6QjKVSOR4ZpGQeZj4THD82l25NY09QR5rXoKP1mag%3D%3D_V2&loc=TW&title=Performance+Architect - Excerpt: Performance Architect, Use Case and Workload Analysis New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Conduct CPU power and performance correlation. Conduct CPU workload analysis and optimization on real use cases and commercial benchmarks. Drive post-silicon characterization and failure analysis for next-generation CPU and memory systems, focusing on optimizing F_max/V_min boundaries and root-causing complex silicon-level bugs. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience in embedded system software development, test and debugging. Experience in programming (e.g., Python, or C/C++, Shell script). Experience with Android/Linux environments. Preferred qualifications: Experience in silicon characterization, system-level test (SLT), chip bring-up, hardware debugging, and failure analysis (FA). Expertise in performance and power analysis for CPUs, GPUs, TPUs, interconnect fabrics, and memory systems, including QoS tuning and bandwidth/latency analysis. Knowledge of OS kernel-level optimization, including schedulers, ### Lead, Intellectual Property and Electronic Design Automation Sourcing - Google - Location: Austin, TX, USA (unspecified) - Salary: $236K-$330K - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTo1S0CNhLsO16mA6bLJ-pOUQUJhFHmHbXEqbQQDvm00EjsACxwdTNOyzW7reHUmHeESibsT60oBDosQBzweXsMQlblS2E9xrvvH3Bx7ce2WWM5kszbDIL7IILduOA%3D%3D_V2&loc=US&title=Lead - Excerpt: Lead, Intellectual Property and Electronic Design Automation Sourcing Austin, TX, USA Commodity Managers work with Engineering teams to make sure Google has the supplies and equipment to put into production the innovative products coming from our Engineering teams. As a Commodity Manager, you use your wide industry knowledge and strategic supplier relationships to optimize our total cost of ownership for our global -- and growing -- infrastructure. The scale at which Google operates means that savings on just one piece of hardware can have a huge impact on Google's bottom line. In this role, you will join the Silicon Sourcing Center of Excellence (SSCE) to support our AI and cloud infrastructure. You will connect hardware engineering and global supply chain execution by managing the commercial life-cycle for silicon operations. You will source standard compute and custom AI accelerators (TPUs), direct partnerships, and execute early-stage strategic investments to secure resilient supply, generate cost efficiencies, and support Google's technology roadmap. The Lead for IP and EDA Sourcing is the strategic architect of the commercial frameworks that allow Google's silicon engineers to design chips. You will manage the foundational "Enablement and Tools" pillar, ensuring Google has the most advanced third-party Intellectual Property (IP) and Electronic Design Automation (EDA) tools at the most enaged costs. Without this role, the technical roadmap for TPUs and gSOCs is stalled by licensing bottlenecks, misaligned tool integrations, or prohibitive NRE (Non-Recurring Engineering) costs. Behind everything our users see online is the architecture built by the Technical Infrastructure team ### Memory System Architect, Silicon - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZMNBVC8P6WO9SXv6PBmgcDXax2Y60oYMsF_yZmM9udSEjsACxwdTAYrZ_w4LzN44wKxWCM2Hkq6ZF0OvpOaGtGufk3CEHog-z5_9kkED5SUOM01auYg2WCBdUjWBw%3D%3D_V2&loc=US&title=Memory+System+Architect - Excerpt: Memory System Architect, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will shape the future of our coherent memory systems for consumer SoCs. You will leverage your technical expertise in design and uArch to create the most advanced power- and performance-efficient mobile coherent systems. Your work will have a direct impact on the performance, efficiency, and innovation of our next-generation devices. You will work with hardware designers and validation teams to build and test exceptional hardware architectures. As part of this work, you will participate in the development of technology in the memory system and the filing of associated patents. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Explore and evaluate different uArch and design choices for ### Factory Applications Engineer (Silicon Photonics; North Reading, MA) - Teradyne - Location: North Reading, MA (unspecified) - Salary: $127K-$127K - Posted: 2026-06-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-Factory-Applications-Engineer-%28Silicon-Photonics-North-Reading%2C-MA%29-MA/1392212800/ - Excerpt: Factory Applications Engineer (Silicon Photonics; North Reading, MA) North Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview The Teradyne Factory Applications group is looking for a highly motivated, energetic, and self-driven engineer to join our Silicon Photonics product team. You will work on projects collaboratively with cross-f ### Administrative Business Partner, Cloud Silicon Organization (English, Hebrew) - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXa33mSsnhi3EVGfPS4NTk6ZFkDpYVW6WJVN1ui3erlkEjoACxwdTNqjrmuM-myHylIZ_3o1GdAhoUDZV9CAKpFCmLz6d7F2LH5GK0r84lsh5v9VUwM9CjoO7nRV_V2&loc=IL&title=Administrative+Business+Partner - Excerpt: Administrative Business Partner, Cloud Silicon Organization (English, Hebrew) Tel Aviv, Israel; +1 more As an Administrative Business Partner, you're at the heart of your team's business operations and activities and the soul that keeps your team moving forward. You anticipate the needs of your managers and team members and help them stay focused on their projects by resolving operational and administrative issues before they arise. You move quickly with the changing environment and are up to date with the latest Google products and services. You also use that knowledge to strategically support your team's projects. In addition to being organized and analytical, you possess the strong business judgment and communication skills needed to interact with a variety of people and job functions. Administrative jobs at Google are staffed by organized and dependable people driven by a common company goal: to help us accomplish great things. Working behind the scenes, we make a significant impact on the people we support as well as on Google users around the world. We're adept at leading and managing a variety of simultaneous projects, which requires the particular talent of being able to communicate effectively with all levels of the organization. Perform administrative tasks, including calendar management, travel arrangements, and expense reports. Act as a partner and proxy for the Cloud Silicon Organization Israel leadership team, attend meetings, participate in projects, and make decisions on their behalf as needed. Plan, manage, and execute team and site-level offsites, events, and activities, from pre-planning through to budget ### Machine Learning Hardware Architect, Google Cloud Silicon - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSb5Ztykt9GDsvh6yLbwO-evuOGmXD_5EQqAaQPmH2tWEjsACxwdTMl4OZe1mY6_aHFFTY-l0no3ftkwoAKkPJ4hydQVfwpgzbzzWGcZKYmHXc2zpuD1TP7jbFTpkw%3D%3D_V2&loc=IL&title=Machine+Learning+Hardware+Architect - Excerpt: Machine Learning Hardware Architect, Google Cloud Silicon Tel Aviv, Israel; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own and lead the architecture of the Google Edge AI accelerators. You will work with the Google AI community and with external partners. You will combine the latest innovations in Machine Learning and integrated circuits to create advanced hardware acceleration solutions for Machine Learning training and inference. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on ### Silicon Senior uArch/RTL Engineer, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckY0pPyYYY6CTrUrB1t9oeR3UU0YP0HDQkOcu83kukfF7EjsACxwdTM1wlXYhgwHvyjKNX6Ryo-e6K3C1DC8Bk4imo_YM_0piTb2VhYmMZDIKWQykkP1cLyc93T9Qdg%3D%3D_V2&loc=IN&title=Silicon+Senior+uArch/RTL+Engineer - Excerpt: Silicon Senior uArch/RTL Engineer, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing SoCs used to accelerate Machine Learning (ML) computation in data centers. You will solve technical problems with innovative and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. You will collaborate with members of architecture, verification, power and performance, physical design etc. to specify and deliver high quality designs for next generation data center accelerators. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Own microarchitecture and ### SoC Test Hardware Engineer, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-20 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckfvvArJS2zOkrgzC1k6G7sAPPovlV0qsiStTbONFlvdsEjsACxwdTHwJda_iQMhCStDh-g5d51p_jHvqF-nOzY1QFo-SFlZjoc13ZlHHs4l2tcwAVKyeG5UPHrr0Hw%3D%3D_V2&loc=IL&title=SoC+Test+Hardware+Engineer - Excerpt: SoC Test Hardware Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will help to manufacture the SoC's that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and OSATs. This is an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You will help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will have an understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will help design, deploy and maintain hardware required to screen high performance compute silicon at various stages of the manufacturing pipeline. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of ### Technical Program Manager, Silicon Development - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXGk4MZCsPlNvu8-t1GbneMvgwGgOMIxZN8n981NaD8OEjsACxwdTADThlAtgko6-K_4G1CirApzIJLfY45SFlOi18wGw55SU2-Hqpe4wQ6Sc0gSD75ewXR6WW_qSA%3D%3D_V2&loc=IN&title=Technical+Program+Manager - Excerpt: Technical Program Manager, Silicon Development Bengaluru, Karnataka, India A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. In this role, you will use the technical and management experience to lead the development and execution of multidisciplinary System-on-a-chip (SoC) projects. You will plan programs and manage their execution from concept through development to tape-out and production. You will collaborate with architecture, design, verification, physical implementation and manufacturing teams throughout the SoC execution life-cycle. You will be making technical decisions for the chip designs and methodology, driving project schedules, identifying risks and communicating them to all stakeholders, and managing partner teams. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Justify, plan, coordinate, and deliver custom silicon products. Generate ### ASIC Digital Design Engineer II, Silicon Engineering - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcHsrgwWN7Y2d6pNVVICVe2b0jfdsrwKnS2Duw_RfL4yEjsACxwdTM8PdhjKksREzrwUS05bAsHYIsnAM0j18suBmBOP_jXW3Qr7CK8ogRakyjXMqLc743ndvIUFPg%3D%3D_V2&loc=IN&title=ASIC+Digital+Design+Engineer+II - Excerpt: ASIC Digital Design Engineer II, Silicon Engineering Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will be a part of the team which designs the Tensor Processing Unit (TPU) core and sub-system. The TPU core is the heart of Google's Tensor SoC. You will be working through all phases of design and implementation. You will be working with Architects to come-up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/proto-typing experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical design (PD) team to take the design through PD cycle and eventual tape-out. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Use simulation/emulation/power analysis tools and techniques to ### Silicon Micro-architecture and RTL Lead, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-04-28 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXiAZPQspEkwABvZ6BujZJltNS3E2m7WTxg4dUcXd9YtEjsACxwdTOYq9JSIqkGURs04FP8E5uhd97AQRZrIk6iLNW1H1k9NQg2lg39195nHmwKBIQxKVHgGCZBpRA%3D%3D_V2&loc=IN&title=Silicon+Micro-architecture+and+RTL+Lead - Excerpt: Silicon Micro-architecture and RTL Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to ### RTL Design Engineer, Google Cloud, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRdZcO5rQorwYsIKOXpPSknn10hl8Ydg2e55Pks_qKHgEjsACxwdTHFCJSO5ha3tKkQZ-1dfKUwcSbh4GVdNJqG3PDmoETP6LnpPwhrRoMIJrLAAOg1J_u6u1kui-A%3D%3D_V2&loc=IN&title=RTL+Design+Engineer - Excerpt: RTL Design Engineer, Google Cloud, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Own microarchitecture and implementation of Internet Protocol (IP) and subsystems. Work with Architecture, Firmware, and Software teams to drive feature closure ### Silicon SoC DFT Technical Lead, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckeOLtcKsALKSvQaFNUeIZfSImIdoxh7iYdRWc-Ym1rOREjsACxwdTKTCMkSYGNObmfBxVrokX_S3iEEeeki7lYZYO1N0mME7Tx7gmV6F_vqWOmCAFNpmE-2WjiQ9XQ%3D%3D_V2&loc=IN&title=Silicon+SoC+DFT+Technical+Lead - Excerpt: Silicon SoC DFT Technical Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, functional BISTs, Analog components, logic BIST, high-speed I/O loopback, and ### Silicon Architecture/Design Engineer, PhD, Early Career - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2025-10-17 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckb3OaXPtqBqv0PhifuQNaKlpdTt93PFHhckMk9lsTfGlEjoA7mFcrJUqTs11haUuK4Vzu1fyGTWRMpjrXaICOTWsT1VJPqrDhbmUv7I6Vr0F1YAX6AF0YrjrrQoG_V2&loc=IN&title=Silicon+Architecture/Design+Engineer - Excerpt: Silicon Architecture/Design Engineer, PhD, Early Career Bengaluru, Karnataka, India In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive cutting-edge TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and ### Silicon SoC Integration Design Lead, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckX8jvwKb6wpl2fQ-znYkUFJYigKRxSIBz8pIlIVqxdMZEjsACxwdTAYR-rnkO34pTjinfxpcNaW-3r-RpA9RHG9-ppfaTyjFAYD9FAb1JkoFiG5E4kmWYW7y-5fuTQ%3D%3D_V2&loc=IN&title=Silicon+SoC+Integration+Design+Lead - Excerpt: Silicon SoC Integration Design Lead, Google Cloud Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Lead SoC/SS integration team. Drive development of complex IPs and Subsystems along with a team of engineers in the Bengaluru design organization. Own microarchitecture and implementation of IPs and subsystems. Work with Architecture, Firmware and Software teams to drive feature closure and develop microarchitecture specifications. Drive design methodology, libraries, debug, code review in coordination with other IPs Design Verification (DV) teams and physical design teams. Identify and drive Power, Performance and Area improvements for the domains owned. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in ASIC development with Verilog/SystemVerilog, VHDL, or Chisel. 5 years of experience in micro-architecture and design ### Senior Silicon DFT Engineer, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVL1mKFoIQ3FJc8pxoDAgERcxFO-t6_9vEDmWJ4H6mVVEjsACxwdTGeeTnyUWCDEYnGPQjswNT7Wmfqh0cgE3WawtIsE-7YneA2vKqbmif9t_KzxnJWd99pOCngong%3D%3D_V2&loc=IL&title=Senior+Silicon+DFT+Engineer - Excerpt: Senior Silicon DFT Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will play a crucial role in Design for Testing (DFT) Architecture and DFT design, and support devices of extreme complexity to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality matrix throughout the project life-cycle, and providing sign-off DFT to tapeout. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Lead and execute activities in the design, implementation, and verification of DFT solutions for large-scale ASICs. Develop DFT strategy and architecture, including hierarchical DFT, Memory Built-In Self Test (MBIST), ### ASIC Design Verification Engineer, Devices and Services, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUB0aRQyIw13dcVjTRVKDt-xlOWJjuRumd6rF-husLryEjsACxwdTJq6Db-HfcQQKT9sLiOG4X-d2d29dqr0qcW3u8-cmJn_ZD7JL1nBn9sEbYvHEdyoYkwA7tPPpg%3D%3D_V2&loc=IN&title=ASIC+Design+Verification+Engineer - Excerpt: ASIC Design Verification Engineer, Devices and Services, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will work in the verification of Google's SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP, interconnects, caches, memory management and system services. You will also work in developing high performance VIPs for protocols supported by our SOCs, and closely collaborate in the deployment of the verification stack across a heterogeneous set of IPs.You will build and verify a generalized class of system topology abstractions, and develop the associated methodologies and tools needed to solve the problem.The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Verify designs using verification techniques and methodologies. Work cross-functionally to debug failures and verify the functional correctness of the design. Provide test plans, including verification strategy, environment, components, stimulus, checks, and coverage, and ensure documentation is ### Tensor SOC Performance Design Verification Engineer - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYimJe0yWahAsUhEm1inLXqAEFfUq5w2jNInfDOdzV1MEjsACxwdTHo_glOJ9K36CEG8Hg_zzRA0wlA6jG6aHAkuZkDjBxu1eG3ZmqvTsRbYuopjhou5g3vpHTsCiw%3D%3D_V2&loc=IN&title=Tensor+SOC+Performance+Design+Verification+Engineer - Excerpt: Tensor SOC Performance Design Verification Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop simulators and architectural models of Google's Tensor SOC. Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements. Participate in architectural and design evaluation of Tensor SOC features studies. Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements. Communicate analysis results qualitatively and quantitatively. Minimum qualifications: Master's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience. 4 years of experience in the SOC design/verification. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level. Experience in mobile SOC performance model development, performance analysis, and workload characterization. Preferred qualifications: Experience in CPU microarchitecture innovation. Knowledge of system software components, such as Linux, drivers, and runtime. Knowledge of performance analysis tools. Knowledge ### Senior Silicon Physical Design Engineer - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2025-12-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcEmKw3OqCFQjNCd4HdZzERM6VJ1TALxcKuWEl9dOcK-EjsAvkGZm1vEX_yavFl_ZfZQwpnAYOQ9dnoNy3uz_4XMKzM4htTphNwR5OQcsn_0LABreM6jIaV9Q-VSQQ%3D%3D_V2&loc=IL&title=Senior+Silicon+Physical+Design+Engineer - Excerpt: Senior Silicon Physical Design Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements. Collaborate with cross-functional teams to debug failures or performance shortfalls and ### Senior Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings) - Google - Location: Austin, TX, USA (unspecified) - Salary: $165K-$237K - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckf8g8Jg8yKtHUHziWQv8NIcGAoSVASjOlwIz_IlSURm8EjsACxwdTGc-4OcE5AWaU6hVGN2Uc3ystVivcuHdtXkSdySLO39GKQUNNEbmIHqiPPVavSnzHpQBunpN1w%3D%3D_V2&loc=US&title=Senior+Silicon+Engineer-+P+and+D- - Excerpt: Senior Silicon Engineer- P and D- (gCPU), Design Verification (multiple openings) Austin, TX, USA Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. The US base salary range for this full-time position is $164,550 - $237,000 + 15% Bonus Target + equity + benefits determined by role, level, and location. Individual pay is determined by additional factors, including job-related skills, experience, and relevant education or training. Learn more about benefits at Google . Position reports to the Google Austin, TX office & may allow for a hybrid schedule as per Google policy. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users ### Analog Design Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA; +1 more (unspecified) - Salary: $240K-$334K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYCj9rag0qNUfT4jiwQPcJdUlNx5k3dyW9T57tAQ2cHoEjsACxwdTCOlPbJCCdjLHZXLXY-L0pwEzUg8d68Z9nwSS9tKGRhXUf714e_QbTTlTXbbguFpxp2Ca8tcEA%3D%3D_V2&loc=US&title=Analog+Design+Engineer - Excerpt: Analog Design Engineer, Google Cloud Sunnyvale, CA, USA; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Analog Design Engineer, you are the silicon strategist, defining the architectural path from high-speed electrical interconnects to Co-Packaged Optics (CPO). You will set the technical direction for Google's silicon in the 1.6Tbps era. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and ### Silicon Design Verification Engineer, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVgkmkyFsC3rsCs6l6Yig8g2VjqNa2LYL_0bu6PPRWJWEjsACxwdTPz5kEgI13KmaiAYaJA4gWBYAG8Vxyw_5iFVtUf-uWgOrd6OqCLEEXVF4wF_15A4vKVt_5MAUw%3D%3D_V2&loc=IN&title=Silicon+Design+Verification+Engineer - Excerpt: Silicon Design Verification Engineer, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our ### Design Verification Engineer, Google Cloud Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZ7bb4v8TPkD0G92Tyk7g3DyXEFocMwKtaFzWxB5twVREjsACxwdTEWg9IfNuhwxmIl4r6c2pKhTvObuy7xHzkS1z5rXm3y3dDcOtN39iGbmJJaQVw8BL_FdEWfcIQ%3D%3D_V2&loc=IN&title=Design+Verification+Engineer - Excerpt: Design Verification Engineer, Google Cloud Silicon Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware ### SOC Performance Engineer, Google Cloud - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-13 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdSwSijgWOiuk0tSY-XFquVcg8k-sFjiEOO6i8hbF76NEjsACxwdTIHjoxA5CPA_kR7RqbajisZMekFNs7C_p8byJskTM_DGS-UxRBDHqqTYc0W31j1FjrZxVxcjZA%3D%3D_V2&loc=IL&title=SOC+Performance+Engineer - Excerpt: SOC Performance Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Utilize performance and power models from the architecture team, as well as lab measurements, to validate and tune performance against established goals. Design and build tests to verify that the SoC design meets those goals. Develop and implement advanced technologies for running benchmark representations on pre-silicon environments. Analyze complex problems, identify core design weaknesses, and drive the resolution of performance issues in both pre- and post-silicon environments. Develop performance measurement frameworks, including Key Performance Indicators (KPIs), to produce regular reports and dashboards that support stakeholder decision-making. Minimum qualifications: Bachelor's degree ### SoC DFT Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYAh0Tzoil5BTltlmPYTUOqeoefXBlffE6LHalB8y78REjsACxwdTC6H0bv9C_Ta8G94UurJI79NRcts2n-AcG-U15ITjSsOXQiXiPc27PNOZ5uzDjb6k7kZHI-KUA%3D%3D_V2&loc=US&title=SoC+DFT+Engineer - Excerpt: SoC DFT Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a DFT Engineer you will be responsible for defining, implementing and deploying advanced Design-for-Test (DFT) methodologies including scan, MBIST, JTAG and iJTAG, for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT/DFD architecture, and create DFT and debug specifications for next generation SoCs. In partnership with the Silicon Engineering team, you will also be responsible for diagnosing memory and logic failures, increasing production quality, and enhancing yield and reducing test cost. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build ### Software Engineer, Security Backend, Silicon - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan (unspecified) - Salary: Not disclosed - Posted: 2026-05-21 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVg-WLqdgG1gFvRY1mscKbb-vSpBg9nSOBbpO1MVWCADEjoACxwdTEVpFc8rfdNAsTsGuVvcdR4wnnl1E2ZVNEK0qAum7K5dsio97weLvLBYcVPG-larwvUaOeZf_V2&loc=TW&title=Software+Engineer - Excerpt: Software Engineer, Security Backend, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Design and build scalable, secure, and reliable web backend applications to facilitate the entire Silicon development processes and secure manufacturing. Deploy back-end applications, services and infrastructure using Google's backend application frameworks. Monitor traffic, conduct stress tests, and identify performance bottlenecks to ensure ### Senior Silicon DFT Lead - Google - Location: Haifa, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-04 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTY25Nhw2vAzN66W1qg5QyMMzem-P1VgFA1CJzPif01dEjsACxwdTDTXSZ6NRwLq-8FtsnR5LPXVU3Cy-wSjKW2rEUVo-u-1h9VbANELtTIPnZhTMwUyrAxAMc3huw%3D%3D_V2&loc=IL&title=Senior+Silicon+DFT+Lead - Excerpt: Senior Silicon DFT Lead Haifa, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC). Develop DFT strategy ### Senior CPU Performance Architect - Google - Location: Mountain View, CA, USA; +3 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcDcgs4KibHM8gnqti7eRyV-VMbH_5YbBs3u7pKtMsbGEjsACxwdTMcCzwBhN48GztG1hEO3PTvD5y2M7YFpYpMj1zxD8CQ2pqQ5RXWSi3ioNtAkzsU2FfwOHJ9q5A%3D%3D_V2&loc=US&title=Senior+CPU+Performance+Architect - Excerpt: Senior CPU Performance Architect Mountain View, CA, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user's interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Plan and evaluate ARM's architecture features from both architecture and performance aspects. Develop a performance model for performance analysis and microarchitecture studies. Lead collaboration with design and verification teams to develop efficient CPU implementation. Define and write CPU subsystem architecture specifications. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development and pre-silicon and post-silicon performance bug triage. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer ### CPU Global Design Lead, Silicon - Google - Location: Austin, TX, USA (unspecified) - Salary: $240K-$334K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXZrFkf9Jf4lBqfLvcgBoAzgzYT3qouOIu2MycdT5Bo-EjoACxwdTHMzvhDeu2j16cUP_OpQInihTU-KDIT3xCChcpGFX2M4qwd1DeWh60tfueO2j4LKERrdkOl6_V2&loc=US&title=CPU+Global+Design+Lead - Excerpt: CPU Global Design Lead, Silicon Austin, TX, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $240000 - $334000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Participate in developing CPU subsystem. Develop CPU subsystem front-end designs, emphasizing microarchitecture and RTL design for the next generation CPU. Propose performance enhancing microarchitecture features, and work with Software, Architect, and Performance teams for trade-off studies. Communicate the pros and cons of microarchitecture enhancements. Deliver designs, meeting PPA goals with production quality. Work with the Verification team to ensure production of quality designs, and the physical design and power teams to meet frequency, power, and area goals. Become familiar with modern techniques, interpret the techniques into design constructs, and languages in order to provide guidance to and participate in the performance evaluation ### Performance, Power and Thermal Architect, Silicon - Google - Location: San Diego, CA, USA; +1 more (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU56Ic-wKW3fkOAAkYPPOAUmasNi85u4mVEoA3yjPVmJEjsACxwdTJY6mWLoWTbzLZIhoUhQXUGDsMB_SYd2RfzqJWleOpgwOqsX0gCJz23XrwP-vEOHlRV-5H0uEQ%3D%3D_V2&loc=US&title=Performance - Excerpt: Performance, Power and Thermal Architect, Silicon San Diego, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Performance, Power and Thermal Architect, you will help drive Mobile SoC Architecture optimized for Performance, Power and Thermal. This role will analyze mobile workloads, identify performance bottlenecks and power optimization opportunities in hardware/software architecture, and work with cross-functional teams to implement these solutions. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $138000 - $198000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Conduct performance, power, thermal analysis in both qualitative and quantitative fashion effectively. Identify performance bottlenecks across workloads on Mobile SoCs and suggest potential optimizations to improve Performance/Power. Identify software and hardware architectural optimizations for mobile/tablet workloads (ML/Gen-AI, Browsing, Camera, etc). Evaluate architectural options, trade-offs (CPU Cache sizing, Core configuration, Memory controller QoS, ### Junior SoC DFT Engineer, Google Cloud - Google - Location: Haifa, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRPgGwEh9upSlqlIYcsjMtdxB2Z5L2qfZAVyOasa0yfZEjoACxwdTE5Xs-p4ryQcsf6mwBdFEHHd_qYujiwrydRVC_79rCEBZY1xvGgYI7TGSna0fyqqvxmg9poQ_V2&loc=IL&title=Junior+SoC+DFT+Engineer - Excerpt: Junior SoC DFT Engineer, Google Cloud Haifa, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a System on a Chip (SoC) Design for Testing (DFT) Engineer, you will be responsible for defining, implementing and deploying advanced DFT methodologies for highly digital or mixed-signal chips or IPs. You will define silicon test strategies, DFT architecture, and create DFT specifications for a CPU. You will design, insert and verify the DFT logic.You will prepare for post silicon and co-work/debug with test engineers. You will be responsible for reducing test cost, increasing production quality and enhancing yield. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG). Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality. ### Software Engineer Manager II, Silicon Tools - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan (unspecified) - Salary: Not disclosed - Posted: 2026-05-19 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckY-AHArLKNqMez7nd7-lATp-zYtZ5kbwU59O7D3bp54wEjsACxwdTDLTqI-XL9WNWvJwKhiA43CVhjw3pPgdOq9mD77NkGx5uMhlXquzLAoHk421AHDofGevFk6x1A%3D%3D_V2&loc=TW&title=Software+Engineer+Manager+II - Excerpt: Software Engineer Manager II, Silicon Tools New Taipei, Banqiao District, New Taipei City, Taiwan Like Google's own ambitions, the work of a Software Engineer goes beyond just Search. Software Engineering Managers have not only the technical expertise to take on and provide technical leadership to major projects, but also manage a team of Engineers. You not only optimize your own code but make sure Engineers are able to optimize theirs. As a Software Engineering Manager you manage your project goals, contribute to product strategy and help develop your team. Teams work all across the company, in areas such as information retrieval, artificial intelligence, natural language processing, distributed computing, large-scale system design, networking, security, data compression, user interface design; the list goes on and is growing every day. Operating with scale and speed, our exceptional software engineers are just getting started -- and as a manager, you guide the way. With technical and leadership expertise, you manage engineers across multiple teams and locations, a large product budget and oversee the deployment of large-scale projects across multiple sites internationally. This role requires a blend of technical expertise in embedded systems and the leadership skills to manage complex Hardware/Software (HW/SW) co-design projects in a fast-paced environment. As an Engineering Manager, you will lead the Debug/Trace/Analytics (DTA) Tools team in Taipei. You will manage a group of engineers dedicated to building the next generation of debug and analytics tools for Google's custom silicon (e.g., tensor) providing a comprehensive suite of host-side profiling tools that ### Senior Design Verification Engineer, Multimedia/AI/ML, Silicon - Google - Location: Mountain View, CA, USA (unspecified) - Salary: $163K-$237K - Posted: 2026-06-10 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckfX6WgAHGwUTQ8VP8uIh1439AoiOFP52VFfwtqr39rMOEjoACxwdTDNpQLe7UL3tYKjF37ctT4SIRIYbq2l_9HMGbk6MC4txOwNqP44w7wDJHcfZ999aZj6esEMz_V2&loc=US&title=Senior+Design+Verification+Engineer - Excerpt: Senior Design Verification Engineer, Multimedia/AI/ML, Silicon Mountain View, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Work with designers, architects, and other stakeholders to come up with detailed test plans, dependencies, and deliverables, while representing DV status throughout the development process. Plan the verification of multimedia design blocks at subsystem level by understanding the design specification, and interacting with architecture and design engineers to identify important verification scenarios. Work with architecture, software, design, and back-end implementation stakeholders to make technical decisions. Create and enhance constrained-random verification environments using system verilog and UVM. Identify and implement improvements to the verification methodologies. Identify verification gaps and demonstrate advancement towards tape-out through comprehensive coverage metrics. Debug tests with design engineers ### SoC Chip Architect, Google Cloud, Silicon - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-05-19 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdxaTPuO68Aa2AMVNa0S3e3fjzbO0t62R4vE3UvVMlluEjsACxwdTMxHP10cHE6Y-b2dhSavUoesj7XOzIdEmxdRBhz1dqjJk1W6wkP8xWOpxNkbAIki69Lhk5cQ9w%3D%3D_V2&loc=IL&title=SoC+Chip+Architect - Excerpt: SoC Chip Architect, Google Cloud, Silicon Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will work to shape the future of an Edge-AI product, bringing high-performance intelligence to the edge. You will have an opportunity to drive distributed inference technology that powers real-time systems where latency and reliability are mission-critical. You will be part of a team that pushes boundaries, developing autonomous solutions that define the next generation of intelligent infrastructure and hardware for the edge. You will contribute to the innovation behind products that transform industries, leveraging your expertise in system-level integration and localized processing to deploy AI models across sophisticated hardware platforms, ensuring intelligence is embedded exactly where the action happens. As an SoC Architect at Google, you will lead the definition of a groundbreaking first-generation product family. You will bridge the gap between high-level system requirements and detailed chip implementation across domains, collaborating with cross-functional partners to design scalable, energy-efficient, and feature-rich IO SoCs. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the ### CPU Architecture and Performance Architect - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckcc6-vUeEEArS2izVXTcX1RH7Yk4EWRI28rZfXwldVBfEjsACxwdTE-syAH_u01lrbYh1SeP8bVP0cIvBVE2mzL7TEJds9yXASCugow6wfr6UrMeepf7rPGIP4oanA%3D%3D_V2&loc=TW&title=CPU+Architecture+and+Performance+Architect - Excerpt: CPU Architecture and Performance Architect New Taipei, Banqiao District, New Taipei City, Taiwan Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a CPU architecture and performance architect, you'll be the key contributor to improve processor instruction set architecture, to develop innovative microarchitecture features, and to deliver Google's advanced SoC products. You'll have the opportunity to collaborate with talents in system performance and software teams to plan and conduct application and benchmark performance analysis and to project their performance at various design phases. Leveraging your CPU-specific knowledge and leadership, you'll be guiding junior CPU architects and working with engineers in power, thermal, security, and physical design teams to determine the CPU subsystem configuration and features. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Drive performance correlation between the performance model and RTL implementation, including micro-benchmark development, pre-silicon performance correlation, and post-silicon performance analysis and debugging. Plan and evaluate CPU architecture features from both architecture and performance angles. Develop a performance model for ### Silicon Physical Design Engineer, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-27 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWok3CxHAC6XnI-YFrG1RBFHuCWTtxoff4viQBmN6NuDEjsACxwdTNUxjcHFmKm3RvM0pLsxTLp_HiySIn1WCjimdVgZI-treFkn3covLkQcmoAPmwjxVgZQ3OX7mw%3D%3D_V2&loc=IN&title=Silicon+Physical+Design+Engineer - Excerpt: Silicon Physical Design Engineer, Google Cloud Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Take ownership of one or more physical design partitions or top level. Drive to the closure of timing and power consumption of the design. Contribute to design methodology, libraries, and code review. Define the physical design related rule sets for the functional design engineers. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 4 years of experience with physical design. Experience with System on a Chip ### Design Verification Engineer, TPU, Silicon, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdXcGaa-HQPyMg6Ys3RVC9GrqJorpo-DJSLXfKCC-zY6EjoACxwdTFe452vsL-i-XrK9Qs0AZMPoI_UzO9aIVDtbr5_GYt3_HyJ4uRVMaBRe6_thYRLw6cRaqSlf_V2&loc=IN&title=Design+Verification+Engineer - Excerpt: Design Verification Engineer, TPU, Silicon, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own the full verification life-cycle from verification planning and test execution to coverage closure, with an emphasis on meeting stringent AI/ML performance and accuracy goals, build constrained-random verification environments capable of exposing corner-case bugs and ensuring the reliability of Artificial Intelligence/Machine Learning (AI/ML) workloads on Tensor Processing Unit (TPU) hardware. You will collaborate closely with design and verification engineers in active projects and perform verification. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our ### ASIC RTL Engineer III, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-19 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYpGadnwFrCxIRH2UMkhWyNCMxCjVAGVA6aWToBIpAPCEjsACxwdTFV479vqU9F4HM0FiVlOaWHkxUSgmkvseb_SWFfSDxd1pOKmRT3AsUAbimx9BACtuqm2yxWOjw%3D%3D_V2&loc=IN&title=ASIC+RTL+Engineer+III - Excerpt: ASIC RTL Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical ### CPU Design Verification Engineer - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-03 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYkQ3l5sGy5qPxFcJIYFqljUQRnW0oMoDS8zlySCdcH4EjsACxwdTK33xa_ydYCBNieS4bgWyCtD-4frcPOWzObiObHuDxm1iHMztcX1mokZjsT4SwJblW_MaIEVoA%3D%3D_V2&loc=TW&title=CPU+Design+Verification+Engineer - Excerpt: CPU Design Verification Engineer New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Design verification for future CPU developments. Build functional verification infrastructure, the infrastructure will include unit, multi-unit, core, and subsystem level verification environments. Produce diagnostic code repositories that enable production of CPU's. Verify and validate performance for both pre-silicon and post-silicon. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience. 4 years of experience with verification methodologies and languages such as Universal Verification Methodology (UVM) and SystemVerilog. Experience developing and maintaining verification test benches, test cases, and test environments. Preferred qualifications: Master's degree in Electrical Engineering, Computer Science, or a related field. Experience with Universal Verification Methodology, SystemVerilog, or other scripting languages such as Python, Perl, Shell, Bash, etc. Experience with ARM Instruction Set Architecture. Knowledge of general purpose operating systems such as Linux ### ASIC RTL Design Engineer III, Silicon - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-29 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckctfJ07tUTpQeO5GkYokwYIhZWi6TNbHV7KE4oGmwV8DEjsACxwdTGqmzN6Yd366t4Wp4IUNC6G4RBm2IHsv2hWPhclDdrAb_VB71S9UwT5PBV3j0_GMaBOXXHjE9A%3D%3D_V2&loc=IN&title=ASIC+RTL+Design+Engineer+III - Excerpt: ASIC RTL Design Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will contribute in creating the micro-architecture of the mobile SOC's subsystems, integrating multiple first-party/ third-party components, and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You will be able to timely deliver Subsystems and work with various cross-functional teams ( DV/DFT/PD/Power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform RTL coding, function/performance simulation debug, and Lint/Cyber Defense Center (CDC)/Formal Verification (FV)/ Unified Power Format (UPF) checks. Participate in synthesis, timing/power closure, and FPGA/silicon bring-up. Participate in test plan and coverage analysis of the block and ASIC-level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer ### Head of Semiconductor Manufacturing Planning and Fulfillment - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckagupPAarwVMDxTsSQv3IHlmMIEXmft_VDPqVtgfXUl-EjsACxwdTA61eJpcj8r1fIdY7zZIjqPQ9ClTVOrOYmwBRHHfX9OVDn4bVGndIu7Cf4DSzXGp8kwSOV5JYA%3D%3D_V2&loc=TW&title=Head+of+Semiconductor+Manufacturing+Planning+and+Fulfillment - Excerpt: Head of Semiconductor Manufacturing Planning and Fulfillment New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more The Google Custom Silicon Operations team is responsible for all external manufacturing engagement and supplier management for the foundry and outsource manufacturing (OSAT) partners for building custom silicon for Google consumer hardware products. This includes foundry/OSAT sourcing, supplier management, end-to-end planning and procurement, and execution of development and manufacturing operations, with our suppliers in partnership with Google Engineering. It includes strategy development and orchestration with key stakeholders to shape the supply ecosystem for better partnership, capacity flexibility, high quality, business continuity, and cost effectiveness. It also includes on time delivery of ASIC (Application Specific Integrated Circuits) and other companion chips. The Head of Semiconductor Manufacturing Planning & Fulfillment leads end-to-end supply chain operations for custom silicon and companion chips within Google's hardware ecosystem. This role is responsible for establishing execution frameworks for supply and demand planning, managing supplier relationships, and ensuring material readiness from NPI through mass production. Key priorities include optimizing inventory visibility, logistics, and financial reconciliation, while driving fulfillment execution (PO management, production control). Additionally, you will report supply risks to executive stakeholders and builds high-performing teams, fostering a culture of accountability and effective cross-functional collaboration. The ideal candidate will possess deep expertise in supply chain planning, semiconductor sub-component manufacturing processes or manufacturing operations management, coupled with strong analytical and problem-solving skills, and a proven track record in managing complex supply chains in a fast-paced environment. Establish supply-demand execution frameworks and ### Design Verification Engineer, Multimedia, Silicon - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTkU62QF1blff88guYEHtmUfe78KQbKjSx2HvGXumgzgEjsACxwdTPhEdNNlyBbucjakQ3100WsCjdrGp2uy3dCKmVn_uI-urDqA1IHBOWWLuiELBwShfY6pPK0uGQ%3D%3D_V2&loc=TW&title=Design+Verification+Engineer - Excerpt: Design Verification Engineer, Multimedia, Silicon New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a diverse team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Plan the verification of complex multimedia digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios. Create and enhance constrained-random verification environments using System Verilog and UVM. Identify and write all types of coverage measures for stimulus and corner-cases. Debug tests with design engineers to deliver functionally correct design blocks. Close coverage measures to identify verification holes and to show progress towards tape-out. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 1 year of experience with verification methodologies and languages such as UVM or SystemVerilog. Experience with object oriented programming. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture, ### Silicon Physical Design CAD Engineer - Google - Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-06-01 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (source-backed) - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaVqc_WTfQFyj9QaPk21Npl7L8tNhqgAQOhRskJ-dyLcEjsACxwdTATWVZnSCVyO7NjRhLARd_Llyfy6cvGeOUQTxxmeRjj8q7LdRxxscKz7KvV_PfSOfvH6RkN3YA%3D%3D_V2&loc=TW&title=Silicon+Physical+Design+CAD+Engineer - Excerpt: Silicon Physical Design CAD Engineer New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a various team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Co-work with project team for a more efficient and effective flow execution and results review mechanism in PDV field. Co-work with the methodology team to define Physical Design Verification (PDV) flow requirements for technology nodes Design Rule Check (DRC), Layout Versus Schematic (LVS), and Programmable Electrical Rule Check (PERC) checks. Import new features, improve job efficiency, and maintain a stable flow in PDV analysis to meet technology and project needs. Provide flow usage and execution support with documentation, training and troubleshooting. Minimum qualifications: Bachelor's degree in Electrical Engineering, a similar field, or equivalent practical experience. 4 years of experience in scripting languages such as Perl, TCL, Shell, or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a similar field. 5 years of experience --- Source-backed benefit claims include source links; other benefit values are labeled separately.