# FewerJobs export - 100 curated jobs
Generated: 2026-09-30T10:19:47.721Z
Source: https://fewerjobs.com

## Filters applied
- **q**: SF Tensor
- **quality_floor**: default
- **match_401k_strict**: true
- **parental_strict**: true
- **non_birth_strict**: true
- **pto_strict**: true
- **include_older**: false
- **apply_url_verified**: false
- **page**: 1
- **per_page**: 100
- **sort**: relevance

## Jobs
### Founding Product Engineer - SF Tensor
- Location: San Francisco | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/sf-tensor/be5d8e5d-de0d-4dd3-be8e-3eb2093ad96f
- Excerpt: Founding Product Engineer San Francisco | OnSite ABOUT SF TENSOR At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. ABOUT THE ROLE We're searching for a Founding Product Engineer who'll own the entire user-facing surface of our training platform: everything from the daily interfaces our users interact with to the systems that make it all run. This role requires taking vague features and shipping them from start to finish. We care just as much about how the product feels to use as whether it technically works. If you're someone who gets genuinely annoyed by janky animations, sloppy spacing, or

### Founding GPU Compiler Engineer - SF Tensor
- Location: San Francisco | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/sf-tensor/766757cb-1dd3-4b98-933b-448d0602d083
- Excerpt: Founding GPU Compiler Engineer San Francisco | OnSite ABOUT SF TENSOR At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. ABOUT THE ROLE We're hiring a Founding GPU Compiler Engineer to build the core compilation infrastructure for our AI compiler. That means taking models from PyTorch, JAX, and TensorFlow and turning them into highly optimized binaries for large-scale AI pre-training. You'll own the entire compiler stack, from ingesting StableHLO all the way to backend code generation, and you'll work across targets like NVIDIA, AMD, Trainium, and TPU. You'll help shape our architecture, tooling, and overall engineering culture from the

### Founding GPU Kernel Engineer - SF Tensor
- Location: San Francisco | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/sf-tensor/1326433f-b3f8-4f05-bd3c-746033c66f1f
- Excerpt: Founding GPU Kernel Engineer San Francisco | OnSite ABOUT SF TENSOR At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. ABOUT THE ROLE We're looking for a Founding GPU Kernel Engineer who lives right at the boundary between hardware and software. Someone who thinks in warps, occupancy, and memory hierarchies, and can squeeze every last FLOP out of a GPU. Your job is to go deeper than anyone else. You'll hand-tune kernels to figure out what's actually possible on the hardware, and then turn that knowledge into compiler optimization passes that help every model we compile. WHAT YOU'LL DO

### Founding Research Engineer, AI-Driven Compilation - SF Tensor
- Location: San Francisco | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/sf-tensor/8aab8d9d-de8e-4d36-a2c3-7c9e18903965
- Excerpt: Founding Research Engineer, AI-Driven Compilation San Francisco | OnSite ABOUT SF TENSOR At The San Francisco Tensor Company, we believe the future of AI and high-performance computing depends on rethinking the entire software and infrastructure stack. Today's developers face bottlenecks across hardware, cloud, and code optimization that slow progress before ideas can reach their full potential. Our mission is to remove those barriers and make compute faster, cheaper, and universally portable. We are building a Kernel Optimizer that automatically transforms code into its most efficient form, combined with Tensor Cloud for adaptive, cross-cloud compute and Emma Lang, a new programming language for high-performance, hardware-aware computation. Together, these technologies reinvent the foundations of AI and HPC. SF Tensor is proudly backed by Susa Ventures and Y Combinator, as well as a group of angels including Max Mullen and Paul Graham as well as founders and executives of NeuraLink, Notion and AMD. We are partnering with researchers, engineers, and organizations who share our belief that the next breakthroughs in AI require breakthroughs in compute. ABOUT THE ROLE We're building a next-generation AI compiler that uses machine learning to optimize machine learning. As a Founding Research Engineer focused on AI-driven compilation, you'll develop the agentic and reinforcement learning systems that guide our compiler's optimization decisions. This is a research-heavy role right at the intersection of compilers and ML. You'll design learned systems that can explore huge optimization spaces, discover new code transformations, and keep improving compilation quality over time. WHAT YOU'LL DO -

### Functional Analyst, Salesforce Marketing Cloud (SFMC) - Sysco
- Location: Sysco Corporate (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://sysco.wd5.myworkdayjobs.com/syscocareers/job/Sysco-Corporate/Functional-Analyst--SFMC_R238677
- Excerpt: Functional Analyst, Salesforce Marketing Cloud (SFMC) Sysco Corporate posted: Posted 30+ Days Ago

### Filler Operator, SF-30 (5pm-5:30am) - Saputo Inc.
- Location: Sulphur Springs, TX (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Apply: https://saputo.wd5.myworkdayjobs.com/Saputo_External_Careers/job/Sulphur-Springs-TX/Filler-Operator--SF-30--5pm-5-30am-_JR64989
- Excerpt: Filler Operator, SF-30 (5pm-5:30am) Sulphur Springs, TX posted: Posted Today

### Tensor SOC Performance Design Verification Engineer - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYimJe0yWahAsUhEm1inLXqAEFfUq5w2jNInfDOdzV1MEjsACxwdTHo_glOJ9K36CEG8Hg_zzRA0wlA6jG6aHAkuZkDjBxu1eG3ZmqvTsRbYuopjhou5g3vpHTsCiw%3D%3D_V2&loc=IN&title=Tensor+SOC+Performance+Design+Verification+Engineer
- Excerpt: Tensor SOC Performance Design Verification Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Develop simulators and architectural models of Google's Tensor SOC. Collaborate with system architects, SoC and CPU/GPU/TPU architects/designers, and software and application experts to understand current and future requirements. Participate in architectural and design evaluation of Tensor SOC features studies. Perform pre-silicon performance simulation and correlate with pre and post-silicon measurements. Communicate analysis results qualitatively and quantitatively. Minimum qualifications: Master's degree in Electrical Engineering, Physics, Computer Engineering, Materials Science or related field or equivalent practical experience. 4 years of experience in the SOC design/verification. Experience verifying digital logic at the Register Transfer Level (RTL) using SystemVerilog at Subsystem or Full chip level. Experience in mobile SOC performance model development, performance analysis, and workload characterization. Preferred qualifications: Experience in CPU microarchitecture innovation. Knowledge of system software components, such as Linux, drivers, and runtime. Knowledge of performance analysis tools. Knowledge

### Quantum Architecture Scientist - Tensor Networks Specialist (Intermediate to Senior) - Xanadu
- Location: Location not specified (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://xanadu.jazz.co/apply/1OZKRnF0dV/Quantum-Architecture-Scientist-Tensor-Networks-Specialist-Intermediate-To-Senior
- Excerpt: Quantum Architecture Scientist - Tensor Networks Specialist (Intermediate to Senior) Quantum Architecture Scientist - Tensor Networks Specialist (Intermediate to Senior)

### Associate SF - Apollo Global Management, Inc.
- Location: Mumbai (NESCO), India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://athene.wd5.myworkdayjobs.com/Apollo_Careers/job/Mumbai-NESCO-India/Associate-SF_R252972-1
- Excerpt: Associate SF Mumbai (NESCO), India posted:

### Staff Personalization Specialist - SF and Adobe Target - Infineon Technologies
- Location: Bangalore (India) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808969260056
- Excerpt: Staff Personalization Specialist - SF and Adobe Target Bangalore (India)

### Co-Op: Financial Data Engineer - Clorox
- Location: Remote - California, SF Bay Area (remote)
- Salary: Not disclosed
- Posted: 2026-05-14
- Apply: https://clorox.wd1.myworkdayjobs.com/clorox/job/Remote---California-SF-Bay-Area/Co-Op--Financial-Data-Engineer_22166
- Excerpt: Co-Op: Financial Data Engineer Remote - California, SF Bay Area posted: Posted 29 Days Ago

### Lead Product Designer - Matterport - SF Bay Area - CoStar Group
- Location: US-CA San Francisco (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Apply: https://costar.wd1.myworkdayjobs.com/costarcareers/job/US-CA-San-Francisco/Lead-Product-Designer_R36046
- Excerpt: Lead Product Designer - Matterport - SF Bay Area US-CA San Francisco posted: Posted 30+ Days Ago

### Group Product Manager, GPU/Graphics, Tensor SoC - Google
- Location: Mountain View, CA, USA; +1 more (unspecified)
- Salary: $240K-$334K
- Posted: 2026-06-04
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTsOhGQcy5BUb8Ks6CMmjnHIJxlTdpWmR0gE0lucMbhjEjsACxwdTMj8Gtpt5eYw2ads85DjE_kyDap_zR6z6txWKXt2mRh3TsgUC5lrt4f0eKRvGxHw7wMmzN_MAw%3D%3D_V2&loc=US&title=Group+Product+Manager
- Excerpt: Group Product Manager, GPU/Graphics, Tensor SoC Mountain View, CA, USA; +1 more At Google, we put our users first. The world is always changing, so we need Product Managers who are continuously adapting and excited to work on products that affect millions of people every day. In this role, you will work cross-functionally to guide products from conception to launch by connecting the technical and business worlds. You can break down complex problems into steps that drive product development. One of the many reasons Google consistently brings innovative, world-changing products to market is because of the collaborative work we do in Product Management. Our team works closely with creative engineers, designers, marketers, etc. to help design and develop technologies that improve access to the world's information. We're responsible for guiding products throughout the execution cycle, focusing specifically on analyzing, positioning, packaging, promoting, and tailoring our solutions to our users. In this role, you will own and define the long-term graphics processing unit (GPU) product roadmap for Google's tensor system-on-chips (SoCs). You will be ensuring Pixel devices deliver graphics performance, gaming experiences, and GPU compute capabilities, while balancing power, performance, and area (PPA) within the mobile SoC constraints. You will drive strategy from concept to silicon, working closely with engineering, software, Pixel, and external partners. Google's mission is to organize the world's information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users.

### General Submissions, for any job not currently listed - Swayable
- Location: NYC, SF, Remote (remote)
- Salary: Not disclosed
- Posted: 2024-02-20
- Apply: https://job-boards.greenhouse.io/swayable/jobs/4261222007
- Excerpt: General Submissions, for any job not currently listed NYC, SF, Remote Please send us your resume if there are other roles not listed here that you believe you could be a good fit for.

### Senior AI-Native Systems Software Engineer, TensorRT - NVIDIA Corporation
- Location: US, CA, Santa Clara (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-AI-Native-Systems-Software-Engineer--TensorRT_JR2016396
- Excerpt: Senior AI-Native Systems Software Engineer, TensorRT US, CA, Santa Clara posted: Posted 30+ Days Ago

### Senior Software Engineer, Deep Learning Inference - TensorRT - NVIDIA Corporation
- Location: US, CA, Santa Clara (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Software-Engineer--Deep-Learning-Inference---TensorRT_JR2013020
- Excerpt: Senior Software Engineer, Deep Learning Inference - TensorRT US, CA, Santa Clara posted: Posted 3 Days Ago

### Analyst - TRI Pointe Homes
- Location: Based in SF Bay Area, but open to other U.S. locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- Apply: https://jobs.lever.co/tri/6929e3c9-3904-4777-9d19-9929a5ddeca6
- Excerpt: Analyst Based in SF Bay Area, but open to other U.S. locations

### Welder III - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-11
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Welder-III_R165367
- Excerpt: Welder III IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted Yesterday

### Project Management Specialist - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Project-Management-Specialist_R164588-1
- Excerpt: Project Management Specialist IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 3 Days Ago

### Architecte et Intégrateur Plate-forme Digitale et Cybersécurité GeoDataCentre (F/H) - Thales
- Location: Toulouse, Haute-Garonne, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-04
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Toulouse/Architecte-et-Intgrateur-Plate-forme-Digitale-et-Cyberscurit-GeoDataCentre--F-H-_R0290817-2/apply
- Excerpt: Architecte et Intégrateur Plate-forme Digitale et Cybersécurité GeoDataCentre (F/H) Toulouse, Haute-Garonne, France Rejoignez notre équipe dynamique en tant qu'Architecte et Intégrateur Plate-forme Digitale et Cybersécurité. Vous serez au cœur de la transformation numérique, en définissant des architectures innovantes et en intégrant des solutions DevSecOps. Si vous êtes passionné par les technologies cloud et la cybersécurité, ce poste est fait pour vous !

### Master Thesis: AI-based Analog/Mixed Signal Design (f/m/div) - Infineon Technologies
- Location: Padua (Padova) (Italy) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808970762499
- Excerpt: Master Thesis: AI-based Analog/Mixed Signal Design (f/m/div) Padua (Padova) (Italy)

### Kernel Engineer — Scientific Computing (SPU) - Vorticity
- Location: Redwood City | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/vorticity/14097a55-df8b-41a5-b5b2-80cad7257550
- Excerpt: Kernel Engineer — Scientific Computing (SPU) Redwood City | OnSite Vorticity is building the world's first Scientific Processing Unit (SPU https://pyrite9.com), a new class of silicon purpose-built to accelerate scientific computing beyond the limits of GPUs. We are designing tightly coupled software-hardware systems around applied mathematics workloads to deliver order-of-magnitude performance gains. Unlocking its full potential requires early, deep engagement from applied mathematics-driven software engineers who can translate real-world scientific workloads into executable models, kernels, libraries, and applications that inform both architecture and tooling decisions. As a Kernel Engineer, you will work at the intersection of applied mathematics, scientific computing, parallel programming, and low-level performance engineering. You will help shape how numerical kernels are implemented, optimized, and eventually mapped onto the SPU. Your work may include building early numerical kernels and libraries, developing prototype applications, and writing Python-based workload models and simulators, all to support and inform the evolving hardware and compiler stack. This requires both strong applied math fundamentals and deep low-level implementation ability. You should be comfortable moving from mathematical formulations to efficient kernels, reasoning about accuracy, stability, data movement, memory hierarchy, parallel execution, and compiler behavior along the way. This position is ideal for someone who combines strong scientific computing instincts with the low-level habits of a performance engineer. RESPONSIBILITIES - Prototyping and implementing core kernels and low-level numerical primitives for the SPU. - Translating mathematical formulations into executable, performance-relevant kernel implementations. - Analyzing and optimizing me

### Principal Engineer System Compute (f/m/div) - Infineon Technologies
- Location: Langen (Frankfurt am Main) (Germany) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808970374969
- Excerpt: Principal Engineer System Compute (f/m/div) Langen (Frankfurt am Main) (Germany)

### Applied Math Libraries Engineer (SPU) - Vorticity
- Location: Redwood City | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/vorticity/76e866dd-5c39-4fc5-85bb-51c517815804
- Excerpt: Applied Math Libraries Engineer (SPU) Redwood City | OnSite Vorticity is building the world's first Scientific Processing Unit (SPU https://pyrite9.com), a new class of silicon purpose-built to accelerate scientific computing beyond the limits of GPUs. We are designing tightly coupled software-hardware systems around applied mathematics workloads to deliver order-of-magnitude performance gains. Unlocking its full potential requires early, deep engagement from applied mathematics-driven software engineers who can translate real-world scientific workloads into executable models, kernels, libraries, and applications that inform both architecture and tooling decisions. As a Applied Math Libraries Engineer, you will work at the intersection of applied mathematics, scientific computing, and low-level software. From day one, you will help build the numerical software foundation of the SPU. This role is focused on building reusable mathematical primitives rather than full end-to-end scientific applications. The ideal candidate is excited to implement mathematics on a new architecture. You will work closely with hardware architects, compiler engineers, and runtime engineers to shape how numerical algorithms are expressed, executed, and optimized on the SPU. This position is ideal for someone who enjoys moving fluidly between applied math, numerical algorithms, and low-level software, and who wants to help build a new scientific computing platform from the ground up. RESPONSIBILITIES - Prototype and implement core numerical linear algebra kernels and libraries for the SPU. - Translate mathematical algorithms into executable, performance-relevant software. - Write C, C++, and Python reference implementations to guide hardware, compiler, and runtime decisions. - Design benchmarks, correctness tests, numerical accuracy tests, and

### Coach/Compagnon Polarion (F/H) - Thales
- Location: Bordeaux, Gironde, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-20
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Bordeaux/Coach-Compagnon-Polarion--F-H-_R0316326-2/apply
- Excerpt: Coach/Compagnon Polarion (F/H) Bordeaux, Gironde, France Rejoignez notre équipe en tant que Coach Polarion et contribuez à l'harmonisation des pratiques d'ingénierie au sein de Thales. Si vous avez une solide expérience en ingénierie de projets logiciels complexes et maîtrisez Polarion, ce poste est fait pour vous !

### Software Engineer, Staff - SIMD Kernels - d-Matrix
- Location: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-15
- Apply: https://jobs.ashbyhq.com/d-matrix/0dd92e0e-ac07-44d5-b8cf-ca1a9d18d7b5
- Excerpt: Software Engineer, Staff - SIMD Kernels Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Santa Clara, CA headquarter or any of our regional offices. Remote possible. The Role: Software Engineer, Staff - SIMD Kernels What you will do: As a member of the SIMD Kernels team, you will help productize the software stack for our AI compute engine. You will develop, enhance, and maintain software kernels for ML operators-such as softmax, layer norm, and activation functions-for next‑generation AI hardware. You will also build solutions that make our SDK intuitive for developers to use and analyze performance. You have experience building software kernels for modern hardware architectures and understand how to map algorithms and AI‑framework computational graphs onto those architectures. You're comfortable working across the full toolchain and navigating hardware-software co‑design trade‑offs. You can deliver and scale high‑quality software quickly in a fast‑moving development environment. What you will bring: Minimum: - MS or PhD in

### Senior Architect, Simulation Kernel Modelling - NVIDIA Corporation
- Location: US, CA, Santa Clara (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Architect--Simulation-Kernel-Modelling_JR2017737
- Excerpt: Senior Architect, Simulation Kernel Modelling US, CA, Santa Clara posted: Posted 30+ Days Ago

### SECURITY SPECIALIST (TRAINING SPECIALIST) - Department of the Air Force
- Location: Rickenbacker AFB, Ohio (unspecified)
- Salary: $64K-$84K
- Posted: 2026-06-05
- Hires in: OH
- Apply: https://www.usajobs.gov:443/job/871893900
- Excerpt: SECURITY SPECIALIST (TRAINING SPECIALIST) Rickenbacker AFB, Ohio Summary This National Guard position is for a SECURITY SPECIALIST (TRAINING SPECIALIST), Position Description Number D2161000 and is part of the OH 121 Air Refueling Wing, Ohio Air National Guard. The primary purpose of this position is to serve as the subject matter expert in managing the SF Squadron program to include Air Expeditionary Force (AEF) deployments, formal training programs, and readiness and emergency management. Duties As a SECURITY SPECIALIST (TRAINING SPECIALIST), GS-0080-9, you will perform the following duties: 1. Reviews all operations, mobility, contingency, and exercise plans to ensure combat readiness for the SF Squadron. Analyzes exercise and contingency plans to determine required SF actions in support of mission requirements. Evaluates all equipment, manning and training requirements to meet wartime, contingency, deployment, and pre-planned tasking. Coordinates with other base organizations on applicable plans. Manages the development of plans for deployment, disaster preparedness, base recovery, contingency response, and other related plans. Prepares, updates, and reviews the SF portion of the base deployment, disaster preparedness, base recovery, contingency response, and related plans. Coordinates plans and annexes with SF supervisors. Initiates changes, modifications, additions and deletions to personnel and equipment tasking and assignments through the SF Commander for approval. Identifies deficiencies develops, and implements plans for increasing mission readiness. Ensures the SF unit meets requirements for wartime capability and AEF requirements. 2. Responsible for proper security, classification, and storage of classified documents. Compiles information by identifying shortfalls and recommending corrective actions to Defense Readiness Reporting

### Senior Engineer II, GPU Kernel and Performance - DigitalOcean
- Location: San Francisco (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-17
- 401(k) match: listed (not source-backed)
- Apply: https://www.digitalocean.com/careers/position/apply/?gh_jid=7714480
- Excerpt: Senior Engineer II, GPU Kernel and Performance San Francisco Senior Engineer II, GPU Kernel and Performance

### Compiler Engineer - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $147K-$211K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYCSg9VOxPwFhXku6-bbL-lpRxM4REMsWMN2lhopXIzTEjsACxwdTKMub7OMF0zhVWNJuq7ChzvW48wRFiYA9SvuQ7dGwtrMHmSWagQtqmGOG9iY31b1fVi3LmmRuA%3D%3D_V2&loc=US&title=Compiler+Engineer
- Excerpt: Compiler Engineer Sunnyvale, CA, USA Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. The Tensor Processing Unit Supply Chain and New Product Introduction team operates at the intersection of machine learning, compilers, and Tensor Processing Unit hardware. In this role, you will collaborate with teams across hardware and software, and enable Google to have the industry's most performant machine learning chip (Tensor Processing Unit) at the hands of machine learning modeling teams. The majority of machine learning at Google (and for Cloud customers) flows through tools that the Tensor Processing Unit backend and New Product Introduction team is creating, so impact is both immediate and massive. Individual pay is determined by factors including job-related skills, experience, and relevant education or

### AI Computing Development Engineer, TensorRT and TensorRT-LLM - NVIDIA Corporation
- Location: China, Shanghai (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/China-Shanghai/AI-Computing-Development-Engineer--TensorRT-and-TensorRT-LLM_JR2018666
- Excerpt: AI Computing Development Engineer, TensorRT and TensorRT-LLM China, Shanghai posted: Posted 15 Days Ago

### Branch Manager SAFE Act ( DeNovo) Daly City SF Ca, Vice President - Citigroup Inc.
- Location: SAN FRANCISCO, California, United States of America | 20miles (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://citi.eightfold.ai/careers/job/859035534050
- Excerpt: Branch Manager SAFE Act ( DeNovo) Daly City SF Ca, Vice President SAN FRANCISCO, California, United States of America | 20miles

### Thèse : Reconstruction de volumes 3D pour la chirurgie assistée par AI (H/F) - Thales
- Location: Moirans, Isere, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Moirans/Thse---Reconstruction-de-volumes-3D-pour-la-chirurgie-assiste-par-AI--H-F-_R0327010/apply
- Excerpt: Thèse : Reconstruction de volumes 3D pour la chirurgie assistée par AI (H/F) Moirans, Isere, France Les limites de ces algorithmes, telles que les hallucinations et le temps de reconstruction, seront étudiées et adaptées aux besoins de la chirurgie en bloc opératoire. - Tests de performance en simul...

### Computational and/or Experimental Hybrid Scientist – Foster City, CA (SF Bay Area) - Illumina, Inc.
- Location: US - Bay Area - Foster City (hybrid)
- Salary: Not disclosed
- Posted: 2026-06-01
- 401(k) match: listed (not source-backed)
- Apply: https://illumina.wd1.myworkdayjobs.com/illumina-careers/job/US---Bay-Area---Foster-City/Senior-Scientist--Immunology---Foster-City--CA--San-Francisco-Bay-Area-_42704-JOB
- Excerpt: Computational and/or Experimental Hybrid Scientist – Foster City, CA (SF Bay Area) US - Bay Area - Foster City posted: Posted 11 Days Ago

### SRE Data (H/F) - Thales
- Location: Paris 9e Arrondissement, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-02-20
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/PARIS-9me/SRE-Data--H-F-_R0314759-1/apply
- Excerpt: SRE Data (H/F) Paris 9e Arrondissement, France Rejoignez notre équipe en tant qu'Ingénieur SRE Data et participez à la construction d'une plateforme Cloud de Confiance. Vous aurez l'opportunité de travailler avec des technologies avancées telles que GCP, Kubernetes et Elasticsearch. Si vous êtes passionné par l'automatisation et l'architecture cloud, ce poste est fait pour vous !

### Shop/Plan Operator-Entry - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Shop-Plan-Operator-Entry_R162611
- Excerpt: Shop/Plan Operator-Entry IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 7 Days Ago

### Principal Software Engineer - Kernels - d-Matrix
- Location: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-02
- Apply: https://jobs.ashbyhq.com/d-matrix/a8c4d6e0-bc72-4ffc-ab5c-4d8b3769f085
- Excerpt: Principal Software Engineer - Kernels Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA, headquarters 3-5 days per week. The Role: Principal Software Engineer - Kernels What you will do: The role requires you to be part of the team that helps productize the SW stack for our AI compute engine. As part of the software team, you will be responsible for the development, enhancement, and maintenance of software kernels for next-generation AI hardware. You possess experience building software kernels for HW architectures. You possess a very strong understanding of various hardware architectures and how to map algorithms to the architecture. You understand how to map computational graphs generated by AI frameworks to the underlying architecture. You have had past experience working across all aspects of the full-stack toolchain and understand the nuances of what it takes to optimize and trade off various aspects of hardware-software co-design.

### India Regional Senior Sourcing Leader - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/India-Regional-Senior-Sourcing-Leader_R165117
- Excerpt: India Regional Senior Sourcing Leader IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted Today

### Postdoctoral Scholar — AI Researcher for Critical Mineral Discovery - KoBold Metals
- Location: Remote (remote)
- Salary: $80K-$90K
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/koboldmetals/jobs/4702493005
- Excerpt: Postdoctoral Scholar — AI Researcher for Critical Mineral Discovery Remote Position: Fully funded 3-year postdoctoral fellowship at Stanford Mineral-X, advised by Prof. Jef Caers, in collaboration with KoBold Metals, developing and deploying new methods for critical mineral exploration and resource definition. The scholar will develop and apply AI, muon tomography, seismic imaging, and geophysical inversion methods to discover and characterize copper, nickel, lithium, cobalt, and rare earth deposits using real exploration data from active field programs. More information here: https://postdocs.stanford.edu/postdoc-admins/policy/funding-rates-and-guidelines. Research Scope - Multi-physics inversion: Develop stochastic and ensemble inversion frameworks that jointly assimilate muon flux, seismic (active-source, passive, DAS), magnetics, gravity, and EM data into 3D subsurface property models with calibrated uncertainty. - Muon tomography: Forward modeling, sensor placement optimization, and inversion of cosmic-ray muon attenuation data from borehole and surface detectors to constrain ore body density at depth. - Machine learning for geoscience: Apply deep generative models, geostatistical priors, and physics-informed neural networks to regional-to-deposit-scale targeting and resource estimation. Build pipelines that respect geological process constraints rather than purely data-driven correlations. - Decision under uncertainty: Extend Mineral-X's intelligent agent framework to sequential data acquisition decisions (drill hole placement, geophysical survey design) that maximize information value per dollar. Required Qualifications - PhD (fully completed, and within 4 years of graduation) in physics, applied physics, geophysics, computational earth sciences, machine learning, applied mathematics, or related field. - Strong Python proficiency (NumPy, PyTorch or JAX, scientific stack); experience with HPC, GPU computing, and reproducible research workflows. - Track record of publishing

### Shop/Plan Operator-Entry - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Shop-Plan-Operator-Entry_R164714
- Excerpt: Shop/Plan Operator-Entry IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 8 Days Ago

### Doctorant sur le Watermarking pour une sécurité et une robustesse accrues des modèles d’IA dans l’apprentissage fédéré (H/F) - Thales
- Location: Palaiseau, Essonne, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-03
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Palaiseau/Doctorant-sur-le-Watermarking-pour-une-scurit-et-une-robustesse-accrues-des-modles-d-IA-dans-l-apprentissage-fdr--H-F-_R0312735-1/apply
- Excerpt: Doctorant sur le Watermarking pour une sécurité et une robustesse accrues des modèles d’IA dans l’apprentissage fédéré (H/F) Palaiseau, Essonne, France Rejoignez notre équipe en tant que Doctorant sur le Watermarking pour renforcer la sécurité des modèles d'IA. Si vous êtes passionné par l'apprentissage machine et la cybersécurité, ce poste est fait pour vous !

### Manufacturing Professional - Warehouse & Internal Logistics - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Manufacturing-Professional---Warehouse---Internal-Logistics--Manufacturing-Professional---Warehouse---Internal-logistics_R163192
- Excerpt: Manufacturing Professional - Warehouse & Internal Logistics IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 24 Days Ago

### Software Engineer - GPU Kernels - Baseten
- Location: San Francisco, California, United States, New York (unspecified)
- Salary: Not disclosed
- Posted: 2025-07-17
- Fertility benefits: yes (not source-backed)
- Apply: https://jobs.ashbyhq.com/baseten/ddb5bc98-6116-49a2-802e-1c05398663f1
- Excerpt: Software Engineer - GPU Kernels San Francisco, California, United States, New York ABOUT BASETEN Baseten powers mission-critical inference for the world's most dynamic AI companies, like Cursor, Notion, OpenEvidence, Abridge, Clay, Gamma and Writer. By uniting applied AI research, flexible infrastructure, and seamless developer tooling, we enable companies operating at the frontier of AI to bring cutting-edge models into production. We're growing quickly and recently raised our $300M Series E , backed by investors including BOND, IVP, Spark Capital, Greylock, and Conviction. Join us and help build the platform engineers turn to to ship AI products. THE ROLE We're seeking a GPU Kernel Engineer to join our team at the cutting edge of AI acceleration, where your code directly impacts the performance of state-of-the-art machine learning models. As a GPU Kernel Engineer, you'll craft the foundation that powers modern AI workloads, optimizing every microsecond of computation to enable breakthrough applications. You'll work in a fast-paced, intellectually stimulating environment where technical excellence is paramount and your contributions directly influence production systems serving millions of users across numerous products. This role offers exceptional growth potential for engineers passionate about low-level optimization and high-impact systems work. EXAMPLE INITIATIVES You'll get to work on these types of projects as part of our Model Performance team: - Baseten Embeddings Inference: The fastest embeddings solution available - The Baseten Inference Stack - Driving model performance optimization RESPONSIBILITIES Core Engineering Responsibilities - Design and implement high-performance GPU kernels for key ML operations, including matrix multiplications, attention mechanisms,

### Thesis Quantum Computing and Generative Models (f/m/x) - BMW
- Location: Location not specified (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Apply: https://www.bmwgroup.jobs/job-invite/172466/?locale=en_US
- Excerpt: Thesis Quantum Computing and Generative Models (f/m/x) Location not specified SOME IT WORKS. SOME CHANGES WHAT'S POSSIBLE. SHARE YOUR PASSION. More than 90% of automotive innovations are based on electronics and software. That's why creative freedom and lateral thinking are so important in the pursuit of truly novel solutions. That's why our experts will treat you as part of the team from day one, encourage you to bring your own ideas to the table - and give you the opportunity to really show what you can do. Our team at the BMW Group explores innovative solutions in quantum computing and generative models to advance research in quantum chemistry. We offer you the opportunity to support pioneering projects in a collaborative environment. What awaits you? You will support the team in applying generative models to quantum chemistry challenges. Furthermore, you help to develop and implement quantum algorithms for research purposes. In addition, you participate in research and development activities to explore new applications of quantum computing. Please note that your thesis must be supervised by a university on your part. What should you bring along? Studies in computer science, engineering, physics or a related field. Strong programming skills, preferably in Python. Experience or coursework in machine learning. Interest in quantum computing and quantum chemistry. Ability to collaborate in a dynamic team environment. Good English skills. Would you like to support our team in advancing quantum computing and generative models? Then apply now! What do we o

### Couldn't find the right opportunity? - Bunkerhill Health
- Location: SF Office (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/bunkerhillhealth/95dc07bf-3817-4846-8b07-02159b026a01
- Excerpt: Couldn't find the right opportunity? SF Office ABOUT THE ROLE If you're interested in joining the Bunkerhill Health team but don't see an opportunity that fits what you're looking for right now, please apply her. We're always looking for talented and motivated people to join our team. We'll reach out if we find a potential match!

### Quality Control Inspector -Entry Level - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Quality-Operator-Entry_R164715
- Excerpt: Quality Control Inspector -Entry Level IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 4 Days Ago

### RE / RS - Foundations, Search - OpenAI
- Location: San Francisco, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2025-06-16
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.ashbyhq.com/openai/020b2aae-8be0-408c-ab49-20eefa8541af
- Excerpt: RE / RS - Foundations, Search San Francisco, California, United States About the Team The Foundations Research team works on high-risk, high-reward ideas that could shape the next decade of AI. Our goal is to advance the science and data that enable our training and scaling efforts, with a particular focus on future frontier models. Pushing the boundaries of data, scaling laws, optimization techniques, model architectures, and efficiency improvements to propel our science. The Search team sits within Foundations, building agentic search by co-designing model-system interfaces with the core search stack (serving, indexing, retrieval) to translate model intent into reliable, real-world actions. Operating at the frontier of AI and information retrieval, the team develops large-scale systems that transform and index vast corpora, enabling models to reason over global knowledge and act dependably. In close partnership with researchers, we rapidly bring modeling breakthroughs into production and redefine how intelligent systems discover, retrieve, and synthesize information at planetary scale. About the Role We're looking for a researcher focused on our embedding retrieval efforts. You'll work with a a team of world-class research scientists and engineers developing foundational technology that enables models to retrieve and condition on the right information, at the right time. This includes designing new embedding training objectives, scalable vector store architectures, and dynamic indexing methods. This work will support retrieval across many OpenAI products and internal research efforts, with opportunities for scientific publication and deep technical impact. This role is based in San Francisco, CA. We use a hybrid

### Safety valve product design and Engineering Lead - Baker Hughes
- Location: IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-27
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/IN-Tamil-Nadu-Coimbatore-SF-No-608-Chettipalayam-Road-Eachanari-Post-Consolidation/Lead-Engineer---Safety-valve-product-design-and-Engineering_R157049-1
- Excerpt: Safety valve product design and Engineering Lead IN-Tamil Nadu-Coimbatore-SF No 608 Chettipalayam Road, Eachanari Post (Consolidation) posted: Posted 16 Days Ago

### Intégrateur Plate-forme Digitale et Cybersécurité Segment Sol (F/H) - Thales
- Location: Toulouse, Haute-Garonne, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-05
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Toulouse/Intgrateur-Plate-forme-Digitale-et-Cyberscurit-Segment-Sol--F-H-_R0316866-1/apply
- Excerpt: Intégrateur Plate-forme Digitale et Cybersécurité Segment Sol (F/H) Toulouse, Haute-Garonne, France Rejoignez notre équipe dynamique en tant qu'Intégrateur Plate-forme Digitale et Cybersécurité Segment Sol. Vous contribuerez à la transformation numérique de l'entreprise en intégrant des solutions sécurisées et en développant des architectures cloud. Si vous êtes passionné par la technologie et l'innovation, ce poste est fait pour vous !

### Business Processes Associate Consultant - SF - SAP
- Location: Country China | Internal Posting Location Shanghai (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.sap.com/job/Shanghai-Business-Processes-Associate-Consultant-SF-201203/1385828133/
- Excerpt: Business Processes Associate Consultant - SF Country China | Internal Posting Location Shanghai We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. Responsibilities: 1. Project Implementation & Support: • Assist in the delivery of SF module implementations (e.g., Employee Central, GMPM) by participating in requirement analysis, system configuration, testing, and go-live support. • Provide day-to-day system maintenance, user training, and issue resolution to ensure smooth operations. 2. Business Process Optimization: • Collaborate with business stakeholders to identify process bottlenecks and design SF-based solutions to enhance efficiency and compliance. 3. Client Collaboration & Communication: • Act as a liaison between technical teams and clients, translating business needs into technical requirements and vice versa. • Maintain clear and proactive communication with clients to manage expectations and ensure project alignment. 4. Knowledge Development & Team Collaboration: • Stay updated with SF best practices and industry trends through continuous learning and knowledge sharing. • Support senior consultants and cross-functiona

### Principal Architect, Performance Analysis and Modeling - d-Matrix
- Location: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-11
- Apply: https://jobs.ashbyhq.com/d-matrix/d0564841-0785-4687-9d44-525869b6753d
- Excerpt: Principal Architect, Performance Analysis and Modeling Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Working onsite at our Santa Clara, CA headquarters 3 days per week Hybrid. The role: Principal Architect- Performance Analysis and Modeling d-Matrix is seeking outstanding computer architects to help accelerate AI application performance at the intersection of both hardware and software, with particular focus on emerging hardware technologies (such as DIMC, D2D, 3D-DRAM etc.) and emerging workloads (such as generative inference etc.). Our acceleration philosophy cuts through the system ranging from efficient tensor cores, storage, and data movements along with co-design of dataflow, and collective communication techniques. What you will do: - As a member of the architecture team, you will analyze the latest ML workloads (multi-modal LLMs, CoT reasoning models, video/audio-generation) - You will contribute Hardware and Software features that power the next generation of inference accelerators in datacenters. - This role requires to keep up the latest research in

### Sr Manager, Field Service Operations - Otis Worldwide
- Location: OT348: SF - SAN FRANCISCO, CA 444 SPEAR STREET, STE 102, SAN FRANCISCO, CA, 94105 USA (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- 401(k) match: listed (not source-backed)
- Apply: https://otis.wd5.myworkdayjobs.com/REC_Ext_Gateway/job/OT348-SF---SAN-FRANCISCO-CA-444-SPEAR-STREET-STE-102-SAN-FRANCISCO-CA-94105-USA/Sr-Manager--Field-Service-Operations_20145913
- Excerpt: Sr Manager, Field Service Operations OT348: SF - SAN FRANCISCO, CA 444 SPEAR STREET, STE 102, SAN FRANCISCO, CA, 94105 USA posted: Posted 4 Days Ago

### Architecte Cybersécurité Spatial F/H - Thales
- Location: Gennevilliers, Hauts-de-Seine, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-24
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Gennevilliers/Architecte-Cyberscurit-Spatial-F-H_R0316597-1/apply
- Excerpt: Architecte Cybersécurité Spatial F/H Gennevilliers, Hauts-de-Seine, France Rejoignez notre équipe en tant qu'Architecte Cybersécurité Spatial et contribuez à la sécurité des systèmes spatiaux. Vous serez responsable de la définition des architectures de sécurité et de la collaboration avec des équipes multidisciplinaires. Si vous avez une passion pour la cybersécurité et l'innovation, ce poste est fait pour vous !

### Senior Deep Learning Software Engineer, TensorRT Performance - NVIDIA Corporation
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Deep-Learning-Software-Engineer--TensorRT-Performance_JR2014992
- Excerpt: Senior Deep Learning Software Engineer, TensorRT Performance 2 Locations posted: Posted 30+ Days Ago

### Space Force Race Director - Department of the Air Force
- Location: Wright-Patterson AFB, Ohio (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-06
- Learning budget: yes (not source-backed)
- Hires in: OH
- Apply: https://www.usajobs.gov:443/job/864070100
- Excerpt: Space Force Race Director Wright-Patterson AFB, Ohio Summary About the position: This position is Non-appropriated Fund (NAF) and will be assigned to the Space Force Operation. Serves as the primary point of authority and owner for the planning, execution, and success of the Space Force (SF) T-10 Miler event, ensuring it meets all strategic, financial, and operational goals. The position includes paid holidays, leave accrual, optional participation in Group Health, Dental and Life Insurance plans, Retirement, 401K and Flexible Benefits plans. Duties Serves as the primary point of authority and owner for the planning, execution, and success of the Space Force (SF) T-10 Miler event, ensuring it meets all strategic, financial, and operational goals. Reports to the Air Force Marathon (AFM) Programs Director on plans, development, and management of the SF T-10 Miler and related events, to include but not limited to top-level operations plans for implementation of all related event execution elements, including Emergency Management, Anti-Terrorism, LLC, Civil Engineering, Department of Transportation, and EMS. Exercises daily task-oriented direction and provides event-specific priorities to personnel from functional teams for all aspects related to the SF T-10 Miler. Develops activities to meet the needs of participants while remaining within established guidelines, parameters, and objectives of funding, facilities, equipment and support staff. Continuously evaluates the effectiveness of on-going SF running activities to ascertain where and how the program can be strengthened and improved. Adheres to monthly, quarterly, and annual budget requirements; monitors variances and makes revisions as necessary. Collaborates with Functional Directors

### Principal Engineer Analog Mixed Signal Design (f/m/div) - Infineon Technologies
- Location: Bucharest (Romania) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808956973733
- Excerpt: Principal Engineer Analog Mixed Signal Design (f/m/div) Bucharest (Romania)

### SAP - SF – Payroll Manager - PricewaterhouseCoopers International Limited
- Location: Bangalore, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- 401(k) match: listed (not source-backed)
- Apply: https://pwc.wd3.myworkdayjobs.com/CRM_Experienced_Careers_Site/job/Bangalore/SAP---SF---Payroll-Manager_732325WD/apply
- Excerpt: SAP - SF – Payroll Manager Bangalore, India Join us as an SAP SuccessFactors Payroll Manager and lead the implementation of SAP HCM solutions for top-tier clients. Drive business process improvement, mentor teams, and deliver strategic HR transformation projects. If you excel in SAP HCM, project management, and client leadership, this is your opportunity to make a real impact.

### SAP- SF Talent - Senior Associate - PricewaterhouseCoopers International Limited
- Location: Telangana, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-25
- 401(k) match: listed (not source-backed)
- Apply: https://pwc.wd3.myworkdayjobs.com/CRM_Experienced_Careers_Site/job/Hyderabad/SAP--SF-Talent---Senior-Associate_731580WD/apply
- Excerpt: SAP- SF Talent - Senior Associate Telangana, India Join our team as a Senior SAP SuccessFactors Talent Acquisition Associate and drive impactful business solutions for global clients. Leverage your expertise in SAP SuccessFactors, cloud implementation, and client collaboration to deliver high-quality consulting projects. Grow your career with hands-on learning, mentorship, and opportunities to shape the future of talent management.

### Ingénieur Algorithmes Simulations Performance - F/H - Thales
- Location: Rungis, Val-de-Marne, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-22
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Rungis/Ingnieur-Algorithmes-Simulations-Performance---F-H_R0320033-1/apply
- Excerpt: Ingénieur Algorithmes Simulations Performance - F/H Rungis, Val-de-Marne, France Rejoignez notre équipe en tant qu'Ingénieur Algorithmes Simulations Performance et contribuez à la conception de solutions innovantes pour des systèmes complexes. Si vous êtes passionné par l'innovation et le développement d'algorithmes, ce poste est fait pour vous !

### Conseiller Client (F/H) - Technique -Fès - Français - Concentrix
- Location: MAR Fès - 112, Avenue des FAR Champs de course, Ville Nouvelle (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://cnx.wd1.myworkdayjobs.com/external_global/job/MAR-Fs---112-Avenue-des-FAR----Champs-de-course-Ville-Nouvelle/Conseiller-Client--F-H----Technique--Fs---Franais_R1674297-1
- Excerpt: Conseiller Client (F/H) - Technique -Fès - Français MAR Fès - 112, Avenue des FAR Champs de course, Ville Nouvelle posted: Posted 30+ Days Ago

### General Manager - SF Hub - Ever Loved
- Location: San Francisco, CA (unspecified)
- Salary: $140K-$165K
- Posted: 2026-06-10
- Apply: https://job-boards.greenhouse.io/ever/jobs/5193135008
- Excerpt: General Manager - SF Hub San Francisco, CA General Manager - SF Hub About Us Ever is building the future of auto retail. As the first AI-native auto retail platform, we are building the next $100B+ automotive business, starting with electric vehicles. Our AI-native product and operations power our full-stack auto retail business, serving EV buyers and sellers across the nation, both online and offline. About the Role The General Manager is the senior operational leader at Ever's San Francisco hub. You will own the full customer-facing deal lifecycl -from first contact through funding and title - and are accountable for the performance, culture, and daily execution of four verticals: Sales, BDC, Finance & Insurance, and Business Office / Title & Registration. This role reports directly to the VP of Operations and requires full-time, on-site presence at the SF hub. Key Responsibilities Sales Leadership Deal Volume & Margin: Own retail deal volume targets for the SF market. Hold the Sales Manager and consultants accountable to closing ratios, front-end margin per unit, and customer experience scores. Sales Process: Drive a consistent process from lead to delivery. Monitor pipeline health, stage-by-stage conversion, and days-to-close across the team. Deal Quality: Review deals in progress and post-close for margin integrity, proper structure, and process adherence. Coach the Sales Manager on unit economics and objection handling. Funnel Gaps: Identify and address breakdowns in the sales funnel before they become pattern issues. BDC & Lead Operations Pipeline Performance: Oversee BDC inbound and outbound pipeline. Hold the

### Nurse Navigator, SF Head and Neck Surgery - Sutter Health
- Location: San Francisco, California, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-18
- 401(k) match: listed (not source-backed)
- Apply: https://wd1.myworkdaysite.com/recruiting/sutterhealth/SH/job/San-Francisco/Nurse-Navigator--SF-Head-and-Neck-Surgery_R-122064-1/apply
- Excerpt: Nurse Navigator, SF Head and Neck Surgery San Francisco, California, United States of America Join our team as a Senior Nurse Navigator, Head and Neck Surgery, and make a real impact on patient care. Coordinate multidisciplinary teams, empower patients and families, and ensure seamless navigation through the healthcare system. If you're a licensed RN with strong communication and care coordination skills, this is your opportunity to shape patient outcomes.

### Algorithm Developer - Image Processing/Machine Learning IV - Applied Materials
- Location: Santa Clara,CA (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://amat.wd1.myworkdayjobs.com/External/job/Santa-ClaraCA/Algorithm-Developer---Image-Processing-Machine-Learning-III_R2616672
- Excerpt: Algorithm Developer - Image Processing/Machine Learning IV Santa Clara,CA posted: Posted 30+ Days Ago

### SF Operator - Newell Brands
- Location: Country United States | Additional Job Posting Location(s) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.newellbrands.com/job/Winchester-SF-Operator-Virg/1396181000/
- Excerpt: SF Operator Country United States | Additional Job Posting Location(s) Position Description Position Title: SF Operator Division/Location/Product: Winchester, VA. Job Code: OPSMFDO101 Reports To: Manufacturing Supervisor Department Name/Number: SF/ 1665204580 Manager Approval: Manufacturing Manager Next Level Approval: Sr. Manager Operations Updated: July 15, 2025 Shift: D Shift (6PM-6AM) As an Inspector-Assembler (Manufacturing Operator) in the Commercial Group, located in Winchester, VA you will report to a manufacturing supervisor. This position will work as part of a team having responsibility for reviewing operator instruction sheets to assemble and/or package an entire product or a component of a product to manufacturing specifications and quality standards. Responsibilities: Assemble and/or package manufactured goods Conduct regular inspections of manufactured goods to ensure product meets quality standards Use computer to report defective pieces, problems with process, product or manufacturing machinery Maintain a safe and accident-free environment by adhering to safety standards and identifying safety issues Keep work area clean Other duties as assigned MINIMUM QUALIFICATIONS/SKILL SET: High School diploma or GED preferred, experience will be considered in lieu of education Must be legally authorized to work in the United States Must be able to lift 40lbs Preferred Qualifications: Must be a team player and able to communicate effectively with co-workers and leadership Forklift experience required

### SHAPE _ Aortic _ DSM _ 石家庄 - Medtronic
- Location: Shijiazhuang, Hebei, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 24 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://medtronic.wd1.myworkdayjobs.com/medtroniccareers/job/Shijiazhuang-Hebei-China/SHAPE---Aortic---DSM---_R66083
- Excerpt: SHAPE _ Aortic _ DSM _ 石家庄 Shijiazhuang, Hebei, China posted: Posted 30+ Days Ago

### SF Operator - Newell Brands
- Location: Country United States | Additional Job Posting Location(s) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.newellbrands.com/job/Winchester-SF-Operator-Virg/1395564900/
- Excerpt: SF Operator Country United States | Additional Job Posting Location(s) Position Description Position Title: SF Operator Division/Location/Product: Winchester, VA. Job Code: OPSMFDO101 Reports To: Manufacturing Supervisor Department Name/Number: SF/ 1665204580 Manager Approval: Manufacturing Manager Next Level Approval: Sr. Manager Operations Updated: July 15, 2025 Shift: C Shift (6PM-6AM) As an Inspector-Assembler (Manufacturing Operator) in the Commercial Group, located in Winchester, VA you will report to a manufacturing supervisor. This position will work as part of a team having responsibility for reviewing operator instruction sheets to assemble and/or package an entire product or a component of a product to manufacturing specifications and quality standards. Responsibilities: Assemble and/or package manufactured goods Conduct regular inspections of manufactured goods to ensure product meets quality standards Use computer to report defective pieces, problems with process, product or manufacturing machinery Maintain a safe and accident-free environment by adhering to safety standards and identifying safety issues Keep work area clean Other duties as assigned MINIMUM QUALIFICATIONS/SKILL SET: High School diploma or GED preferred, experience will be considered in lieu of education Must be legally authorized to work in the United States Must be able to lift 40lbs Preferred Qualifications: Must be a team player and able to communicate effectively with co-workers and leadership Forklift experience required

### Principal Engineer Functional Verification (f/m/div) - Infineon Technologies
- Location: Belgrade (Serbia) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808961478809
- Excerpt: Principal Engineer Functional Verification (f/m/div) Belgrade (Serbia)

### SF Operator - Newell Brands
- Location: Country United States | Additional Job Posting Location(s) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.newellbrands.com/job/Winchester-SF-Operator-Virg/1395628500/
- Excerpt: SF Operator Country United States | Additional Job Posting Location(s) Position Description Position Title: SF Operator Division/Location/Product: Winchester, VA. Job Code: OPSMFDO101 Reports To: Manufacturing Supervisor Department Name/Number: SF/ 1665204580 Manager Approval: Manufacturing Manager Next Level Approval: Sr. Manager Operations Updated: July 15, 2025 Shift: B Shift (6AM-6PM) As an Inspector-Assembler (Manufacturing Operator) in the Commercial Group, located in Winchester, VA you will report to a manufacturing supervisor. This position will work as part of a team having responsibility for reviewing operator instruction sheets to assemble and/or package an entire product or a component of a product to manufacturing specifications and quality standards. Responsibilities: Assemble and/or package manufactured goods Conduct regular inspections of manufactured goods to ensure product meets quality standards Use computer to report defective pieces, problems with process, product or manufacturing machinery Maintain a safe and accident-free environment by adhering to safety standards and identifying safety issues Keep work area clean Other duties as assigned MINIMUM QUALIFICATIONS/SKILL SET: High School diploma or GED preferred, experience will be considered in lieu of education Must be legally authorized to work in the United States Must be able to lift 40lbs Preferred Qualifications: Must be a team player and able to communicate effectively with co-workers and leadership Forklift experience required

### Gestionnaire de Flux (F/H) - Thales
- Location: Brest, Finistere, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-30
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Brest/Gestionnaire-de-Flux--F-H-_R0325996/apply
- Excerpt: Gestionnaire de Flux (F/H) Brest, Finistere, France Nous recherchons un Gestionnaire de Flux pour rejoindre notre équipe à Brest. Vous serez responsable de la gestion logistique, de l'utilisation de SAP et de l'assurance qualité des informations. Rejoignez-nous pour contribuer à notre performance opérationnelle dans un environnement inclusif et innovant.

### Field Service Engineer III (LCMS) SF Bay Area, CA - Thermo Fisher Scientific
- Location: Remote, California, United States of America (remote)
- Salary: Not disclosed
- Posted: 2026-03-30
- 401(k) match: listed (not source-backed)
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Remote-California-USA/Field-Service-Engineer-III--LCMS--SF-Bay-Area--CA_R-01346638/apply
- Excerpt: Field Service Engineer III (LCMS) SF Bay Area, CA Remote, California, United States of America Embrace the opportunity to become a Field Service Engineer III, delivering expert installation, maintenance, and repair for advanced analytical and microscopy equipment. Leverage your technical skills and customer focus to support scientific innovation across research and industrial sites. Enjoy professional growth, hands-on problem-solving, and the opportunity to make a real impact in a dynamic environment.

### Forward Deployed Machine Learning Engineer - Black Forest Labs
- Location: San Francisco (USA) (unspecified)
- Salary: $180K-$270K
- Posted: 2025-09-26
- Apply: https://job-boards.greenhouse.io/blackforestlabs/jobs/4935984008
- Excerpt: Forward Deployed Machine Learning Engineer San Francisco (USA) About Black Forest Labs We're the team behind Latent Diffusion, Stable Diffusion, and FLUX - foundational technologies that changed how the world creates images and video. Our models power the tools used by millions of creators, developers, and businesses worldwide, and FLUX is among the most advanced generative systems in the world. Headquartered in Freiburg, Germany with a growing presence in San Francisco, we're scaling fast while staying true to what makes us different: research excellence, open science, and building technology that expands human creativity. Why This Role You'll live at the intersection of cutting-edge research and brutal production reality. Your customers won't just want FLUX to work-they'll need it optimized for their specific hardware, fine-tuned for their unique use cases, and integrated into systems that weren't designed for diffusion models in the first place. What You'll Work On - Ensures FLUX models perform optimally in customer environments-whether that's on-premise GPU clusters or BFL-hosted infrastructure-balancing the eternal tension between latency and output quality - Architects deep product integrations that go far beyond "here's an API endpoint"-helping customers with everything from model hosting and deployment to inference optimization techniques that haven't made it into textbooks yet - Customizes our foundation models for visual media to solve problems customers couldn't articulate until you helped them understand what's possible - Sits in technical deep-dives with customers to diagnose performance bottlenecks, then translates those findings into solutions (and sometimes into research questions for our core team)

### Field Application Scientist, Olink Proteomics (Remote - SF Bay Area, CA) - Thermo Fisher Scientific
- Location: Remote, California, United States of America (remote)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (not source-backed)
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Remote-California-USA/Field-Application-Scientist--Olink-Proteomics--Remote---SF-Bay-Area--CA-_R-01353351/apply
- Excerpt: Field Application Scientist, Olink Proteomics (Remote - SF Bay Area, CA) Remote, California, United States of America Embrace the opportunity to become a Field Application Scientist, Olink Proteomics, and provide expert technical support and training for cutting-edge proteomics solutions. Collaborate with cross-functional teams, deliver impactful product demonstrations, and help drive innovation in scientific research. Make a difference in global health and science with Thermo Fisher Scientific.

### Stagiaire – Calcul embarqué des pertes IGBT d’un onduleur moyenne tension (H/F) - GE Vernova
- Location: Belfort (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Belfort/Stagiaire---Calcul-embarqu-des-pertes-IGBT-d-un-onduleur-moyenne-tension--H-F-_R5027147-2
- Excerpt: Stagiaire – Calcul embarqué des pertes IGBT d’un onduleur moyenne tension (H/F) Belfort posted: Posted 30+ Days Ago

### Doctoral Thesis - Automated Layout Synthesis for Scalable Quantum Computing Cryogenic Circuit Design Automation (f/m/div) - Infineon Technologies
- Location: Munich (Germany) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (not source-backed)
- Apply: https://infineon.eightfold.ai/careers/job/563808970498857
- Excerpt: Doctoral Thesis - Automated Layout Synthesis for Scalable Quantum Computing Cryogenic Circuit Design Automation (f/m/div) Munich (Germany)

### Clinical Research Engagement Lead - West Region (SF Bay Area, CA) - Genentech, Inc.
- Location: South San Francisco, California, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (not source-backed)
- Apply: https://roche.wd3.myworkdayjobs.com/ROG-A2O-GENE/job/South-San-Francisco/Clinical-Research-Engagement-Lead---West-Region--South-San-Francisco--CA-_202606-114232-2/apply
- Excerpt: Clinical Research Engagement Lead - West Region (SF Bay Area, CA) South San Francisco, California, United States of America Embrace the opportunity to become a Clinical Research Engagement Lead and drive strategic partnerships across the full clinical trial lifecycle. Leverage your expertise in clinical operations, site management, and regulatory compliance to accelerate clinical trial success. Shape the future of clinical research with a global leader and make a real impact in advancing healthcare innovation.

### Ingénieur Calculs - F/H - Thales
- Location: La Ferté-Saint-Aubin, Loiret, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-06
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/La-Fert-Saint-Aubin/Ingnieur-Calculs---F-H_R0307331-1/apply
- Excerpt: Ingénieur Calculs - F/H La Ferté-Saint-Aubin, Loiret, France Rejoignez notre équipe en tant qu'Ingénieur Calculs et contribuez à des projets innovants dans le domaine de la défense et de la sécurité. Si vous êtes passionné par la modélisation et la simulation, ce poste est fait pour vous !

### Staff Software Engineer - Arc
- Location: NYC | Hybrid | SF Bay Area | Remote (hybrid)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/joinarc/cb6947cd-8512-44f5-b2a5-93b64c51c169
- Excerpt: Staff Software Engineer NYC | Hybrid | SF Bay Area | Remote Location: Prefer Onsite NYC. Open to exceptional candidates in SF Employment Type: Full-Time Hiring Manager: Andrew Rosen, Head of Engineering ABOUT ARC Arc is building the first AI-native business cash management platform. We empower high-growth companies to manage, analyze, and act on their financial data through a unified cash management, treasury, and debt-financing platform-powered by AI. Founded in 2021, Arc is backed by world-class investors (Series A), supports thousands of technology companies as customers, and manages billions of dollars in transaction volume. With offices in NYC and SF, we operate on a Monday-Wednesday in-office model (Thu-Fri optional in-office or WFH). We're at an inflection point. Large enough to matter; small enough to innovate. THE ROLE This is a critical role, with expectations unleveled for broader architectural influence, technical leadership, and impact on Arc's evolving AI-native financial platform. As a Staff Software Engineer, you will own major components across our cash management, treasury, and AI automation systems-designing for reliability, scale, safety, and speed. You'll work directly with Arc's Head of Engineering, and partner cross-functionally with leadership, product, data, and security to build the intelligence layer that powers business finance. WHAT YOU'LL DO LEAD ARCHITECTURE AND DEVELOPMENT OF ARC'S FINANCE AND AI SYSTEMS - Own end-to-end design for major platform surfaces across cash management, treasury, and debt marketplace. - Contribute to Arc's AI agent, Archie, evolving from insights → supervised actions → controlled execution inside the bank. BUILD MISSION-CRITICAL, HIGH-RELIABILITY

### Contrôleur(se) tridimensionnel (F/H) - Baker Hughes
- Location: FR-BFC-FOUGEROLLES-2-4 RUE DE FONTAINE (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://bakerhughes.wd5.myworkdayjobs.com/BakerHughes/job/FR-BFC-FOUGEROLLES-2-4-RUE-DE-FONTAINE/Contrleur-se--tridimensionnel--F-H-_R163410
- Excerpt: Contrôleur(se) tridimensionnel (F/H) FR-BFC-FOUGEROLLES-2-4 RUE DE FONTAINE posted: Posted 30+ Days Ago

### CompChem Research Scientist (Free Energy Methods) - Sr. - Principal - Genesis Molecular AI
- Location: NYC or SF Bay Area, NYC, or SF Bay Area, California or NY, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-02-06
- Apply: https://jobs.ashbyhq.com/genesis-molecular-ai/90211df1-2ae8-4fd7-a049-594c2fa45472
- Excerpt: CompChem Research Scientist (Free Energy Methods) - Sr. - Principal NYC or SF Bay Area, NYC, or SF Bay Area, California or NY, United States About Genesis Molecular AI Genesis Molecular AI unifies cutting edge molecular machine learning with rigorous physics to discover novel small molecule therapies for severe diseases. Our molecular AI platform, GEMS, combines generative models and high throughput molecular simulation to search chemical space and prioritize compounds with unprecedented speed and accuracy. We are bringing together a world-class computational team to build out the industry's fastest and most accurate small molecule property predictions, by combining the power of machine learning and physics-based methods. About the Team Our computational chemistry team partners with ML researchers, medicinal chemists, and biologists to turn our computational models into real drug candidates for our internal pipeline and our pharma collaborators. You will join a team led by experienced drug hunters and method developers across statistical mechanics, free energy methods, and computer aided drug design. About the Role We are looking for a binding free energy specialist, who is comfortable both with the theory necessary to propose new methodological ideas and with coding necessary to implement them. This individual will advance free energy methods across our platform and own their delivery. You will be the person our teams turn to when they need physics based ranking of tight binders, especially in potency regimes where current models start to flatten out. Your work will directly shape which compounds we make, which ones move forward,

### Sr Machine Learning Engineer - PayPal Holdings, Inc.
- Location: San Jose, California, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (not source-backed)
- Apply: https://paypal.wd1.myworkdayjobs.com/Jobs/job/San-Jose-California-United-States-of-America/Sr-Machine-Learning-Engineer_R0136486-1
- Excerpt: Sr Machine Learning Engineer San Jose, California, United States of America posted: Posted 30+ Days Ago

### Growth Marketer [In Person, SF] - Recall Labs
- Location: San Francisco | OnSite (onsite)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/recall/74d59397-4b51-418b-ae86-c8836867a029
- Excerpt: Growth Marketer [In Person, SF] San Francisco | OnSite As a Growth Marketer at Recall.ai https://www.recall.ai, you'll own our organic presence on the internet, by creating compelling content and getting it in front of the right people, wherever they spend time online. Our ICP is founders, product teams, and engineering teams. WHAT YOU'LL DO - Create content for our ICP, and distribute through: - Linkedin - Twitter - Reddit - Hackernews - Create content revolving around: - Early-stage startups - Sales - Engineering challenges - Optimize content and channels for sign up conversions. WHAT IT WILL BE LIKE - Huge impact. You'll have a major role in building the company culture. You get to evolve the marketing motion from the strong foundation we've already built. - No bureaucracy. You'll own and drive every initiative you work on from start to finish. We fully trust you. - Massive growth opportunities. And not just on the marketing side. Anything you want to learn about the business we'll teach you. WHY YOU SHOULDN'T JOIN - You are not ready for the occasional 60 hour work week right now. - You are not ready to work 5 days a week, in SF. - You are not comfortable working without clear structure. - You are not ready for a risky career opportunity. Even with our growth, we are still an early-stage startup. If you need something more predictable, this is not the right fit. - You're not excited about writing. You won't be able to

### Senior Software Engineer, Embedded Systems/Firmware, Pixel - Google
- Location: Mountain View, CA, USA (unspecified)
- Salary: $174K-$253K
- Posted: 2026-06-04
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSVHTvcw4VDBcNLUxa1Nbv4NFioiJpXHWOyNmFZ7dQi1EjsACxwdTARFuWLX_iC70Kvm4yKcTf_k9muRbkcSzL4ENLcjHh0Z9eoqTNLu-UeBEy3E7Rj_QCDRgJwDPw%3D%3D_V2&loc=US&title=Senior+Software+Engineer
- Excerpt: Senior Software Engineer, Embedded Systems/Firmware, Pixel Mountain View, CA, USA Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. The Google Security Architecture (GSA) is a security element in every Pixel phone's Tensor SoC. It is an independent CPU and separate from the main Application Processor, but can access the main bus of the rest of the SoC. It is responsible for securing cryptographic keys and providing services such as key derivation, key wrapping, and authentication. The GSA is present in every phone build since the introduction of the Tensor SoC (Pixel 6 and newer) and is a critical security component for Pixel phones. The team own, build, maintain and extend all the firmware running in the GSA and are responsible

### Senior Full Spectrum GEOINT (FSG) NVA - CACI
- Location: Fort Belvoir, VA, US (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (not source-backed)
- Apply: https://caci.wd1.myworkdayjobs.com/External/job/Fort-Belvoir-VA-US/Senior-Full-Spectrum-GEOINT--FSG--NVA_318764
- Excerpt: Senior Full Spectrum GEOINT (FSG) NVA Fort Belvoir, VA, US posted: Posted 7 Days Ago

### TPU RTL Design Engineer, Cloud - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $138K-$198K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRlx3V2kfLOXvYwfGD7xNXtbXJi14xxv4VIeqHESGFH6EjsACxwdTEmphvK_rqhhd94s3rfXRZD-xbrEHxChYMtX-elkfXMJi6KTWRQReCWEy58kwZPD4x9ZPDFC_A%3D%3D_V2&loc=US&title=TPU+RTL+Design+Engineer
- Excerpt: TPU RTL Design Engineer, Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an RTL Design Engineer on the Tensor Processing Units (TPU) team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. You will be responsible for the microarchitecture, design, and implementation of key digital logic blocks within the TPU. Your role requires collaborating with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver hardware. You will own critical design deliverables and contribute to the continuous improvement of our design methodologies and flows. This position offers the opportunity to manage technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers

### Software Engineer, TensorRT Specialized Platforms - New College Grad 2025 - NVIDIA Corporation
- Location: US, CA, Santa Clara (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-29
- 401(k) match: listed (not source-backed)
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Software-Engineer--TensorRT-Specialized-Platforms---New-College-Grad-2025_JR2002870
- Excerpt: Software Engineer, TensorRT Specialized Platforms - New College Grad 2025 US, CA, Santa Clara posted: Posted 14 Days Ago

### RTL Design and Integration Engineer, TPU and ML - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $138K-$198K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckW3HrwPAW6XFS0kaZT5Dh8Zu-xrameTBruIPMM9C7c06EjsACxwdTEIRn06AQPEAA86H7R-ozUW6Zn-SxJjoTQI2DaK0c_gd9nC2RfkhzUMunDL1Q2ywKVwKcVk-yg%3D%3D_V2&loc=US&title=RTL+Design+and+Integration+Engineer
- Excerpt: RTL Design and Integration Engineer, TPU and ML Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including verification, physical design, validation, and firmware, to deliver hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough

### Sr Machine Learning Engineer - Adobe Inc.
- Location: San Jose (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 16 weeks (not source-backed)
- Non-birth-parent leave: 16 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://adobe.wd5.myworkdayjobs.com/external_experienced/job/San-Jose/Sr-Machine-Learning-Engineer-4_R165400-1
- Excerpt: Sr Machine Learning Engineer San Jose posted: Posted 30+ Days Ago

### ASIC Digital Design Engineer II, Silicon Engineering - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcHsrgwWN7Y2d6pNVVICVe2b0jfdsrwKnS2Duw_RfL4yEjsACxwdTM8PdhjKksREzrwUS05bAsHYIsnAM0j18suBmBOP_jXW3Qr7CK8ogRakyjXMqLc743ndvIUFPg%3D%3D_V2&loc=IN&title=ASIC+Digital+Design+Engineer+II
- Excerpt: ASIC Digital Design Engineer II, Silicon Engineering Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role you will be a part of the team which designs the Tensor Processing Unit (TPU) core and sub-system. The TPU core is the heart of Google's Tensor SoC. You will be working through all phases of design and implementation. You will be working with Architects to come-up with microarchitecture specifications. You will use your logic design skills to convert the micro-arch into System Verilog code. You will be involved in Power, Performance and Area (PPA) experiments/proto-typing experiments early on to optimize PPA. You will also work closely with the verification team to verify the features implemented in design. You will also work with the Physical design (PD) team to take the design through PD cycle and eventual tape-out. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Use simulation/emulation/power analysis tools and techniques to

### Senior Full Spectrum GEOINT (FSG) NC - CACI
- Location: Fort Bragg, NC, US (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (not source-backed)
- Apply: https://caci.wd1.myworkdayjobs.com/External/job/Fort-Bragg-NC-US/Senior-Full-Spectrum-GEOINT--FSG--NC_319930
- Excerpt: Senior Full Spectrum GEOINT (FSG) NC Fort Bragg, NC, US posted: Posted 7 Days Ago

### Regional Business Manager - SF Bay Area - Seer
- Location: Remote (remote)
- Salary: $140K-$160K
- Posted: 2026-06-07
- Apply: https://seer.bio/careers/?gh_jid=5971853004
- Excerpt: Regional Business Manager - SF Bay Area Remote At Seer, we are passionate about empowering our customers to expand scientific discoveries and achieve exceptional scientific outcomes. Our team is growing quickly as we develop innovative approaches to solve complex biological questions. And we believe the next frontier in biology is enabled through a clearer and more complete view of the proteome - something that Seer can uniquely deliver. As we build our team, we are looking for collaborative, driven, intellectually curious people who are committed to solving complex challenges. Our culture rewards accountability and cross functional teamwork, because we believe that this enables the kind of breakthrough thinking that will accelerate our mission. Location: SF Bay Area The Role and The Team: We are looking for a collaborative, self-driven sales leader to join our team. You will be responsible for developing, driving and executing the commercial strategy within the defined US territory and supporting our global expansion. In this sales role you will develop deep customer relationships within academic, Biotech, Pharma and Government accounts, establish the Seer technology for unbiased proteomics as the market leader, support the build out of Seer's commercial organization and meet or exceed the commercial targets set for the company. This role will be field and home-office based. Responsibilities and goals: Develop a territory and account-based sales plan for the territory Execute the plan for the territory to meet or exceed company goals Deliver presentations on the Seer technology to customers in seminars and smaller meetings

### Senior Staff Engineer, AI - Arc
- Location: NYC | Hybrid | SF Bay Area | Remote (hybrid)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://jobs.ashbyhq.com/joinarc/bdddc3a3-312c-434e-a0ae-774be17e75c7
- Excerpt: Senior Staff Engineer, AI NYC | Hybrid | SF Bay Area | Remote Location: Prefer Onsite NYC or SF. Open to exceptional Remote candidates Employment Type: Full-Time Hiring Manager: Andrew Rosen, Head of Engineering ABOUT ARC Arc is building the first AI-native business cash management platform. We empower high-growth companies to manage, analyze, and act on their financial data through a unified cash management, treasury, and debt-financing platform-powered by AI. Founded in 2021, Arc is backed by world-class investors (Series A), supports thousands of technology companies as customers, and manages billions of dollars in transaction volume. With offices in NYC and SF, we operate on a Monday-Wednesday in-office model (Thu-Fri optional in-office or WFH). We're at an inflection point. Large enough to matter; small enough to innovate. THE ROLE We are seeking a Senior Staff Engineer, AI to join Arc's engineering organization as a key technical leader. This is a foundational AI role, responsible for driving the research direction, execution, and delivery of Arc's AI-powered products across both cash management and debt marketplace products. WHAT YOU'LL DO LEADERSHIP & STRATEGY - Drive Arc's most critical AI initiatives end-to-end in a cross-functional environment. - Serve as a company-wide thought leader on foundational models, LLMs, agent systems, retrieval, and emerging research. - Establish and refine Arc's internal AI strategy, research direction, and technology roadmap. EXECUTION & PRODUCT IMPACT - Collaborate with engineering, product, design, and leadership to build and improve AI-powered financial products. - Build evaluation frameworks, model-improvement infrastructure, and production-grade AI

### Leader Technique Simulation Numérique / EF (F/H) - Michelin
- Location: Clermont-Ferrand (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- Apply: https://michelinhr.wd3.myworkdayjobs.com/Michelin/job/Clermont-Ferrand/Ingnieure-Simulation-en-lments-Finis--F-H----CDI_R-2025044999
- Excerpt: Leader Technique Simulation Numérique / EF (F/H) Clermont-Ferrand posted: Posted 15 Days Ago

### RTL Design and Integration Engineer - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $116K-$166K
- Posted: 2026-06-10
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckR4BUKQ53z5jfRBgUqfjLXTgKNoxP5AC_sxqJ9Xg5mIeEjsACxwdTAxmgCiiIE8mdrkpFNTul_qHOIjieOf6Rkms9RO_EmQdcXX9AAG_o3AIt4_JqOMn78cIlYYD1w%3D%3D_V2&loc=US&title=RTL+Design+and+Integration+Engineer
- Excerpt: RTL Design and Integration Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and

### Analog Design Engineer Sr Staff - d-Matrix
- Location: Santa Clara, Santa Clara, Ca, Ca, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-19
- Apply: https://jobs.ashbyhq.com/d-matrix/8cd5868b-fe7e-429d-bf5a-63b551036878
- Excerpt: Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in

### Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $163K-$237K
- Posted: 2026-06-09
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSgalpQhzM5Ichn4Kev0ABmyItMwQYLWnnrpagdWX5eqEjsACxwdTLGpYbkeUqFv9jbOOe4BYIoPkADmjeIPXdAYCjvHAC_KBtAKQe4QJFNsAIk4l4TeYLnCYHwAFQ%3D%3D_V2&loc=US&title=Senior+TPU+RTL+Design+Engineer
- Excerpt: Senior TPU RTL Design Engineer, Networking, Inter-Chip Interconnects Sunnyvale, CA, USA In this role, you will work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the core components of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in data centers. As a member of the inter-chip interconnect team, you will play an important role in designing ASIC/SoC hardware for AI and networking accelerators that drive the computational workloads behind Google's most important products. Our hardware accelerators power nearly every product Google offers. Our primary focus is AI acceleration. You will design RTL IP with a focus on chip-to-chip high-speed interconnect subsystems. You will have dynamic, multi-faceted responsibilities in areas such as project definition, RTL design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators. You will have the opportunity to solve challenging technical problems at the forefront of AI hardware, working in a dynamic and collaborative environment. The AI

### Forward Deployed Engineer (FDE) - SF - OpenAI
- Location: San Francisco, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2025-08-06
- 401(k) match: listed (not source-backed)
- Apply: https://jobs.ashbyhq.com/openai/305a4b22-7ff9-4fa5-9229-c6a22c9aa64f
- Excerpt: Forward Deployed Engineer (FDE) - SF San Francisco, California, United States About the team OpenAI's Forward Deployed Engineering team partners with customers to turn research breakthroughs into production systems. We operate at the intersection of customer delivery and core platform development. About the role Forward Deployed Engineers (FDEs) lead complex end-to-end deployments of frontier models in production alongside our most strategic customers. You will own discovery, technical scoping, system design, build, and production rollout, partnering directly with customer engineering and domain teams. You will measure success through production adoption, measurable workflow impact, and eval-driven feedback that changes product and model roadmaps. You'll work closely with our Product, Research, Partnerships, GRC, Security, and GTM teams. This role is based in San Francisco. We use a hybrid work model of 3 days in the office per week. We offer relocation assistance. Travel up to 50% is required. In this role you will - Own technical delivery across multiple deployments from first prototype to stable production - Build full-stack systems that deliver customer value and sharpen how we learn - Embed closely with customer teams, understand their needs, and guide adoption of what you build - Scope work, sequence delivery, and remove blockers early - Make trade-offs between scope, speed, and quality; adjust plans to protect delivery - Contribute directly in the code when progress or clarity depends on it - Codify working patterns into tools, playbooks, or building blocks that others can use - Share field feedback that helps Research and Product

### ASIC Physical Design Tools, Flows, Methodologies Manager - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdA65qFUzIMVLO_qpz0DNp3VEGiDi--dD76uednIOm7mEjsACxwdTGTK8Ty7-tc9OpPxcMp3gpC2QfV58Ip69SKMasdvH2uZn6ZCXIhkWceu3r0ksfD-cHEB3yQhqA%3D%3D_V2&loc=US&title=ASIC+Physical+Design+Tools
- Excerpt: ASIC Physical Design Tools, Flows, Methodologies Manager Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will manage and lead a team of TFM engineers responsible for the physical design flows that power our Tensor Processing Unit (TPU) products. You will guide your team in developing, deploying, and supporting a register-transfer level (RTL)-to-GDS infrastructure. You will bridge design engineering and electronic design automation (EDA) capabilities, balancing resources and managing priorities across projects, feature requests, and bug resolutions to ensure silicon delivery. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by

### Architecte Salesforce F/H - Orange
- Location: BALMA,FRANCE (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Apply: https://careers-jobin.icims.com/jobs/2127/architecte-salesforce-f-h/job/login
- Excerpt: Architecte Salesforce F/H BALMA,FRANCE En tant qu'Architecte Salesforce (F/H), et intégré au sein de l'Agence Conseil & Expertise de la région Grand Sud-Ouest, vous jouerez un rôle clé dans la conception, l'intégration et le déploiement de...

### Senior Design and Integration Engineer, Cloud TPU - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $163K-$237K
- Posted: 2026-06-10
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (not source-backed)
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcYoH0HRbh82KuqBliMW9QkTPf8wTubHV35vD__Rus2pEjsACxwdTCAFWkOXs-0k-evitw1Gxp6FZ7oC2p3SFFsFuYJxEDmWjaU1NMFB8DDl4nIazbeA_1J8LF9toA%3D%3D_V2&loc=US&title=Senior+Design+and+Integration+Engineer
- Excerpt: Senior Design and Integration Engineer, Cloud TPU Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. Join the team designing and developing the On-Chip Network of Google's next-generation Tensor Processing Units (TPUs), the custom-built accelerators powering our AI and machine learning workloads in datacenters. You will be responsible for the microarchitecture, design, implementation, and integration of key digital logic blocks within the TPU. This role requires close collaboration with cross-functional teams, including Verification, Physical Design, Validation, and Firmware, to deliver cutting-edge hardware. You will own critical design deliverables, help with integration efforts, and contribute to the continuous improvement of our design methodologies and flows. As an RTL Design Engineer on the TPU team, you will be a key contributor to the development of Google's AI accelerators. You will leverage your expertise in digital logic design, computer architecture, and RTL coding to create innovative and efficient hardware solutions. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering

### PO Migration Polarion (F/H) - Thales
- Location: Vélizy-Villacoublay, Yvelines, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-07
- 401(k) match: listed (not source-backed)
- Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Vlizy-Villacoublay/PO-Migration-Polarion--F-H-_R0322848-1/apply
- Excerpt: PO Migration Polarion (F/H) Vélizy-Villacoublay, Yvelines, France Nous recherchons un Product Owner Migration Polarion pour rejoindre notre équipe dynamique chez Thales. Vous serez responsable de la gestion de la vision produit, de la priorisation des backlogs et de la collaboration avec les parties prenantes pour assurer le succès des projets. Rejoignez-nous pour façonner l'avenir de la technologie !

---
Source-backed benefit claims include source links; other benefit values are labeled separately.