# FewerJobs export - 100 curated jobs
Generated: 2026-06-20T02:18:55.384Z
Source: https://fewerjobs.com

## Filters applied
- **q**: Quantum Circuits
- **quality_floor**: default
- **match_401k_strict**: true
- **parental_strict**: true
- **non_birth_strict**: true
- **pto_strict**: true
- **include_older**: false
- **verified_benefits_only**: true
- **apply_url_verified**: false
- **page**: 1
- **per_page**: 100
- **sort**: relevance

## Jobs
### Research Scientist, Quantum Error Correction, Quantum AI - Google
- Location: Goleta, CA, USA; +1 more (unspecified)
- Salary: $147K-$211K
- Posted: 2026-06-09
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckeFKgCw_hiCM4RsHv08x6SjfiLbS3hiNrhvy5jGaHBSiEjsACxwdTNwi6A90gYTQaiIp7AyshWmOSHUpN_Fha0GYE33Z3Wf7xaSkkNk8Kildvr-8pYvtrZ3A6tiUKw%3D%3D_V2&loc=US&title=Research+Scientist
- Excerpt: Research Scientist, Quantum Error Correction, Quantum AI Goleta, CA, USA; +1 more As a Quantum Research Scientist, you will develop quantum error correction (QEC) schemes for fault-tolerant quantum computing, specifically focusing on superconducting qubits and high-connectivity platforms. You will develop and analyze QEC for modular architectures, addressing challenges such as entangling links between chips that are slower or more faulty than on-chip gates. Your role involves developing fault-tolerant circuits for logical gates while navigating hardware tradeoffs on connectivity and engineering higher accuracy decoding algorithms for high-connectivity codes, such as Low-Density Parity-Check (LDPC) codes. Beyond the technical design, you will contribute to the wider research community by sharing and publishing your findings. These contributions will be inspired by internal projects as well as through active collaborations with research programs at partner universities and technical institutes globally. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $147000 - $211000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop new quantum codes that achieve high encoding rate, high distance, or favorable layout in hardware. Important examples include LDPC codes and yoked encoding schemes. Adapt error correction circuits

### Quantum Error Correction Metrologist, Quantum AI - Google
- Location: Goleta, CA, USA (unspecified)
- Salary: $147K-$211K
- Posted: 2026-06-08
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckf0eqVxV016JA8D6mdgpi7tdB6BkK8_kHRSsyMvT8-AEEjsACxwdTOR13QGA4Mqv_xIx7vQ40YMUjgTK8HHWrYJF1R8I1Mu1KsTYv8Z-WCSUmoF3-ioNb-35hmplBA%3D%3D_V2&loc=US&title=Quantum+Error+Correction+Metrologist
- Excerpt: Quantum Error Correction Metrologist, Quantum AI Goleta, CA, USA As an organization, Google maintains a portfolio of research projects driven by fundamental research, new product innovation, product contribution and infrastructure goals, while providing individuals and teams the freedom to emphasize specific types of work. As a Research Scientist, you'll setup large-scale tests and deploy promising ideas quickly and broadly, managing deadlines and deliverables while applying the latest theories to develop new and improved products, processes, or technologies. From creating experiments and prototyping implementations to designing new architectures, our research scientists work on real-world problems that span the breadth of computer science, such as machine (and deep) learning, data mining, natural language processing, hardware and software performance analysis, improving compilers for mobile platforms, as well as core search and much more. As a Research Scientist, you'll also actively contribute to the wider research community by sharing and publishing your findings, with ideas inspired by internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $147000 - $211000 (USD) + 15% bonus target + bonus + equity +

### AMS/RF Board Designer, Quantum AI - Google
- Location: Goleta, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQ0osbW7lM07kHPZKbezrCaTMsBw6Kn0FZkzYznZSu9WEjsACxwdTB-78lJRoIDMQP_IVIkUQcoBk_8Ex60Yc1oVmvT6RugF_zaj38Z8EQUQxbKrCPU3soeKt7Yj1A%3D%3D_V2&loc=US&title=AMS/RF+Board+Designer
- Excerpt: AMS/RF Board Designer, Quantum AI Goleta, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a key team member in the development of quantum control and measurement systems. You will leverage radio frequency (RF), analog, or mixed-signal expertise to implement high-performance board-level designs which are then used to control our quantum computers. You will work with ASIC designers to architect system-level solutions which allow us to improve our system density and performance. You will document your designs and measurement results and present these data to relevant stakeholders. You will support team-members using the equipment you have designed as they integrate it into larger quantum computing systems. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Support deployment and operations of electronics to Google's fleet of quantum computers.

### Intern (f/m/d) for Quantum Sensing Demonstrator and Technical Documentation - NXP Semiconductors
- Location: Hamburg (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Hamburg/Intern--f-m-d--for-Quantum-Sensing-Demonstrator-and-Technical-Documentation_R-10063075
- Excerpt: Intern (f/m/d) for Quantum Sensing Demonstrator and Technical Documentation Hamburg posted: Posted 30+ Days Ago

### Research Scientist, Optical Engineering Neutral Atoms, Quantum AI - Google
- Location: Boulder, CO, USA (unspecified)
- Salary: $174K-$253K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckb8WUk_9_cdOq29auaH_RH77v6lIgHtOf91PRQSQm90DEjsACxwdTGl6AnFxKcwvwMVdCMDpdIBLvRr9tYxUudg2AZ2ZXQQfpXxCcPb1Kkk-j8Fq4iIP-n78HSC6IQ%3D%3D_V2&loc=US&title=Research+Scientist
- Excerpt: Research Scientist, Optical Engineering Neutral Atoms, Quantum AI Boulder, CO, USA As an organization, Google maintains a portfolio of research projects driven by fundamental research, new product innovation, product contribution and infrastructure goals, while providing individuals and teams the freedom to emphasize specific types of work. As a Research Scientist, you'll setup large-scale tests and deploy promising ideas quickly and broadly, managing deadlines and deliverables while applying the latest theories to develop new and improved products, processes, or technologies. From creating experiments and prototyping implementations to designing new architectures, our research scientists work on real-world problems that span the breadth of computer science, such as machine (and deep) learning, data mining, natural language processing, hardware and software performance analysis, improving compilers for mobile platforms, as well as core search and much more. As a Research Scientist, you'll also actively contribute to the wider research community by sharing and publishing your findings, with ideas inspired by internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. The full potential of quantum computing will be unlocked with a computer capable of error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Google Research is building the next generation of intelligent systems for all Google products. To achieve this, we're working on projects that utilize the latest computer science techniques

### Research Scientist, Neutral Atoms, Quantum AI - Google
- Location: Boulder, CO, USA (unspecified)
- Salary: $147K-$211K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRCEA5LpirV5PEzILs_ZKnhCn5YtHjbJusEv32I5lRzXEjsACxwdTL9-H6p7qU8fjLptsmR-zuxHdCbInsXk3rjZhUypGz-Pwi3yubGKH714itiMkBLSRqb6n5_gWA%3D%3D_V2&loc=US&title=Research+Scientist
- Excerpt: Research Scientist, Neutral Atoms, Quantum AI Boulder, CO, USA As an organization, Google maintains a portfolio of research projects driven by fundamental research, new product innovation, product contribution and infrastructure goals, while providing individuals and teams the freedom to emphasize specific types of work. As a Research Scientist, you'll setup large-scale tests and deploy promising ideas quickly and broadly, managing deadlines and deliverables while applying the latest theories to develop new and improved products, processes, or technologies. From creating experiments and prototyping implementations to designing new architectures, our research scientists work on real-world problems that span the breadth of computer science, such as machine (and deep) learning, data mining, natural language processing, hardware and software performance analysis, improving compilers for mobile platforms, as well as core search and much more. As a Research Scientist, you'll also actively contribute to the wider research community by sharing and publishing your findings, with ideas inspired by internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. As a Research Scientist, you will be joining a team building a fault-tolerant quantum computer based on neutral atoms. You will be involved in research and development to advance the neutral atom quantum platform, translating theoretical concepts into practical experimental setups.The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is

### Development Manager Optimization, Quantum & AI (m/f/d) - SAP
- Location: Region Europe | Country Germany | Internal Posting Location Walldorf (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Walldorf-Development-Manager-Optimization%2C-Quantum-&-AI-%28mfd%29-69190/1394423833/
- Excerpt: Development Manager Optimization, Quantum & AI (m/f/d) Region Europe | Country Germany | Internal Posting Location Walldorf We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll do: Enterprise software is shifting from passive process infrastructure to active decision infrastructure. SAP is pioneering autonomous enterprise decision systems that combine optimization science, quantum computing, and artificial intelligence to help organizations navigate complexity and execute under real-world constraints. The Development Manager Optimization, Quantum & AI will lead the transformation of an established data science team into a strategic contributor to SAP's autonomous decision infrastructure. You will manage a team with ten years of experience in classical analytics and guide their evolution toward building decision-capable systems that evaluate, optimize, orchestrate, and execute under dynamic constraints. This role requires dual leadership: transforming team capabilities while leveraging deep domain expertise to accelerate impact. You will bridge classical data science with decision infrastructure-moving from descriptive analytics to prescriptive s

### Fabrication Equipment Engineer, Quantum AI - Google
- Location: Goleta, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQfhSSweHV2PCsmMWmZ1SSxXb-gTzI49PoDLw0CUa5oDEjsACxwdTP4h1kYYdAFzv7xEYyG5wc3r6x3gvpRogwcigV-hU_vmbysrS5bZkGlV55-UrZKiTEiO4DmReQ%3D%3D_V2&loc=US&title=Fabrication+Equipment+Engineer
- Excerpt: Fabrication Equipment Engineer, Quantum AI Goleta, CA, USA The Quantum Equipment Engineering team ensures the installation, reliability, and optimization of the manufacturing fleet used to produce high-quality quantum devices. As an Equipment Engineer, you will own the performance of complex semiconductor tools within our fabrication facility. You will lead root-cause troubleshooting, manage vendor relationships, and drive continuous improvement projects to maximize tool availability. Beyond maintenance, you will analyze failure modes and implement upgrades. Your technical expertise and safety-first mindset will ensure our facility maintains the precise stability required for Quantum Computing breakthroughs. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Perform complex preventative maintenance, diagnostics, and repairs to ensure the maximum uptime and optimal performance of critical fabrication tools. Lead the scoping, evaluation, and procurement of new process equipment tailored for quantum manufacturing, and drive the qualification of these tools. Manage equipment installations, retrofits, and upgrades, serving as the primary technical liaison with external vendors to ensure effective project execution. Support operations across multiple local facilities, including shared research labs, ensuring consistent equipment

### Senior Technology Project Specialist - Quantum Computing (f/m/d) - SAP
- Location: Region Europe | Country Germany | Internal Posting Location Walldorf (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Walldorf-Senior-Technology-Project-Specialist-Quantum-Computing-%28fmd%29-69190/1369614233/
- Excerpt: Senior Technology Project Specialist - Quantum Computing (f/m/d) Region Europe | Country Germany | Internal Posting Location Walldorf We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll do SAP is launching a bold, long-term initiative to explore the transformative potential of Quantum Technologies. Anchored within the Office of the CTO, we are building a high-caliber, world-class team of experts to create a center of expertise for Quantum Computing. This central team, reporting to SAP's Head of Quantum, is responsible for orchestrating development efforts across the company and managing the complex stakeholder landscape. As the Senior Technology Project Specialist, you will act as the organizational backbone of this initiative, serving as a key business partner to the Head of Quantum. Your role is less about developing strategy and more about driving its execution through flawless organization, reporting, and coordination. You will ensure the day-to-day business of our quantum initiative runs smoothly, enabling the team to focus on achieving our ambitious goals. The Role · Serve as

### Technical Lead, Software Technical Infrastructure, Quantum AI - Google
- Location: Seattle, WA, USA; +1 more (unspecified)
- Salary: $207K-$301K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcnlrpfzEVXqwW8ZSBI6dRbIG0eDFfgpJrT5bIruBRg6EjsACxwdTGHlTyxhH3we6C_jMrWU_2nihmfnB0L5TBo84Am_12t4r1Pjb6-8ZDOnluJSUI-cxplscWYchw%3D%3D_V2&loc=US&title=Technical+Lead
- Excerpt: Technical Lead, Software Technical Infrastructure, Quantum AI Seattle, WA, USA; +1 more Like Google's own ambitions, the work of a Software Engineer goes beyond just Search. Software Engineering Managers have not only the technical expertise to take on and provide technical leadership to major projects, but also manage a team of Engineers. You not only optimize your own code but make sure Engineers are able to optimize theirs. As a Software Engineering Manager you manage your project goals, contribute to product strategy and help develop your team. Teams work all across the company, in areas such as information retrieval, artificial intelligence, natural language processing, distributed computing, large-scale system design, networking, security, data compression, user interface design; the list goes on and is growing every day. Operating with scale and speed, our exceptional software engineers are just getting started -- and as a manager, you guide the way. With technical and leadership expertise, you manage engineers across multiple teams and locations, a large product budget and oversee the deployment of large-scale projects across multiple sites internationally. Google's Quantum AI team builds and runs algorithms on today's world leading quantum computers. As these machines grow from research prototypes into products, the software that orchestrates and executes quantum computations will need to transition into a form that more closely resembles traditional software products. In this role, you will manage and lead a team within Quantum AI. You will drive cross-team alignment on RPC standardization and prioritize and guide the direction of related sub-projects.

### Senior Technology Researcher/Developer, Quantum Simulation (f/m/d) - SAP
- Location: Region Europe | Country Germany | Internal Posting Location Garching (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Garching-bei-M%C3%BCnchen-Senior-Technology-ResearcherDeveloper%2C-Quantum-Simulation-%28fmd%29-85748/1370869833/
- Excerpt: Senior Technology Researcher/Developer, Quantum Simulation (f/m/d) Region Europe | Country Germany | Internal Posting Location Garching We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll do Summary: SAP is launching a bold, long-term initiative to explore the transformative potential of Quantum Technologies in enterprise software. Anchored within the Office of the CTO and led by a dedicated Head of Quantum, we are building a high-caliber, world-class team of experts to create a center of expertise for Quantum Computing. This team drives SAP's strategy, orchestrates development efforts across the company, and manages the internal and external stakeholder landscape. As a Senior Technology Researcher/Developer Simulation, you will be a pivotal member of this central team. You will be responsible for planning and coordinating SAP-wide efforts to leverage Quantum Computing for complex simulation problems, particularly in areas like Financial Planning and other Lines of Business (LOBs). The Role: Plan, coordinate, and drive SAP's strategic efforts in leveraging Quantum Computing for simulation problems, identifying high-impact use cases in collaboration

### Senior Staff Research Scientist, Quantum Error Correction, Quantum AI - Google
- Location: Goleta, CA, USA (unspecified)
- Salary: $262K-$365K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU0N6o_3h5uZmsR3pyV32c0kgR-QQRIUi6NRAQwxaDFkEjsACxwdTMlGpuSdI2UqCmnEvk2Nyc9IkMl2ZeNUJE0htEJVKoKKHEf-UnUBxcOdkCjHoReEuRL02kVudQ%3D%3D_V2&loc=US&title=Senior+Staff+Research+Scientist
- Excerpt: Senior Staff Research Scientist, Quantum Error Correction, Quantum AI Goleta, CA, USA In this role, you will be a senior researcher on the quantum error correction team within Quantum AI, responsible for setting research agendas into new and improved forms of quantum error correction. You will explore exciting research directions including quantum LDPC codes and compact circuits for non-clifford gates such as magic-state cultivation. As a Research Scientist, you will actively contribute to the wider research community by sharing and publishing your findings, with ideas inspired by internal projects as well as from collaborations with research programs at partner universities and technical institutes all over the world. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $262000 - $365000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop new quantum codes that achieve high encoding rate, high distance, or favorable layout in hardware. Develop new constructions for non-clifford logical gates. Analyze fault-tolerant circuits for syndrome measurement and logical operations. Minimum qualifications: PhD or equivalent experience in a domain relevant to quantum computing, such as math, physics, computer science, or electrical engineering. 10 years of experience

### Materials Engineer, Quantum AI - Google
- Location: Santa Barbara, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQ-6Dz5ASwMiu580clhgcr2Kd3icn4ZjWb7Pc0oqUdunEjsACxwdTDYTe56JpJRDwKrlWQU39LMjJ27KvhT4r_QUwf2roAtBqWsHcwMPY0hpfOpx6rsfrukpWnWp4g%3D%3D_V2&loc=US&title=Materials+Engineer
- Excerpt: Materials Engineer, Quantum AI Santa Barbara, CA, USA In this role, you will accelerate our investigations into new materials, associated fabrication processes, and testing procedures. You will be responsible for developing and troubleshooting new and existing processes for the fabrication of wiring, interconnects, and packaging components that are critical for building our next generation of quantum computers. You will collaborate with other researchers and engineers on the Quantum Artificial Intelligence team to develop new materials, use and expand our current capabilities, and identify processes and equipment to take us in new directions of higher performance materials for more densely-integrated superconducting quantum computing systems. You will work directly with research scientists and other hardware engineers to develop materials to enhance our superconducting hardware stack including packaging, input/output, and associated filtering. You will drive hardware implementation and testing efforts to validate these materials in the lab by building and analyzing materials using performance focused experiments.The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Research and develop new materials for use in wiring, interconnects and packaging

### Staff Silicon Physical Design Engineer, Quantum AI - Google
- Location: Mountain View, CA, USA; +1 more (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka6ynNv-mDgL43cCHuU-QcnkQeaVPfXvQdRR5qXxalNxEjsACxwdTJz6IPcZdARe4StyfvFv27I07rEtCUPBWqIO1af98KffnC2Z2GFag9fhjjmiLDiJZLrEJXVnUA%3D%3D_V2&loc=US&title=Staff+Silicon+Physical+Design+Engineer
- Excerpt: Staff Silicon Physical Design Engineer, Quantum AI Mountain View, CA, USA; +1 more In this role, you will be a vital member of the quantum electronics team, providing technical leadership in the area of ASIC implementation as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital designers and RF/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. You will own the digital RTL-to-GDS2 process, developing standard ASIC implementation flows and using these flows to transform RTL-level designs into fabrication-ready GDS; this will involve leading external implementation teams through the ASIC digital implementation process. You will be involved in vendor selection, vendor program management, Statement of Work (SOW) documentation, and managing foundry and post-silicon vendor activities related to silicon quality. You will collaborate with adjacent teams and members of the quantum electronics team to contribute to the long-term ASIC strategy. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus +

### Sr. Quantum Information Scientist - Leidos
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://leidos.wd5.myworkdayjobs.com/External/job/Huntsville-AL/Sr-Quantum-Information-Scientist_R-00184243
- Excerpt: Sr. Quantum Information Scientist 2 Locations posted: Posted 15 Days Ago

### Silicon Design Verification Engineer, Quantum AI - Google
- Location: Mountain View, CA, USA; +1 more (unspecified)
- Salary: $138K-$198K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZBrlSIJ2RP0JswxqGM5BOAeAy80x62shuzWXEYtvo9mEjsACxwdTDuhKmYc0SPC0qbjgg04TXclBqiPhj2OviUIuP9twM6BXqcXGSdAZKNtGIhuEt9RexYAzZiuLg%3D%3D_V2&loc=US&title=Silicon+Design+Verification+Engineer
- Excerpt: Silicon Design Verification Engineer, Quantum AI Mountain View, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be a vital member of the quantum electronics team, providing key technical contributions in the area of ASIC design verification (DV) as we realize sophisticated electronics for control and readout of our future quantum computers. You will work as part of a team of digital, DV, physical design, and radio frequency/analog/mixed-signal engineers, collaborating with adjacent teams in the electronic, software, and quantum engineering areas to implement complex ASICs for use in the readout and control of our scaled quantum processors. As a Silicon DV Engineer, you will help drive the DV of all of Quantum's control and readout electronics. You will contribute to the entire verification lifecycle for our ASICs, collaborating with ASIC architects, digital designers to understand the chip functional requirements, plan out verification plans, and drive execution of those plans in collaboration with other DV engineers. You will build out and track coverage metrics to ensure thorough verification of designs. You will also work with external IP vendors, overseeing the DV work that they directly provide on their own IP and collaborating with these vendors to create suitable DV integration coverage. The full potential

### Quantum Information Research Scientist - Leidos
- Location: Lawton, OK (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://leidos.wd5.myworkdayjobs.com/External/job/Lawton-OK/Quantum-Information-Research-Scientist_R-00184282
- Excerpt: Quantum Information Research Scientist Lawton, OK posted: Posted 15 Days Ago

### Security Engineer - Cryptographic Engineer for Post Quantum Cryptography - The PNC Financial Services Group, Inc.
- Location: 6 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://pnc.wd5.myworkdayjobs.com/External/job/Two-PNC-Plaza-PA374/Security-Engineer---Cryptographic-Engineer-for-Post-Quantum-Cryptography_R224478-1
- Excerpt: Security Engineer - Cryptographic Engineer for Post Quantum Cryptography 6 Locations posted: Posted 8 Days Ago

### Product Manager Optimization, Quantum & AI - SAP
- Location: Region Europe | Country Hungary | Internal Posting Location Budapest (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Budapest-Product-Manager-Optimization%2C-Quantum-&-AI-1031/1396293933/
- Excerpt: Product Manager Optimization, Quantum & AI Region Europe | Country Hungary | Internal Posting Location Budapest We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you'll do: Summary: Enterprise software is shifting from passive process infrastructure to active decision infrastructure. SAP is pioneering autonomous enterprise decision systems that combine optimization science, quantum computing, and artificial intelligence to help organizations navigate complexity and execute under real-world constraints. The Product Manager Optimization, Quantum & AI will own the strategy and roadmap for highly technical products within SAP's business application portfolio. You will translate the vision of autonomous decision systems into deployable enterprise solutions that create measurable value across diverse domains-from supply chain and manufacturing to finance, HR, procurement, and customer operations. This role requires bridging two worlds: deep technical understanding of optimization, quantum computing, and AI architectures on one side, and sharp business acumen for enterprise operations on the other. You will work at the intersection of cutting-e

### Digital Engineer for Integrated Circuits (Graduate) (f/m/d) - NXP Semiconductors
- Location: Munich (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-27
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/Munich/Digital-Engineer-for-Integrated-Circuits--Graduate---f-m-d-_R-10063430
- Excerpt: Digital Engineer for Integrated Circuits (Graduate) (f/m/d) Munich posted: Posted 16 Days Ago

### Senior Research Scientist, Superconducting Digital Electronics, Quantum AI - Google
- Location: Cambridge, MA, USA; +5 more (unspecified)
- Salary: $174K-$253K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckU9OdrBuwpSRBOIXEdYVplduLEyWqRGAKDUVO_nIFJqREjsACxwdTNV6erPcLK3AaQuSE58YIWPI7gePy-rGUNn7MjbcUmKTf4Rg8MqPcInQuHgOr5DOpm93d_N-CA%3D%3D_V2&loc=US&title=Senior+Research+Scientist
- Excerpt: Senior Research Scientist, Superconducting Digital Electronics, Quantum AI Cambridge, MA, USA; +5 more As a Research Scientist, your primary focus will be designing and simulating superconductor digital logic circuits (such as single flux quantum (SFQ) logic and adiabatic quantum flux parametron (AQFP) logic) for qubit control and readout. You will engage in co-design loops with qubit designers and superconducting digital circuit designers, utilizing advanced IC design tools, numerical circuit simulation techniques and 3D electromagnetic modeling to optimize signal integrity, minimize crosstalk, manage thermal budgets, and aim performance metrics required for coherent control of qubits. You will also interface with fabrication engineers to help define and establish IC design standards that are compatible for both the sensitive superconducting qubits and the co-located cryogenic control electronics. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computer. This work is critical to building a fully integrated, modular chip stack that combines superconducting qubits with their control electronics directly within the cryogenic environment, accelerating the path toward large-scale, error-corrected quantum computers. The full potential of quantum computing will be unlocked with a large-scale computer capable of complex, error-corrected computations. Google Quantum AI's mission is to build this computer and unlock solutions to classically intractable problems. Our roadmap is focused on advancing the capabilities of quantum computing and enabling meaningful applications.Individual pay is determined by factors including job-related skills, experience, and relevant

### Hardware Engineer (PCB, Circuit Design, Industrialization, Wireless, ECAD) Relocation Assistance/Sign On Bonus - GE Vernova
- Location: Rochester (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Rochester/Hardware-Engineer---Experienced--PCB--Circuit-Design--Industrialization--Wireless--ECAD--Relocation-Assistance-Sign-On-Bonus_R5043786-2
- Excerpt: Hardware Engineer (PCB, Circuit Design, Industrialization, Wireless, ECAD) Relocation Assistance/Sign On Bonus Rochester posted: Posted 8 Days Ago

### Analog Mixed Signal Circuit Design - NXP Semiconductors
- Location: San Jose (Rose Orchard) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://nxp.wd3.myworkdayjobs.com/Careers/job/San-Jose-Rose-Orchard/Analog-Mixed-Signal-Circuit-Design_R-10061418
- Excerpt: Analog Mixed Signal Circuit Design San Jose (Rose Orchard) posted: Posted 7 Days Ago

### Staff R&D Engineer-Flexible Circuits Expert - Abbott Laboratories
- Location: United States - Minnesota - Plymouth (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-21
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://abbott.wd5.myworkdayjobs.com/abbottcareers/job/United-States---Minnesota---Plymouth/Staff-R-D-Engineer-Flexible-Circuits-Expert_31143628-1
- Excerpt: Staff R&D Engineer-Flexible Circuits Expert United States - Minnesota - Plymouth posted: Posted 22 Days Ago

### Principal Electrical Engineer-Digital Electronics Circuit Design - Raytheon Technologies
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-MA-TEWKSBURY-TB1--50-Apple-Hill-Dr--ASSABET-BLDG/Principal-Electrical-Engineer-Digital-Electronics-Circuit-Design_01838047
- Excerpt: Principal Electrical Engineer-Digital Electronics Circuit Design 2 Locations posted: Posted 30+ Days Ago

### Lead Electrical Design Engineer - Circuit Breaker - GE Vernova
- Location: Charleroi USA (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Charleroi-USA/Lead-Electrical-Design-Engineer---Circuit-Breaker_R5039029-2
- Excerpt: Lead Electrical Design Engineer - Circuit Breaker Charleroi USA posted: Posted 30+ Days Ago

### Software Engineer – Power Systems Short-Circuit Analysis - GE Vernova
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Hyderabad/Software-Engineer_R5042257-2
- Excerpt: Software Engineer – Power Systems Short-Circuit Analysis 2 Locations posted: Posted 17 Days Ago

### Senior Test Engineer, In-Circuit Test - Rockwell Automation
- Location: Monterrey, Nuevo Leon, Mexico (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://rockwellautomation.wd1.myworkdayjobs.com/External_Rockwell_Automation/job/Monterrey-Nuevo-Leon-Mexico/Senior-Test-Engineer--In-Circuit-Test_R26-2568
- Excerpt: Senior Test Engineer, In-Circuit Test Monterrey, Nuevo Leon, Mexico posted: Posted 30+ Days Ago

### Ingénieur Disjoncteur Courant Continu H/F / DC Circuit Breaker Engineer (M/F) - GE Vernova
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Villeurbanne/Ingnieur-Disjoncteur-Courant-Continu-H-F---DC-Circuit-Breaker-Engineer--M-F-_R5036546-2
- Excerpt: Ingénieur Disjoncteur Courant Continu H/F / DC Circuit Breaker Engineer (M/F) 2 Locations posted: Posted 30+ Days Ago

### Principal Engineer, Integrated Circuit Design - Abbott Laboratories
- Location: 5 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-21
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://abbott.wd5.myworkdayjobs.com/abbottcareers/job/United-States---California---Sunnyvale/Principal-Engineer--Integrated-Circuit-Design_31146615-1
- Excerpt: Principal Engineer, Integrated Circuit Design 5 Locations posted: Posted 22 Days Ago

### Senior Manager - Quality Engineering and Continuous Improvement – Dead tank Circuit-breakers - GE Vernova
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/Charleroi-USA/Senior-Manager---Quality-Engineering-and-Continuous-Improvement---Dead-tank-Circuit-breakers_R5036323-3
- Excerpt: Senior Manager - Quality Engineering and Continuous Improvement – Dead tank Circuit-breakers 2 Locations posted: Posted 11 Days Ago

### Digital Electronics Circuit & Unit Hardware Design Engineer (Lead or Senior) - The Boeing Company
- Location: USA - El Segundo, CA (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://boeing.wd1.myworkdayjobs.com/External_Careers/job/USA---El-Segundo-CA/Digital-Electronics-Circuit---Unit-Hardware-Design-Engineer--Lead-or-Senior-_JR2025487688
- Excerpt: Digital Electronics Circuit & Unit Hardware Design Engineer (Lead or Senior) USA - El Segundo, CA posted: Posted 2 Days Ago

### Ingénieur(e) concepteur(trice) électrique - Disjoncteur / Electrical design engineer - Circuit breaker - GE Vernova
- Location: La Prairie (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 10 weeks (not source-backed)
- Non-birth-parent leave: 10 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://gevernova.wd5.myworkdayjobs.com/Vernova_ExternalSite/job/La-Prairie/Ingnieur-e--concepteur-trice--lectrique---Disjoncteur---Electrical-design-engineer---Circuit-breaker_R5038468-2
- Excerpt: Ingénieur(e) concepteur(trice) électrique - Disjoncteur / Electrical design engineer - Circuit breaker La Prairie posted: Posted 30+ Days Ago

### Digital Electronics Circuit & Unit Hardware Design Engineer (Associate or Mid-Level) - The Boeing Company
- Location: USA - El Segundo, CA (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://boeing.wd1.myworkdayjobs.com/External_Careers/job/USA---El-Segundo-CA/Digital-Electronics-Circuit---Unit-Hardware-Design-Engineer--Associate-or-Mid-Level-_JR2025487163
- Excerpt: Digital Electronics Circuit & Unit Hardware Design Engineer (Associate or Mid-Level) USA - El Segundo, CA posted: Posted 2 Days Ago

### Monolithic Microwave Integrated Circuit (MMIC) Manufacturing Engineer (Associate or Mid-Level) - The Boeing Company
- Location: USA - El Segundo, CA (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://boeing.wd1.myworkdayjobs.com/External_Careers/job/USA---El-Segundo-CA/Monolithic-Microwave-Integrated-Circuit--MMIC--Manufacturing-Engineer--Associate-or-Mid-Level-_JR2026504579-1
- Excerpt: Monolithic Microwave Integrated Circuit (MMIC) Manufacturing Engineer (Associate or Mid-Level) USA - El Segundo, CA posted: Posted 2 Days Ago

### Design Engineer (PCB & Circuit) - Carrier Global
- Location: 144/9 Moo 5, Bangkadi Industrial Park, Tivanon Road, Bangkadi, Muang, Pathumthani 12000 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/1449-Moo-5-Bangkadi-Industrial-Park-Tivanon-Road-Bangkadi-Muang-Pathumthani-12000/Design-Engineer--PCB-_30207502-1
- Excerpt: Design Engineer (PCB & Circuit) 144/9 Moo 5, Bangkadi Industrial Park, Tivanon Road, Bangkadi, Muang, Pathumthani 12000 posted: Posted Today

### Senior Integrated Circuit Digital Design Engineer - Raytheon Technologies
- Location: US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-GOLETA-B01--6825-Cortona-Dr--BLDG-B01/Senior-Integrated-Circuit-Digital-Design-Engineer_01832473
- Excerpt: Senior Integrated Circuit Digital Design Engineer US-CA-GOLETA-B01 ~ 6825 Cortona Dr ~ BLDG B01 posted: Posted 30+ Days Ago

### Senior Design Engineer (PCB & Circuit) - Carrier Global
- Location: 144/9 Moo 5, Bangkadi Industrial Park, Tivanon Road, Bangkadi, Muang, Pathumthani 12000 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/1449-Moo-5-Bangkadi-Industrial-Park-Tivanon-Road-Bangkadi-Muang-Pathumthani-12000/Senior-Design-Engineer--PCB---Circuit-_30207587-1
- Excerpt: Senior Design Engineer (PCB & Circuit) 144/9 Moo 5, Bangkadi Industrial Park, Tivanon Road, Bangkadi, Muang, Pathumthani 12000 posted: Posted Today

### Senior Photonics Integrated Circuit Design Engineer - Raytheon Technologies
- Location: US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-SAN-DIEGO-15110--15110-Ave-of-Science--SCIENCE-Ste-200/Senior-Photonics-Integrated-Circuit-Design-Engineer_01834081
- Excerpt: Senior Photonics Integrated Circuit Design Engineer US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 posted: Posted 30+ Days Ago

### Senior Photonics Integrated Circuit Test Engineer - Raytheon Technologies
- Location: US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-SAN-DIEGO-15110--15110-Ave-of-Science--SCIENCE-Ste-200/Senior-Photonics-Integrated-Circuit-Test-Engineer_01834086
- Excerpt: Senior Photonics Integrated Circuit Test Engineer US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 posted: Posted 30+ Days Ago

### Principal Photonics Integrated Circuit Design Engineer - Raytheon Technologies
- Location: US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-SAN-DIEGO-15110--15110-Ave-of-Science--SCIENCE-Ste-200/Principal-Photonics-Integrated-Circuit-Design-Engineer_01834083
- Excerpt: Principal Photonics Integrated Circuit Design Engineer US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 posted: Posted 30+ Days Ago

### Principal Photonics Integrated Circuit Test Engineer - Raytheon Technologies
- Location: US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://globalhr.wd5.myworkdayjobs.com/REC_RTX_Ext_Gateway/job/US-CA-SAN-DIEGO-15110--15110-Ave-of-Science--SCIENCE-Ste-200/Principal-Photonics-Integrated-Circuit-Test-Engineer_01834091
- Excerpt: Principal Photonics Integrated Circuit Test Engineer US-CA-SAN DIEGO-15110 ~ 15110 Ave of Science ~ SCIENCE, Ste 200 posted: Posted 30+ Days Ago

### Electrical + Instrument Technician - Bunge
- Location: Council Bluffs, IA (unspecified)
- Salary: $34K-$34K
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://jobs.bunge.com/job/Council-Bluffs-Electrical-%2B-Instrument-Technician-IA-51503-6593/1292926601/
- Excerpt: Electrical + Instrument Technician Council Bluffs, IA Requisition Number: 43812 A Day in the Life: The Electrical & Instrumentation Technician is responsible for maintaining plant wide electrical troubleshooting and repair. Position Details: Monday through Friday day shift Pay: $34.67 an hour What You'll Be Doing: Maintain all automation throughout the facility (electric circuits of 480VAC or less) Troubleshoot and repair high voltage lighting, variable frequency drive (VFD) and alternating current / direct current (AC/DC) systems Troubleshoot and repair Programmable Logix Control (PLC) (Allen-Bradley) systems like SLC 500, MicroLogix, CompactLogix, PLC 5s, 5000 Logix Controllers and Panel Views Check output on DC controllers and replace printed circuit boards when needed Troubleshoot, locate, test, identify, or diagnose electrical malfunction and then adjust, repair, or replace Follow, interpret, and read blueprints or schematics Calibrate and/or troubleshoot process instrumentation Assigning IP addresses to new equipment Inspect for conformity to industry standards or specifications Rebuild, repair, and replace damaged, defective, or worn parts Maintain a clean and orderly work area and remove material and equipment from job site Troubleshoot and repair AC motor starter circuits Minimum Qualifications: Associates degree in electronics or 3-5 years of equivalent experience is required Ability to read and understand ladder logic Experience with networking systems such as Control Net, Ethernet, and Data Highway Familiarity with m

### Hardware Systems Integration Engineer, Pixel Phones - Google
- Location: New Taipei, Banqiao District, New Taipei City, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQhvNNOlMVxoaq0ehVx6Tusl2afrXba_z1ZYS-rpGflYEjsACxwdTGNxTjEbOw44UlBOd4GdUsvoNQB5-RiLsdb9qnWqd6E5mW-M93VgMMeUV--vYxG5BBpHCKmf-Q%3D%3D_V2&loc=TW&title=Hardware+Systems+Integration+Engineer
- Excerpt: Hardware Systems Integration Engineer, Pixel Phones New Taipei, Banqiao District, New Taipei City, Taiwan Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Android is Google's mobile operating system powering more than 3 billion devices worldwide. Android is about bringing computing to everyone in the world. We believe computing is a super power for good, enabling access to information, economic opportunity, productivity, connectivity between friends and family and more. We think everyone in the world should have access to the best computing has to offer. We provide the platform for original equipment manufacturers (OEMs) and developers to build compelling computing devices (smartphones, tablets, TVs, wearables, etc) that run the best apps/services for everyone in the world. Design, develop, and review phone hardware systems and sub-components from concept to mass production. Perform detailed direct testing/validation to bring the design to mass production. Participate in all stages of next generation consumer product development. Maintain design rules, work with layout engineers to optimize Printed Circuit Board (PCB) design, including circuits and layout design for high speed signal Flexible Printed Circuit (FPC) and connector, product validation and supporting production test, and buildup design and test capability including design guideline and lab. Work with Engineering/Qualification teams on system bring-up and design validation. Minimum qualifications: Bachelor's degree in

### Supplier Quality Engineer, Optical Circuit Switch, Google Cloud - Google
- Location: Thailand (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdTh0p4jMW8dIAxagLnwCpNLdK6A9KSqn-jMYI9cl7ZQEjsACxwdTMZSJ2pCpnG3XMGZ04L7Jm_vNnQCLr2daAN3crAnhZ-FNvHntlCxntqmgYslTeQqBikoc-9USw%3D%3D_V2&loc=US&title=Supplier+Quality+Engineer
- Excerpt: Supplier Quality Engineer, Optical Circuit Switch, Google Cloud Thailand Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Manage the supplier quality and reliability for optical circuit switch (OCS) components, from new product introduction (NPI) through end-of-life. Lead cross-functional initiatives to ensure the OCS supply chain's technical and operational readiness for mass production. Drive supplier selection and qualification by conducting on-site audits and serve as the subject matter expert to influence product roadmaps. Resolve critical fleet and factory issues by leading suppliers through root cause and corrective action (RCCA) and failure analysis (FA) processes.

### Integrated Circuit Package Design Engineer - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $163K-$237K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUdr8lbp84BgUNuk_CUbeuIP5Ba5NzyLe707vBdltyD2EjsACxwdTEFVBD5W2gDbHF3RBCinEX3Kp20aRIkPgE2kFxzhJrJMzgi4To1-HvMUJmTpxCzrWeM2oLIRxw%3D%3D_V2&loc=US&title=Integrated+Circuit+Package+Design+Engineer
- Excerpt: Integrated Circuit Package Design Engineer Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Package Designer, you will develop package substrate designs of advanced (2.5D/3.5D) packaging technologies for Machine Learning (ML) chips. This involves collaborating with SI/PI, thermal/mechanical, assembly, and PCB engineers to create complex, high-performance substrate designs. You will manage all phases of the design process, including routing feasibility, test vehicle creation, product designs, conducting design reviews, artwork export, DFM process and generating final documentation. Additionally, you will be instrumental in identifying and incorporating advanced chip packaging technologies into the Google chip product design pipeline. This contributes to successful chip deployment in data centers, ensuring the best optimized power, performance, area (PPA) designs and enhancing system performance relative to total cost of ownership (TCO ). Our team is responsible for designing and building the custom hardware, software, and networking technologies that power all of Google's services, as standard off-the-shelf hardware cannot meet our unique computational needs. You will be developing and building the systems that form the core of the world's largest and most powerful computing infrastructure. Your work will span from the fundamental levels of circuit design up to system design, seeing systems through to high-volume manufacturing, which directly influences the machinery in our

### Photonics Research - Connectivity for Integrated Optical Circuits (m/f/d) - Corning
- Location: Berlin (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://corningjobs.corning.com/job/Berlin-Photonics-Research-Connectivity-for-Integrated-Optical-Circuits-%28mfd%29-12489/1389041900/
- Excerpt: Photonics Research - Connectivity for Integrated Optical Circuits (m/f/d) Berlin Requisition Number: 74930 The company built on breakthroughs. ​ Join us.​ Corning is one of the world's leading innovators in glass, ceramic, and materials science. From the depths of the ocean to the farthest reaches of space, our technologies push the boundaries of what's possible. ​ How do we do this? With our people. They break through limitations and expectations - not once in a career, but every day. They help move our company, and the world, forward. ​ ​At Corning, there are endless possibilities for making an impact. You can help connect the unconnected, drive the future of automobiles, transform at-home entertainment, and ensure the delivery of lifesaving medicines. And so much more.​ ​Come break through with us. Our Optical Communications segment has recently evolved from being a manufacturer of optical fiber and cable, hardware and equipment to being a comprehensive provider of industry-leading optical solutions across the broader communications industry.This segment is classified into two main product groupings - carrier network and enterprise network. The carrier network product group consists primarily of products and solutions for optical-based communications infrastructure for services such as video, data and voice communications. The enterprise network product group consists primarily of optical-based communication networks sold to businesses, governments and individuals for their own use. For our location in Berlin, Germany, we are looking for a Photonics Re

### Photonics Research Engineer - Connectivity for Integrated Optical Circuits - Corning
- Location: Corning, NY (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://corningjobs.corning.com/job/Corning-Photonics-Research-Engineer-Connectivity-for-Integrated-Optical-Circuits-NY-14831/1390480300/
- Excerpt: Photonics Research Engineer - Connectivity for Integrated Optical Circuits Corning, NY Requisition Number: 74928 The company built on breakthroughs. ​ Join us.​ Corning is one of the world's leading innovators in glass, ceramic, and materials science. From the depths of the ocean to the farthest reaches of space, our technologies push the boundaries of what's possible. ​ How do we do this? With our people. They break through limitations and expectations - not once in a career, but every day. They help move our company, and the world, forward. ​ ​At Corning, there are endless possibilities for making an impact. You can help connect the unconnected, drive the future of automobiles, transform at-home entertainment, and ensure the delivery of lifesaving medicines. And so much more.​ Come break through with us. Corning's businesses are ever-evolving to best serve our customers, industries, and consumers. Today, we accelerate and transform life sciences, mobile consumer electronics, optical communications, display, automotive, and solar markets. We are changing the world with: Trusted products that accelerate drug discovery, development, and delivery to save lives Damage-resistant cover glass to enhance the devices that keep us connected Optical fiber, wireless technologies, and connectivity solutions to carry information and ideas at the speed of light Precision glass for advanced displays to deliver richer experiences Auto glass and ceramics to drive cleaner, safer, and smarter transportation Solar polysilicon, wafers, and innovative photovoltaic modules, enabling

### Senior ASIC Power Delivery Engineer - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $163K-$237K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWbdDKru71qVx64mSCpNOtjnGIM9Nj1Punl2doCtcY0pEjsACxwdTLwTCceJfJ3WQKmohBUmiDg79urbaBrqTNYk3Y4hE313MNtI0Ysj21dAZnBp7WMHu-6bv-ryWA%3D%3D_V2&loc=US&title=Senior+ASIC+Power+Delivery+Engineer
- Excerpt: Senior ASIC Power Delivery Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will collaborate with physical design, circuits, technology, and package leads to overcome the slowing of Moore's law in advanced technology nodes and deliver application-specific integrated circuits and systems on a chip. You will drive reliable products by optimizing, analyzing, customizing, and verifying our power delivery network to meet performance and integrity specifications. You will perform technical evaluations of process nodes, metal stacks, electronic design automation tools, and intellectual properties, and provide recommendations. You will develop power delivery and reliability solutions and methodologies that co-optimize across the entire design space, then see these through from inception to maturity and tapeout. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking

### Early Talent Programs - Fortinet
- Location: Location not specified (hybrid)
- Salary: Not disclosed
- Posted: 2026-06-04
- Parental leave: 2 weeks (not source-backed)
- Non-birth-parent leave: 2 weeks (not source-backed)
- Apply: https://www.fortinet.com/corporate/careers/early-talent-program
- Excerpt: Early Talent Programs Read more about the Early Talent Program at Fortinet Skip to content Skip to navigation Skip to footer FREE PRODUCT DEMO SERVICES SUPPORT DOWNLOADS FORTICLOUD LOGIN username Search USA (English) UK & Ireland (English) Germany (Deutsch) France (Français) Italy (Italiano) Mainland China (简体中文) Taiwan (繁體中文) Korea (한국어) Japan (日本語) Brazil (Portugués) Latin America (Español) Products The Fortinet Platform Hybrid Mesh Firewall Next-Generation Firewalls AI-Powered Security Services More Enterprise Networking Secure Ethernet Switches Secure Wireless LAN More AI Security FortiAI Overview Generative AI and AIOPs Operating System FortiOS Unified SASE SASE Secure SD-WAN More Cloud Security Cloud NGFW CNAPP More Security Operations SOC Platform Unified Endpoint Platform More Operational Technology Modernized OT Security Ruggedized Products More Learn more about GenAI Security » Network Security Network Firewall Firewall Appliances Cloud Firewalls Services AI-Powered Security Services FortiGate-as-a-Service Quantum Security Overview Quantum Safety Operating System FortiOS NOC Management Centralized Management GenAI for NOC Firewall Migration Service Latest from Fortinet Fortinet Named a Leader in the 2025 Gartner® Magic Quadrant™ for Hybrid Mesh Firewall Get the Report Learn more about Secure Networking » Enterprise Networking LAN Switching Chassis Switching WLAN High-Density NAC NOC Management Cloud-based LAN Management Centralized Management AIOps GenAI for NOC Operating System FortiOS WAN Secure SD-WAN 5G/LTE Wireless WAN Latest from Fortinet Fortinet Named a Leader in the 2025 Gartner® Magic Quadrant™ for Enterprise Wired and Wireless LAN Infrastructure Get the Report Learn more about Secure Networking » Unified SASE SASE SASE Secure SD-WAN Universal ZTNA FortiSASE Sovereign Services

### Request a Quote - Fortinet
- Location: Location not specified (hybrid)
- Salary: Not disclosed
- Posted: 2026-06-04
- Parental leave: 2 weeks (not source-backed)
- Non-birth-parent leave: 2 weeks (not source-backed)
- Apply: https://www.fortinet.com/corporate/about-us/request-a-quote
- Excerpt: Request a Quote Request a Quote | Fortinet Skip to content Skip to navigation Skip to footer FREE PRODUCT DEMO SERVICES SUPPORT DOWNLOADS FORTICLOUD LOGIN username Search USA (English) UK & Ireland (English) Germany (Deutsch) France (Français) Italy (Italiano) Mainland China (简体中文) Taiwan (繁體中文) Korea (한국어) Japan (日本語) Brazil (Portugués) Latin America (Español) Products The Fortinet Platform Hybrid Mesh Firewall Next-Generation Firewalls AI-Powered Security Services More Enterprise Networking Secure Ethernet Switches Secure Wireless LAN More AI Security FortiAI Overview Generative AI and AIOPs Operating System FortiOS Unified SASE SASE Secure SD-WAN More Cloud Security Cloud NGFW CNAPP More Security Operations SOC Platform Unified Endpoint Platform More Operational Technology Modernized OT Security Ruggedized Products More Learn more about GenAI Security » Network Security Network Firewall Firewall Appliances Cloud Firewalls Services AI-Powered Security Services FortiGate-as-a-Service Quantum Security Overview Quantum Safety Operating System FortiOS NOC Management Centralized Management GenAI for NOC Firewall Migration Service Latest from Fortinet Fortinet Named a Leader in the 2025 Gartner® Magic Quadrant™ for Hybrid Mesh Firewall Get the Report Learn more about Secure Networking » Enterprise Networking LAN Switching Chassis Switching WLAN High-Density NAC NOC Management Cloud-based LAN Management Centralized Management AIOps GenAI for NOC Operating System FortiOS WAN Secure SD-WAN 5G/LTE Wireless WAN Latest from Fortinet Fortinet Named a Leader in the 2025 Gartner® Magic Quadrant™ for Enterprise Wired and Wireless LAN Infrastructure Get the Report Learn more about Secure Networking » Unified SASE SASE SASE Secure SD-WAN Universal ZTNA FortiSASE Sovereign Services AI-Powered Security Services Operating

### Technical Lead, Custom Digital Circuit Design, Mixed Signal - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $240K-$334K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcF-45uccTWmzaQzOydjG4wSLkyWJ3Z4EsGPZUEWfULOEjsACxwdTIOpl4gqR2UJXogvRFPqujzt16yyvoUIINZK9Jwwap35QVvZslazpQPUPfiUOQHsFAilelQfhw%3D%3D_V2&loc=US&title=Technical+Lead
- Excerpt: Technical Lead, Custom Digital Circuit Design, Mixed Signal Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As the Lead Architect for Google's custom back-end solutions for high-speed internal connections, you will set the design standards for our custom silicon. You will ensure our physical design methods can support data speeds of 1.6T and above while maintaining high manufacturing reliability and performance. You will create the design framework for our future hardware, solving complex engineering challenges in the latest manufacturing processes. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving channel behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping

### Field Application Engineer Intern (Teradyne, Pathum Thani, Thailand) - Teradyne
- Location: Field Application Engineer Intern (Teradyne, Pathum Thani, Thailand) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/Khlong-Luang-Field-Application-Engineer-Intern-%28Teradyne%2C-Pathum-Thani%2C-Thailand%29-13/1378117000/
- Excerpt: Field Application Engineer Intern (Teradyne, Pathum Thani, Thailand) Field Application Engineer Intern (Teradyne, Pathum Thani, Thailand) Work Location: Pathum Thani, Thailand Project: Spare Parts Management / AI Tester Monitoring System O ur Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview The intern will design and develop an online inventory system for spare part tracking across multiple sites (e.g., Thailand, Philippines, Taiwan, Korea), as well as implement AI-based tester monitoring (e.g., status, failures, yield) using historical data. The intern will also participate in designing software diagnostics to test electronic circuits and the functionality of modules within the tester. Key Responsibilities Manage Inventory data for multiple sites on SharePoint Design Excel sheet formats Set up online storage/location on SharePoint Develop real-time reports or dashboard views Develop AI monitoring tools Develop a local AI model (offline) for leaning tester data from databases Analysis data and develop a chatbot for users Perform basic failure prediction Co-develop diagnostic tools to verify electronic circuits and functionality S

### Chip Packaging Architect - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWV9dyAd9yhuFwAej9o2r08trSjJAPtWPt8lbN_UbRkcEjsACxwdTDxw62pjCv5VQdh1jev470hJGTlY2mNy28Ezald7RnD1WGgbzhxs12ULPzRi9WZ4H8xobpKuBw%3D%3D_V2&loc=US&title=Chip+Packaging+Architect
- Excerpt: Chip Packaging Architect Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Chip Packaging Architect on our Silicon Integration team, you will drive advanced packaging solutions (2.5D/3D/3.5D) and technologies for Machine Learning (ML) chips and custom Application-Specific Integrated Circuits (ASICs). You will collaborate with product architects, design teams, and Signal Integrity/Power Integrity (SI/PI), thermal, mechanical, assembly, and Printed Circuit Board (PCB) engineers to create high-performance packages. Your focus will span optical packaging technologies, design tradeoffs, assembly evaluation, mechanical reliability, and qualification, seeing systems through to high-volume manufacturing. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Own product and packaging architecture for next-generation optical modules (e.g., CPO, uLED, VCSEL) and define manufacturing strategies for Tensor Processing Unit (TPU) packaging solutions. Bridge hardware domains from silicon architects to platform teams, managing technical trade-offs across manufacturing, electrical, thermal, and mechanical parameters. Drive advanced packaging concepts to high-volume manufacturing, proactively mitigating technical risks and authoring assembly processes and reliability test plans. Lead cross-functional initiatives guiding new designs and test vehicles through qualification and New Product Introduction (NPI) phases. Develop and scale the

### Field Engagements Manager-South - Boston Scientific
- Location: Bangalore (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.bostonscientific.com/job/Bangalore-Field-Engagements-Manager-South/1386465200/
- Excerpt: Field Engagements Manager-South Bangalore Diversity - Innovation - Caring - Global Collaboration - Winning Spirit - High Performance At Boston Scientific, we'll give you the opportunity to harness all that's within you by working in teams of diverse and high-performing employees, tackling some of the most important health industry challenges. With access to the latest tools, information and training, we'll help you in advancing your skills and career. Here, you'll be supported in progressing - whatever your ambitions. Role: Field Engagements Manager-South (IC) Location: Bangalore Reporting to: Regional Sales Manager Own up the field engagements strategy for assigned region/Country: a. Increase in the proportion of training-oriented engagements: ROVUS workshops, IVUS masterclass, case support proctorships etc b. Fous on increasing the quantum of engagements (for the right engagements, we will find the budgets) c. HPLS focus, hold the RMs accountable for activities and projected business d. Own up the marketing budget utilization for the region, optimize spends to ensure strategic engagements Draft a quarterly engagement plan for 5 customers for each TM, this plan needs to be co-owned by RM & the RSM (plan basis the above mentioned) a. Plan to be finalized 15 days prior to the start of the quarter, and track monthly b. Be the SPOC for nominating HCPs for central events,nominations of HCPs basis skill sets and engagement plans. Track progress through Dashboards: a. Share a monthly dashboard, one each for West and for So

### Software Engineer, Crypta, Cloud Infrastructure - Google
- Location: Kirkland, WA, USA (unspecified)
- Salary: $147K-$211K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaKdXdZKqyMiapeQFhFD6QL0VqvbzDv3GYHsSuVy14myEjsACxwdTL8PqbpUCBZ2Ik6nU1g8WyifbU3bAYL-DkO0V72c2fZqrdp88DkzqFHHvIVsrKheersHCEw8BA%3D%3D_V2&loc=US&title=Software+Engineer
- Excerpt: Software Engineer, Crypta, Cloud Infrastructure Kirkland, WA, USA Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. In this role, you will secure Google's production hardware by anchoring Google's silicon security stance in trustworthy hardware, developing, deploying, and managing foundational Root-of-Trust (RoT) identity services, RoT firmware, and firmware signing infrastructure to ensure hardware boots securely and to guard against severe low-level vulnerabilities at scale. As a part of this role, your primary focus areas will include RoT identity provisioning and attestation, continuous alignment with industry standards (e.g., Caliptra, OpenTitan, TCG), and the strategic migration of services and hardware toward post-quantum cryptography (PQC).Google Cloud accelerates every organization's ability to digitally transform its business and industry. We deliver enterprise-grade solutions that leverage Google's

### Working Student (f/m/d) - Industry-University Collaboration @ SAP Labs Germany - SAP
- Location: Working Student (f/m/d) - Industry-University Collaboration @ SAP Labs Germany | Region Europe | Country Germany | Internal Posting Location Garching (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Garching-bei-M%C3%BCnchen-Working-Student-%28fmd%29-Industry-University-Collaboration-%40-SAP-Labs-Germany-85748/1397643933/
- Excerpt: Working Student (f/m/d) - Industry-University Collaboration @ SAP Labs Germany Working Student (f/m/d) - Industry-University Collaboration @ SAP Labs Germany | Region Europe | Country Germany | Internal Posting Location Garching We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. What you´ll build At SAP Labs Germany, we run applied research projects with the Technical University of Munich, where cutting-edge technologies (AI agents, robotics, quantum computing) are developed and tested against real business challenges to shape the next generation of software innovation. As a working student, you are part of the team that makes this collaboration possible. In this role, you will work across project support, stakeholder management, event coordination, and content creation-always connected to research that ultimately becomes part of products used by businesses around the world. You support the coordination of ongoing research projects, track their status, prepare updates for joint steering meetings, and ensure that the right people are kept informed. You help prepare and run events together with researchers from universities and SAP.

### Assembler(GCS-CS, Philippines:Cebu) - Teradyne
- Location: Assembler(GCS-CS, Philippines:Cebu) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/Basak%2C-Lapu-Lapu-City-Assembler%28GCS-CS%2C-PhilippinesCebu%29/1390914300/
- Excerpt: Assembler(GCS-CS, Philippines:Cebu) Assembler(GCS-CS, Philippines:Cebu) Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Duties of an Assembler are as follows: Directly reports to the Rework Supervisor. Ensures circuit boards are applied with the specified rework soldering job types. Ensures the use of proper tools and equipment in the execution of rework processes. Interprets rework soldering Engineering Change Order through related databases. Collaborated with the team in the conduct of the various rework and soldering processes. Meet with the groups and personal operational goals and deliverables. Conducts in-process, incoming or outgoing inspection. All About You We seek individuals who share our passion and determination. Our commitment to customer success drives us to go the extra mile. If you're ready to join us in this mission, take a closer look at the minimum criteria for the position. Candidate must possess at least a vocational Diploma in Electronics, BS in Industrial Technology Major in Electronics, or any related course. Having extensive soldering

### Power Architect, Platforms Engineering - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $236K-$330K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQKyBl07yTas1HrOoSuhxQm4sQjMTRdWdLMMIh5LW4ApEjsACxwdTOAqPMkSedJHpwJfsCGsh_id_H8zdzGvPVWnC-mKjZSI9xw1_clqE42qLP1J3NGNdIWg8J9Rfg%3D%3D_V2&loc=US&title=Power+Architect
- Excerpt: Power Architect, Platforms Engineering Sunnyvale, CA, USA Our computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Our Platforms Team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users. As a key member of the team, you will manage projects in multiple areas with your expertise. You will also monitor the performance of vendors working on projects and evaluate new technologies. As a Power Engineer in Technical Infrastructure, you will play a key role in the development of one of the world's fastest growing computing infrastructures. You will work as part of a team to deliver innovative power solutions for point of load application. Your objective will be to design, analyze, optimize and implement board, chip level power topologies and control for large scale point of load applications including ASICs, FPGAs and processors. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity.

### Plant Electrician - Bunge
- Location: Destrehan, LA (unspecified)
- Salary: $31K-$31K
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://jobs.bunge.com/job/Destrehan-Plant-Electrician-LA-70047-5304/1382800233/
- Excerpt: Plant Electrician Destrehan, LA Requisition Number: 44822 A Day in the Life: The Plant Electrician is responsible for the electrical maintenance of the Destrehan, LA soybean processing facility. Candidate must actively participate in Bunge's employee safety policy and maintain a safe work environment for self and all employees. Additionally, this role is responsible for demonstrating a commitment to supply safe food, maintain a food safety culture within the site, continually improve the site's food safety management system, and comply with customer and regulatory requirements. Position Details: Night shift (6:00pm - 6:00am) on a 2/2/3 schedule Overtime, call out availability, on-call rotation, and/or straight days are required Pay: $31.00 an hour Bunge offers a variety of benefits including health and wellness plans, retirement contribution and paid vacation/holidays. What You'll Be Doing: Responsible for plant wide electrical troubleshooting and repair (electrical circuits of 480VAC or less) Perform general electrician skills including but not limited to running conduit and sizing and pulling wires Follow, interpret, and read blueprints and schematics Inspect for conformity to industry standards or specifications Troubleshoot and repair variable frequency drive (VFD) and AC/DC systems Troubleshoot and repair electrical components of mechanical, hydraulic, and pneumatic industrial equipment Maintain electrical switchgear Lay out and install conduit Working knowledge of thermography Other duties as assigned

### Power Engineer - Corning
- Location: Taichung (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://corningjobs.corning.com/job/Taichung-Power-Engineer-407/1379067600/
- Excerpt: Power Engineer Taichung Role Purpose Support the Power Engineering Manager to implement power system strategy, manage electrical power related project portfolio, own core electrical and power capabilities and technologies in core process areas by Supporting development and execution of plants to evaluate both new electrical system design and continuous improvements in the existing electrical system in terms of higher reliability and higher stability Support capital expansion projects in terms of electrical and power systems Troubleshooting electrical power engineering problems Key Responsibilities Scoping and execution of power engineering projects to plants in Taiwan, both for new construction and existing facilities Specify, review, analyze, and/or commission electrical systems and equipment and oversee equipment installation, commissioning and/or decommissioning Perform and/or review power system studies, load flow/short circuit analysis and relay coordination studies for facility-utility interconnection and internal power distribution systems Conduct failure analysis of power system equipment Work in collaboration with Project Managers, equipment suppliers, facility managers, and other project partners Experiences/Education - Required Bachelor's or master's Degree in power and/or electrical engineering preferred Fundamental understanding of industrial electrical systems, electrical power substation, grounding and lightning protection system Electrical system review and analysis, including: Under

### Network Operations Analyst I - Accendra Health INC
- Location: 3610 Accendra India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 3 weeks (not source-backed)
- Non-birth-parent leave: 3 weeks (not source-backed)
- Apply: https://owensminor.wd1.myworkdayjobs.com/OMCareers/job/3610-Accendra-India/Network-Operations-Analyst-I_REQ_24_22746
- Excerpt: Network Operations Analyst I 3610 Accendra India At Owens & Minor, we are a critical part of the healthcare process. As a Fortune 500 company with 350+ facilities across the US and 22,000 teammates in over 90 countries, we provide integrated technologies, products and services across the full continuum of care. Customers-and their patients-are at the heart of what we do. Our mission is to empower our customers to advance healthcare, and our success starts with our teammates. POSITION SUMMARY Owens & Minor is looking for a NOC Analyst I to join the NOC team responsible for monitoring and maintaining over 2000 servers and 3000 network devices, Database and backup located in Owens & Minor locations globally. The NOC Analyst is part of a collective team of engineers which troubleshoot and resolve routine and complex network, server, database and OS issues and alerts in a timely and efficient manner while maintaining target system uptimes. ESSENTIAL JOB FUNCTIONS: Monitor production and non-production systems located at Owens & Minor offices, data centers, distribution centers, and warehouses. Respond to alerts and event-generated incident tickets effectively and efficiently. Create and use Knowledge Base Articles to investigate, diagnose, and resolve incidents. Escalate complex incidents to Networking, Server, and other resources in accordance with established processes and procedures. Review and update status of incidents in ticketing system. Create trouble tickets with carriers for circuit issues. Interface with internal IT groups and business units as needed to achieve incident or problem resolution. Support the Major Incident Management

### Senior Manufacturing Engineer, PCB, Advanced Manufacturing Engineering - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $144K-$209K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYKCnbagouISa1LejLdvqA7IV6zuUDQ2YGC2vulY_JU5EjsACxwdTHkmgAb06dYYRJYLCAJ-Ck4l7Lyyq0tsM_iKKdvADnSfC4e8KwuRn9PAUkZ0F3NxatnTiq_aFw%3D%3D_V2&loc=US&title=Senior+Manufacturing+Engineer
- Excerpt: Senior Manufacturing Engineer, PCB, Advanced Manufacturing Engineering Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As an Advanced Staff Manufacturing Engineer for the New Technology Introduction process, you will be an integral part of the Cloud Supply Chain Operations team. You will be responsible for releasing Google's hardware to mass production and developing a supply chain to deliver it. The core responsibility begins with leading the development and scale of new Printed Circuit Board (PCB) manufacturing and materials technologies to enable the growing roadmap of Google Cloud data center products. You will be the technical expert for advanced PCB manufacturing processes and provide technical leadership for the delivery of approaches and processes for our product development efforts. In this role, you will work cross-functionally to influence technology direction and adoption for our data center products. You will also ensure that our supply chain stack is fully readied to execute novel manufacturing and test approaches in production environments. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations,

### Staff Design Engineer, Networking, Google Cloud - Google
- Location: Haifa, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka-LgNei6dnT140Q1HJUCndLZ-bb6w5RBcNUZXQN8CP1EjsACxwdTOjxTG8TGxNj2IqN_6Wd9rekXhA2AE7ZV6nAhn95CKkUV4akMZuga9t1Gd4xS8QAxrU742VcgQ%3D%3D_V2&loc=IL&title=Staff+Design+Engineer
- Excerpt: Staff Design Engineer, Networking, Google Cloud Haifa, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing application-specific integrated circuits (ASICs) used to accelerate networking in data centers. You will have multiple responsibilities in areas such as project definition, design, and implementation. You will participate in the design, architecture, documentation, and implementation of the next generation of data center accelerators.You will also be responsible for performance analysis for a networking stack using your knowledge. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Lead an ASIC subsystem. Understand how it interacts with software and other ASIC subsystems to implement data center networks. Define hardware/software

### Electromechanical Engineer- Signal Delivery (Computer Test Division; North Reading, MA) - Teradyne
- Location: North Reading, MA (unspecified)
- Salary: $141K-$226K
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-Electromechanical-Engineer-Signal-Delivery-%28Computer-Test-Division-North-Reading%2C-MA%29-MA/1353202500/
- Excerpt: Electromechanical Engineer- Signal Delivery (Computer Test Division; North Reading, MA) North Reading, MA Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview We are seeking a Electromechanical Engineer to join our Compute Test instrumentation team focused on high-speed digital and RF signal delivery solutions for semiconductor test systems and related technologies in North Reading, MA. In this role you will be responsible for designing and releasing Signal Delivery solutions consisting of complex coax cable assemblies, PCBs and interposers. You will integrate across all development functions (Electrical, Mechanical, Systems engineer, Circuit design, Signal Integrity, Project management, etc.) to successfully bring up the new signal delivery product. You will: Design and analyze high-speed digital and RF signal delivery systems-including custom connectors, cables, PC boards, and interposers-supporting industry-standard interfaces (PCIe, UCIe, etc.) from MHz frequencies up to 224 Gbps Support product development from concept through production, ensuring signal integrity and reliability. Provide clea

### Principal/Lead Hardware Engineer (Teradyne, North Reading, MA) - Teradyne
- Location: North Reading Principallead Hardware Engineer Teradyne North Reading, MA (unspecified)
- Salary: $141K-$226K
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-PrincipalLead-Hardware-Engineer-%28Teradyne%2C-North-Reading%2C-MA%29-MA/1390863200/
- Excerpt: Principal/Lead Hardware Engineer (Teradyne, North Reading, MA) North Reading Principallead Hardware Engineer Teradyne North Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview We are seeking a highly skilled and experienced Principal Lead Hardware Engineer to join our dynamic and fast-paced team. The ideal candidate will have a deep understanding of both digital and analog circuit d

### Supply Line Engineer (TERADYNE, North Reading, MA) - Teradyne
- Location: North Reading, MA (unspecified)
- Salary: $125K-$200K
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-Supply-Line-Engineer-%28TERADYNE%2C-North-Reading%2C-MA%29-MA/1376112400/
- Excerpt: Supply Line Engineer (TERADYNE, North Reading, MA) North Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne's Supply Base Management (SBM) group is hiring a Supply Line Engineer to support New Product Introduction (NPI) teams focused on printed circuit boards (PCBs) used in advanced test and measurement sys

### Senior Analog Design Engineer (Teradyne, Augora Hills, CA) - Teradyne
- Location: Agoura Hills, CA (unspecified)
- Salary: $123K-$194K
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/Agoura-Hills-Senior-Analog-Design-Engineer-%28Teradyne%2C-Augora-Hills%2C-CA%29-CA-91301/1379731500/
- Excerpt: Senior Analog Design Engineer (Teradyne, Augora Hills, CA) Agoura Hills, CA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE , where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Teradyne's Semiconductor Test Division in Agoura Hills, CA is looking for an enthusiastic candidate for the position of Senior Analog Design Engineer, to design low high-speed circuits in mixed-signal ICs for

### Associate Systems Support Engineer - Accendra Health INC
- Location: 3610 Accendra India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 3 weeks (not source-backed)
- Non-birth-parent leave: 3 weeks (not source-backed)
- Apply: https://owensminor.wd1.myworkdayjobs.com/OMCareers/job/3610-Accendra-India/Associate-Systems-Support-Engineer_REQ_24_21952-1
- Excerpt: Associate Systems Support Engineer 3610 Accendra India At Owens & Minor, we are a critical part of the healthcare process. As a Fortune 500 company with 50+ facilities across the US and 18,000 teammates in over 90 countries, we provide integrated technologies, products and services across the full continuum of care. Customers-and their patients-are at the heart of what we do. Our mission is to empower our customers to advance healthcare, and our success starts with our teammates. Job Description POSITION SUMMARY Owens & Minor is looking for a NOC Analyst II to join the NOC team responsible for monitoring and maintaining over 2000 servers and 3000 network devices, Database and backup located in Owens & Minor locations globally. The NOC Analyst is part of a collective team of engineers which troubleshoot and resolve routine and complex network, server, database and OS issues and alerts in a timely and efficient manner while maintaining target system uptimes. ESSENTIAL JOB FUNCTIONS: Monitor production and non-production systems located at Owens & Minor offices, data centers, distribution centers, and warehouses. Respond to alerts and event-generated incident tickets effectively and efficiently. Create and use Knowledge Base Articles to investigate, diagnose, and resolve incidents. Escalate complex incidents to Networking, Server, and other resources in accordance with established processes and procedures. Review and update status of incidents in ticketing system. Create trouble tickets with carriers for circuit issues. Interface with internal IT groups and business units as needed to achieve incident or problem resolution. Support the Major

### Machine Learning Hardware Architect, Google Cloud Silicon - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-02
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSb5Ztykt9GDsvh6yLbwO-evuOGmXD_5EQqAaQPmH2tWEjsACxwdTMl4OZe1mY6_aHFFTY-l0no3ftkwoAKkPJ4hydQVfwpgzbzzWGcZKYmHXc2zpuD1TP7jbFTpkw%3D%3D_V2&loc=IL&title=Machine+Learning+Hardware+Architect
- Excerpt: Machine Learning Hardware Architect, Google Cloud Silicon Tel Aviv, Israel; +1 more In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will own and lead the architecture of the Google Edge AI accelerators. You will work with the Google AI community and with external partners. You will combine the latest innovations in Machine Learning and integrated circuits to create advanced hardware acceleration solutions for Machine Learning training and inference. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on

### Silicon Validation Engineer, Google Cloud - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $138K-$198K
- Posted: 2026-06-11
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka5PTdUfs1wloIR9r81GHVZElnQY504gy9d04eiFR4ayEjsACxwdTCB2ZP3pLkpqqk00vPsYs_ALHZcsqhUuqbzq2FnH8npUPaR8oluodDTBd5CkkDiNYkk46ky2vQ%3D%3D_V2&loc=US&title=Silicon+Validation+Engineer
- Excerpt: Silicon Validation Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be helping in bringing custom Application-Specific Integrated Circuits (ASICs) from concept through to production. You will be a part of the silicon validation effort of the overall silicon product development lifecycle. Your efforts may center on power features, interfaces, HBM memory, compute functionality, or various aspects of system performance. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development

### Backend Senior Developer - SAP Concur Travel - SAP
- Location: Country Brazil | Internal Posting Location São Leopoldo (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/S%C3%A3o-Leopoldo-Backend-Senior-Developer-SAP-Concur-Travel-93022-718/1380170833/
- Excerpt: Backend Senior Developer - SAP Concur Travel Country Brazil | Internal Posting Location São Leopoldo We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. SAP Concur, market leader in integrated travel, expense and invoice management, is looking for Software Developers to help making the product even stronger! Your responsibilities will include designing and developing cloud products using various tools and technologies. You will work in a great environment with many global teams to create value for our customers, delivering high quality and innovative product. You will also help design and ship AI-driven features (LLM-powered assistants, embedding-based search/RAG, and model-backed automation), ensuring they are production-ready, scalable, and compliant with privacy and fairness requirements. Value You Deliver Lead technical design decisions for complex features from conception to deployment. Architect end-to-end microservices solutions with advanced patterns: authentication, authorization, decoupling services, asynchronous queues, circuit breakers, distributed cache, auto scaling, infrastructure as code, load testing, failover, obser

### Optical Validation Engineer, Google Cloud - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $108K-$153K
- Posted: 2026-06-09
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYhKTo-jeL3O1mnf0076fIBSosr37uN4v2DdkPDclTxoEjsACxwdTKZlgtvIKVXiHPDKEHZOhsvkrqh4PTEqWKTZUa8wpeavlcCMB9xAMbQUzDC4AGZVSIyjz7RS1Q%3D%3D_V2&loc=US&title=Optical+Validation+Engineer
- Excerpt: Optical Validation Engineer, Google Cloud Sunnyvale, CA, USA The Optical Validation Team is responsible for supporting the development, new product introduction (NPI), and post-production testing of optical transceivers, switches, and technologies that power Google Cloud Platforms. We test new optical transceiver designs, unit, environmental, and system qualification of transceivers in a wide array of host networking and compute platforms, optical circuit switches (OCS), and transceiver component design at the wafer level. As an Optical Hardware Validation Engineer, you will play a key role in the development of Google Cloud network infrastructures. You will be asked to perform testing of novel and complex configurations of networking hardware, and collaborate closely with hardware and software teams to configure lab networks and test infrastructure that evaluate and characterize the performance of cloud computing and networking products. You will support lab maintenance, helping with the day-to-day operations with pride in cleanliness, organization, and safety which plays a key role in the rapid development and support of Google's data center technologies. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes

### Power Management Engineer, Platforms Engineering - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSEUvuNs3QzeX6ohXSFk0se3xJxajBVy2nKHIw2tG2XLEjsACxwdTK2pnfSU6gSLsVKAnwy2ficGgXAyMziB4JG_XA99H5ils8B7wDJcN8QuxHWuSV5MzRE65dGfSA%3D%3D_V2&loc=US&title=Power+Management+Engineer
- Excerpt: Power Management Engineer, Platforms Engineering Sunnyvale, CA, USA Our computational issues mean we can't just purchase off-the-shelf hardware; we've got to make it ourselves. Our platforms team designs and builds the hardware, software, and networking technologies that power all of Google's services. In this role, you will design and build the systems that are the heart of the computing infrastructure. You will develop from the lowest levels of circuit design to system design and see those systems all the way through to manufacturing. Your work has the potential to shape the machinery that goes into our data centers affecting millions of Google users. As a member of the team, you manage projects in multiple areas. You will also monitor the performance of vendors working on projects and evaluate new technologies. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay

### System Integration Lead, Pixel Watch - Google
- Location: Mountain View, CA, USA (unspecified)
- Salary: $236K-$330K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdxVgqmA5QVhxJpEE4vAEkBsVAChoU0JsExYzEftLZfgEjsACxwdTLrC852RyCY_toYMbCtdCxcHIreo94mS36uXdIvgRQd7BhDip7Sk22-NXYlauivE5hvkTZkP4g%3D%3D_V2&loc=US&title=System+Integration+Lead
- Excerpt: System Integration Lead, Pixel Watch Mountain View, CA, USA As a member of a fast-paced multi-disciplinary team, you use your creativity and range of engineering experience to explore solutions to a variety of engineering problems. As a mechanical engineer, you participate in the design, analysis, and prototyping of new concepts. You work in a manufacturing and product oriented development environment and collaborate with vendors and outside sources in order to see parts through to manufacture. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $236000 - $330000 (USD) + 25% bonus target + bonus + equity + benefits Learn more about benefits at Google . Identify, integrate, and validate cutting-edge technologies to enhance the next iteration of our products. Collaborate closely with a team of system architects, industrial designers, and product managers, contributing to the early definition of new products and the exploration of emerging technologies. Be able to maximize comfort and fit within an iconic design, all while delivering performance. Ensure seamless integration of these new technologies into the product line, encompassing module and system design, validation, and correlation. Partner with our operations teams during the early stages of system integration to establish and maintain high quality and yield standards. Minimum qualifications: Bachelor's degree in Mechanical Engineering, Product Design, or related field, or equivalent practical experience. 12 years of experience designing mechanical components such as plastic or metal parts, mechanical assemblies, printed circuit boards, or flexes. 12 years of experience using Computer-Aided

### Senior ECAD Library Engineer, Platforms Infrastructure - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSG-NDg0KJSk02xfjzOfco6WOTZjVyb91AI-PDmWHAhkEjsACxwdTB7zz3fX0RW6KfH79SkpJ0TG145sN1fIV_ExzM2MNbT-xaen8P5A5DpLnQZwdUL6hsrY9WAMOw%3D%3D_V2&loc=US&title=Senior+ECAD+Library+Engineer
- Excerpt: Senior ECAD Library Engineer, Platforms Infrastructure Sunnyvale, CA, USA As an ECAD Librarian, you will manage the Digital Network Architecture (DNA) of our hardware, building and organizing the libraries that allow our engineers to design the world's most powerful computing infrastructure. From large Ball Grid Array (BGA) packages to interconnects, you will ensure that every component is built for precision, manufacturability, and global scale. In this role, you will bridge the gap between Electrical Engineering, Printed Circuit Board Layout, and Manufacturing. You will architect a library system that supports seamless routing and hardware lifecycles. Your work ensures that Google's custom-built servers move from concept to high-volume manufacturing, directly impacting the infrastructure that powers services for millions of users. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users.Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Manage the

### Senior Hardware Systems Design Engineer, Platforms Infrastructure - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdN12o2CqiatJ5R2x8Ud7MEyDjq39zyY7sqpnrsS8ZgiEjsACxwdTFL9VkxaVrcEx0nqd2mXwlIoS6J9mZOnU9Gc195kBBfVbGDM9vkGDDYAdThzFkWMMoVWDyBILg%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Design+Engineer
- Excerpt: Senior Hardware Systems Design Engineer, Platforms Infrastructure Sunnyvale, CA, USA Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Senior Hardware Engineer in the Board and System Design team, you will work on ML/AI hardware systems projects to craft the solutions for current and future data center deployments. You will work with product teams to ensure that their goals are met with your systems. You will work with Application-Specific Integrated Circuit (ASIC), Field Programmable Gate Array (FPGA), Software, and Verification teams to ensure proper verification of features in your systems. You will work with the manufacturing teams to ensure that your designs are manufactured and ready for volume production. You will work with the field teams to support systems that are deployed in the data center. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes

### Performance Engineer/Developer - SAP
- Location: Region Europe | Country Czech Republic | Internal Posting Location Brno (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.sap.com/job/Brno-Performance-EngineerDeveloper-63900/1379211033/
- Excerpt: Performance Engineer/Developer Region Europe | Country Czech Republic | Internal Posting Location Brno We help the world run better At SAP, we keep it simple: you bring your best to us, and we'll bring out the best in you. We're builders touching over 20 industries and 80% of global commerce, and we need your unique talents to help shape what's next. The work is challenging - but it matters. You'll find a place where you can be yourself, prioritize your wellbeing, and truly belong. What's in it for you? Constant learning, skill growth, great benefits, and a team that wants you to grow and succeed. Summary: We are looking for a Senior Performance Engineer to join our SAP Green Token team and take ownership of the stability, resilience, and performance of our cloud-native sustainability platform. You will work across a full-stack environment - Java/Spring Boot microservices, and SAP BTP cloud infrastructure - to ensure our product delivers a fast, reliable experience at scale. The Role: Performance Analysis & Optimization: Profile and tune Java 25 / Spring Boot microservices, database queries (SAP HANA), throughput, and resource-efficiency targets. Load & Stress Testing: Design, implement, and maintain automated load/stress/soak test suites; define and enforce performance budgets for critical user journeys. Reliability Engineering: Identify single points of failure, improve error handling and retry/fallback strategies, and drive adoption of circuit-breaker and bulkhead patterns across services. Incident Prevention & Response: Conduct root-cause analyses of production incidents,

### Silicon Micro-architecture and RTL Lead, Google Cloud - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-28
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXiAZPQspEkwABvZ6BujZJltNS3E2m7WTxg4dUcXd9YtEjsACxwdTOYq9JSIqkGURs04FP8E5uhd97AQRZrIk6iLNW1H1k9NQg2lg39195nHmwKBIQxKVHgGCZBpRA%3D%3D_V2&loc=IN&title=Silicon+Micro-architecture+and+RTL+Lead
- Excerpt: Silicon Micro-architecture and RTL Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will be part of a team developing Application-Specific Integrated Circuits (ASIC) used to accelerate and improve traffic efficiency in data centers. You will collaborate with members of architecture, verification, power and performance, physical design, etc. to specify and deliver high quality designs for next generation data center accelerators. You will solve technical problems with innovative micro-architecture and practical logic solutions, and evaluate design options with complexity, performance, power and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to

### Silicon Quality and Reliability Engineer, Google Cloud - Google
- Location: Zhubei, Zhubei City, Hsinchu County, Taiwan; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaAU75i4_w2XWH9n124Pw_Te4B8Qqarg2I2Jt1JlqbmEEjsACxwdTEJgx-LCdkQPotP29fpSauah-bnUoRGwaRKkAEgeE3f70Yo4nwX20lbVWsIXk2X5NBQ1R1pKDQ%3D%3D_V2&loc=TW&title=Silicon+Quality+and+Reliability+Engineer
- Excerpt: Silicon Quality and Reliability Engineer, Google Cloud Zhubei, Zhubei City, Hsinchu County, Taiwan; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will help to build the System-on-a-chip (SoCs) that power these facilities by driving quality and reliability processes in High Volume Manufacturing (HVM) from an Integrated Circuit perspective. You will partner with cross-functional teams to develop HVM quality and reliability specifications while collaborating with global hardware teams, silicon design, validation, and engineering groups to ensure fleet excellence. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Perform the electrical and physical failure analysis on Central Processing

### RTL Design Engineer, Google Cloud, Silicon - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRdZcO5rQorwYsIKOXpPSknn10hl8Ydg2e55Pks_qKHgEjsACxwdTHFCJSO5ha3tKkQZ-1dfKUwcSbh4GVdNJqG3PDmoETP6LnpPwhrRoMIJrLAAOg1J_u6u1kui-A%3D%3D_V2&loc=IN&title=RTL+Design+Engineer
- Excerpt: RTL Design Engineer, Google Cloud, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be part of a team developing Application-Specific Integrated Circuit (ASICs) used to accelerate machine learning computation in data centers. You will collaborate with members of architecture, verification, power and performance, physical design to specify and deliver quality designs for next generation data center accelerators. You will solve technical problems with micro-architecture and practical reasoning solutions, and evaluate design options with complexity, performance, and power. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Own microarchitecture and implementation of Internet Protocol (IP) and subsystems. Work with Architecture, Firmware, and Software teams to drive feature closure

### Technical Program Manager III, Supplier Technology and Commodity Management, Cloud Supply Chain - Google
- Location: Austin, TX, USA (unspecified)
- Salary: $163K-$237K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcka7zUKbTPGQZs731FLVQGjOaKEMmYTn5E_hVuspPKa1eEjsACxwdTBnqd24nbfgg9IadgPh6YCCbsblxmypv3Vjjg-YGZBqC8tyFNMrgCO3v2SGC5A7DLa4igoArXQ%3D%3D_V2&loc=US&title=Technical+Program+Manager+III
- Excerpt: Technical Program Manager III, Supplier Technology and Commodity Management, Cloud Supply Chain Austin, TX, USA A problem isn't truly solved until it's solved for all. That's why Googlers build products that help create opportunities for everyone, whether down the street or across the globe. As a Technical Program Manager at Google, you'll use your technical expertise to lead complex, multi-disciplinary projects from start to finish. You'll work with stakeholders to plan requirements, identify risks, manage project schedules, and communicate clearly with cross-functional partners across the company. You're equally comfortable explaining your team's analyses and recommendations to executives as you are discussing the technical tradeoffs in product development with engineers. In this role, you will focus on securing leading-edge foundry nodes and 2.5D/3D packaging solutions. You will be responsible for designing a premier supply chain that integrates standard foundry oversight with technologies. Acting as a vital link between external partners and internal engineering, you will ensure technology alignment, capacity assurance, and competitive pricing for Google's custom silicon initiatives. You will be instrumental in the design, verification, and implementation of digital integrated circuits from concept to production, with a particular emphasis on ensuring seamless integration and outcomes with external technology providers. You will work on technologies for next-generation products, contributing to the full lifecycle of ASIC development while actively managing external technical engagements. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and

### Hardware Emulation Technical Lead, Google Cloud - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-06
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaQFCZfr9fta9Hrzv6W7IIgzyRaYsuvNRRPlRHdhBb5GEjsACxwdTOHTajLK4PYhtT-4ZpfVK0ivlmigzAPP5vKFKsuTlSOnhoXf-bV_Nw3gPoJ_vo_uubmxF1Po3A%3D%3D_V2&loc=IL&title=Hardware+Emulation+Technical+Lead
- Excerpt: Hardware Emulation Technical Lead, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define the emulation strategy, identify platforms and technologies to support all customers. Explore emulation methodologies, gather feedback from customers, and implement emulation workflows at scale. Support emulation customers with debugging hardware, software, tooling, and project-specific issues. Create tooling and automation to support emulation tools, licensing, and job management in Google infrastructure. Act as a primary interface to emulation vendors. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 10 years of experience in leading/managing an emulation team/project. Experience with coding and scripting in C or C++ or Python. Experience with emulation systems (e.g., ZeBu Server, Palladium, Veloce), compilation, debug, performance and methodology enhancements. Experience with various emulation technologies (Transactors, In-circuit Emulation, Hybrid), flows (Assertions, Coverage, UPF, Power), Debugging and Performance of compile and runtime environments. Experience

### Senior Mechanical Engineer, Debug - Google
- Location: Singapore (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckRBjDEUWQgMyp86BDQ5WJxuafrqezRhV2JQhYoUtbSV9EjsACxwdTDYwIdz1AROzLy8Ig0XFO3hoHanhKxxqZgc-wN_6FF-9-wn9l--1YCX7fR668spZmm0otU-BNA%3D%3D_V2&loc=SG&title=Senior+Mechanical+Engineer
- Excerpt: Senior Mechanical Engineer, Debug Singapore The Debug Project is a team of scientists and engineers dedicated to developing solutions for mosquito-borne disease control. We are developing technology to raise and release sterile mosquitoes. In this role, you will join a team of mosquito biologists, software engineers, and automation experts working to develop better ways to reduce the impact of mosquito-borne diseases. You will be responsible for research and development across various processes and products. You will be central to the design, development, deployment, and ongoing improvements of Debug technology and products. Design, build and integrate automated systems with a variety of electromechanical components, including servo systems, pneumatics, sensors, drive components, etc. Oversee the full product lifecycle, from defining requirements and prototype validation to the final launch of production-ready systems. Design and iterate with real-world users and use cases, inside and outside the factory. Test prototypes and released products, and resolve technical problems in production equipment. Use engineering tools such as Computer-Aided Design (CAD), Failure Mode and Effects Analysis (FMEA), and Design for Manufacturing (DFA) and incorporate engineering calculations to verify product performance. Collaborate with mechanical engineers, scientists, software engineers, and operations teams to solve technical tests that require unique solutions. Lead technical projects, improve current processes, and contribute to multi-year roadmaps for Debug Singapore. Minimum qualifications: Bachelor's degree in Mechanical Engineering, Product Design, or a related field, or equivalent practical experience. 5 years of experience with designing mechanical components such as plastic or metal parts, mechanical assemblies, printed circuit boards,

### Senior Silicon Physical Design Engineer - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2025-12-18
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcEmKw3OqCFQjNCd4HdZzERM6VJ1TALxcKuWEl9dOcK-EjsAvkGZm1vEX_yavFl_ZfZQwpnAYOQ9dnoNy3uz_4XMKzM4htTphNwR5OQcsn_0LABreM6jIaV9Q-VSQQ%3D%3D_V2&loc=IL&title=Senior+Silicon+Physical+Design+Engineer
- Excerpt: Senior Silicon Physical Design Engineer Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with functional design, Design for Testing (DFT), architecture, and packaging engineers. In this role, you will solve technical problems with innovative micro-architecture and practical logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Use problem-solving and simulation techniques to ensure performance, power, and area (PPA) are within defined requirements. Collaborate with cross-functional teams to debug failures or performance shortfalls and

### Semiconductor Design Engineer (Teradyne, Costa Rica) - Teradyne
- Location: Semiconductor Design Engineer (Teradyne, Costa Rica) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/Alajuela-Semiconductor-Design-Engineer-%28Teradyne%2C-Costa-Rica%29/1397296700/
- Excerpt: Semiconductor Design Engineer (Teradyne, Costa Rica) Semiconductor Design Engineer (Teradyne, Costa Rica) We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Opportunity Overview We're looking for a highly experienced Senior Analog Layout Engineer to join our semiconductor design team. In this role, you will lead the physical layout and verification of complex analog and mixed-signal ASICs in advanced FinFET technologies, helping deliver the next generation of Teradyne's test and automation platforms. You'll collaborate closely with circuit designers, physical design engineers, and cross-functional partners to create high-quality, manufacturable layouts that meet demanding performance, reliability, and schedule targets. Key Responsibilities Lead the layout design and integration of complex analog and mixed-signal ASIC blocks using Cadence Virtuoso. Develop floorplans, placement, routing, and top-le

### RTL Design Engineer, Google Cloud - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-13
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckeaZaY8K1vbuNMGCqWsh26a0PSQmg0gXYEAXsbTZwvv7EjsACxwdTMW5EltT0ZkPhWkVKAhQxqkn9K1CEi7dkQBqEUkLzfeiRihxVNswKV1IVtYb9M_MeGVLumHzBg%3D%3D_V2&loc=IL&title=RTL+Design+Engineer
- Excerpt: RTL Design Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will use Application-Specific Integrated Circuit (ASIC) design experience to be part of a team that develops complex ASIC System-on-Chip (SoC) intellectual property from proof-of-concept to production. This includes creating IP Level microarchitecture definitions, Register-Transfer Level (RTL) coding and all RTL quality checks. You will also have the opportunity to contribute to design flow and methodologies, including design generation automation. You will collaborate with members of architecture, software, verification, power, timing, synthesis design for testing etc. You will develop/define design options for performance, power and area. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers.

### Physical Designer Engineer, Google Cloud - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2025-12-15
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTjuPS0bNVqiOcmm9XLK5b_cjaMtqVx38-yqsSFVWvqTEjsAvkGZm4qfFl5OGlQQ3f_F9wFHbZoabYM75WVlDohL6IYuq2K4zE9TdwKkCTJXy6dKUtSwTws8S9rDBA%3D%3D_V2&loc=IL&title=Physical+Designer+Engineer
- Excerpt: Physical Designer Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a SoC Physical Design Engineer, you will collaborate with Functional Design, Design for Testing (DFT), Architecture, and Packaging Engineers. Additionally, you will solve technical problems with micro-architecture and logic circuits solutions, while evaluating design options with optimized performance, power, and area in mind. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and drive the implementation of physical design methodologies. Take ownership of one or more physical design partitions or top level. Drive to the closure of timing and power consumption of

### Senior SoC Power Engineer, Google Cloud - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-13
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckSBhMjb3rWYRacV3d3e6U-eb8MQacrfeuZM69vqGTYooEjsACxwdTCJGwClOZszRoUejOlZ4xxi8MNZyHf3oxOajFF-_qSs0XOB4VPOWNIPtfM8a8wlWYBLo5PJZDw%3D%3D_V2&loc=IL&title=Senior+SoC+Power+Engineer
- Excerpt: Senior SoC Power Engineer, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Our Platforms Infrastructure Engineering team designs and builds the hardware and software technologies that power all of Google's services. Our computational challenges are complex and unique, enabled by cutting-edge custom hardware designed and made in-house. As a hardware engineer, you will design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You will see those systems from concept all the way through to high-volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers, affecting millions of Google users. Develop methodology of SoC roll up of power reduction, projection, configuration, test plan and tools. Work intact with Architecture, Frontend and Backend teams driving power reduction features (both logic and circuit). Work with power delivery and packaging teams on simulations and scenario definitions. Work with Architecture and design verification (DV) to define power scenarios and tests, debug, and integrate into the flow. Track whether power goals are met throughout execution. Lead the power of a project. Own project priorities, and allocation of technical resources within the project, informing and escalating appropriately when external factors impact execution Minimum qualifications:

### Senior Silicon DFT Lead - Google
- Location: Haifa, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-04
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTY25Nhw2vAzN66W1qg5QyMMzem-P1VgFA1CJzPif01dEjsACxwdTDTXSZ6NRwLq-8FtsnR5LPXVU3Cy-wSjKW2rEUVo-u-1h9VbANELtTIPnZhTMwUyrAxAMc3huw%3D%3D_V2&loc=IL&title=Senior+Silicon+DFT+Lead
- Excerpt: Senior Silicon DFT Lead Haifa, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As the Design for Test (DFT) Engineer Lead, you will play a crucial role in DFT Architecture and DFT design, and support devices to production. You will be responsible for providing technical leadership in DFT, developing flows, automation, and methodology, planning DFT activities, tracking the DFT quality throughout the project life-cycle, and providing sign-off DFT to tapeout. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Lead and execute DFT activities in the design, implementation, and verification solutions for Application-Specific Integrated Circuits (ASIC). Develop DFT strategy

### Data Center Designer - Oracle
- Location: LONDON, United Kingdom, GB (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Parental leave: 14 weeks (not source-backed)
- Non-birth-parent leave: 14 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://careers.oracle.com/en/sites/jobsearch/job/335273/
- Excerpt: Data Center Designer LONDON, United Kingdom, GB The Oracle OCI team is looking for a Data Center Designer to join our team, someone who innovates & shares our passion for winning in the cloud marketplace. You will work closely with the data center development organization and Oracle vendors to build out, maintain and operationally improve the cloud infrastructure. The Data Center Designer evaluates reliability of materials, properties and techniques used in production; plans, designs and develops electronic parts, components, integrated circuitry, mechanical systems, equipment and packaging, and telecom system design. The successful candidate will focus, in part, on the following key responsibilities: Manage and create design of data center white space which includes rack layout, hot/cold containment, network infrastructure, branch circuit distribution, power requirements, cable pathway, and projected build phases. Collaborate with colocation providers and internal stakeholders to deliver project design criteria and develop Basis of Design Coordinate with key internal teams to establish requirements and work with colocation providers to ensure requirement are met Participate in development of OCI data center facilities requirements documentation Research new designs, materials, and construction methods for data center electrical and mechanical equipment and related components Create, develop, and maintain data center infrastructure site documentation, including floor plans, rack elevations, and cable matrices Review and evaluate RFI, RFP, and RFQ submittals Assist in creating global data center infrastructure standards Travel to new and existing data center for engineering analyses Meet critical deadlines for project schedules Participate in project coordination meetings, and clearly communicate any

### Network Engineer - Cloud BGP OSPF - Oracle
- Location: Singapore, SG (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Parental leave: 14 weeks (not source-backed)
- Non-birth-parent leave: 14 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://careers.oracle.com/en/sites/jobsearch/job/330107/
- Excerpt: Network Engineer - Cloud BGP OSPF Singapore, SG What You'll Do As a Principal Network Development Engineer within Oracle Cloud Infrastructure (OCI) Network Reliability Engineering (NRE), you will help ensure the reliability, scalability, and operational excellence of one of the world's largest cloud networks. You will work on complex network infrastructure challenges, develop automation to improve operational efficiency, and collaborate across engineering and operations teams to deliver highly available cloud services. Key Responsibilities - Maintain and improve the availability, performance, and reliability of OCI network services. - Diagnose, troubleshoot, and resolve complex network incidents across large-scale cloud environments. - Design and develop automation and tooling to eliminate repetitive operational tasks and prevent recurring issues. - Review and contribute to network architecture, service design, and lifecycle management initiatives. - Participate in network deployment, expansion, and upgrade projects. - Support engineering, operations, and partner teams during incident response and service restoration activities. - Lead operational excellence initiatives, including runbook development, process improvement, and operational readiness reviews. - Mentor engineers, support onboarding efforts, and contribute to technical interviews and hiring activities. - Represent the team in cross-functional reviews, governance meetings, and vendor engagements. Technical Qualifications Networking - Expert-level knowledge of routing and networking protocols including BGP, OSPF, IS-IS, TCP/IP, IPv4, IPv6, DNS, DHCP, and MPLS. - Strong hands-on experience with at least three of the following technologies: - Juniper - Cisco - Arista - InfiniBand - Firewalls - Data center switching platforms - Circuit management technologies - Proven ability to analyze network telemetry,

### Physical Design Lead, Static Timing Analysis - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-11
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckWZVSk_h_8KpIW9EhQPOBirwsSei3JZmw0CUW80Fm2_AEjsACxwdTE6EeZidZlI90JnBdCsAH7pRVwWLXQCulhW6wrBe2cnvl360E3r0voOcMRwjRbGzNYNuay-9xg%3D%3D_V2&loc=US&title=Physical+Design+Lead
- Excerpt: Physical Design Lead, Static Timing Analysis Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will drive Static Timing Analysis (STA) in the physical implementation of Application-specific integrated circuits (ASIC) using advanced technology nodes. You will lead timing margin derivation, constraint development and validation, and timing closure of large, complex high performance compute ASICs. You will develop static timing methodologies, margins, automation scripts, and write documentation. Additionally, you will work with architecture, logic design, and Design for testing (DFT) teams to fully implement cross-functional design requirements. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the

### Physical Design Engineer - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $138K-$198K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckXldy12fDsKHaDlGieRAaThLHHn4ayl_281ctyVFmDLHEjsACxwdTL6IPnRyQWCJFp8WxViQS-bCnKucylCwulIxMEZu87EbIvOMD9XySNgTkXqJ-MBZFGPr1Hdebg%3D%3D_V2&loc=US&title=Physical+Design+Engineer
- Excerpt: Physical Design Engineer Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a Physical Design Engineer, you will collaborate closely with cross-functional design, Design for Testing (DFT), architecture, power, and packaging engineers. In this role, you will address complex physical implementation issues at advanced process nodes, utilizing micro-architectural insights and practical logic circuit solutions. You will evaluate and optimize design options to deliver Performance, Power, and Area (PPA) for the next generation of Tensor Processing Unit (TPU) blocks and sub-chips. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping

### AC/RF Hardware Design Engineer, New College Graduate, (Teradyne, North Reading, MA) - Teradyne
- Location: Location not specified (unspecified)
- Salary: $69K-$111K
- Posted: 2026-05-01
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/
- Excerpt: AC/RF Hardware Design Engineer, New College Graduate, (Teradyne, North Reading, MA) We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! We attract, develop, and retain a high-performance workforce, comprised of people with diverse backgrounds and a shared drive for excellence. We strive to foster a positive and inclusive work environment that helps employees, and communities, thrive. Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Opportunity Overview Our AC/RF Hardware design group is seeking a highly motivated engineer to join our design team in North Reading, MA. In this role, you will design and release AC and RF solutions consisting of complex instruments. You will integrate across all development functions (Signal Delivery, Mechanical, Systems engineering, Circuit design, Signal Integrity, Project management, etc.) to successfully bring up

### Senior Power Integrity Engineer, Platforms Infrastructure - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $159K-$231K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckcXgw-i6Em_jLU1o7hEbfGsPNrfkWzTciT9tIr_HY5ICEjsACxwdTJiY0MowGP3L-F8vOQZeqnSY5TfVt4n0iY9DDQv7Awz5uu66Sdk4FRW0yjGNRJp6LVKy98Ohsw%3D%3D_V2&loc=US&title=Senior+Power+Integrity+Engineer
- Excerpt: Senior Power Integrity Engineer, Platforms Infrastructure Sunnyvale, CA, USA As a Power Integrity Engineer within Platforms Infrastructure Engineering, you will play a pivotal role in developing one of the world's fastest-growing computing infrastructures. Working with a collaborative and high impact team, you will design, analyze, validate, and deliver robust and innovative power delivery network solutions at the chip, package, board, rack, and pod levels. Your work will directly shape our next generation AI hardware for AL/ML, server, networking, and storage applications. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Design system-level power delivery network solutions across silicon, substrate packaging, and printed circuit boards

### NPI DFM Process Development Engineer (Teradyne, No Reading, MA, Agoura Hills, CA or Deer Park, IL) - Teradyne
- Location: North Reading, MA (unspecified)
- Salary: $77K-$122K
- Posted: 2026-06-12
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- Apply: https://jobs.teradyne.com/Teradyne/job/North-Reading-NPI-DFM-Process-Development-Engineer-%28Teradyne%2C-No-Reading%2C-MA%2C-Agoura-Hills%2C-CA-or-Deer-Park%2C-IL%29-MA/1361371800/
- Excerpt: NPI DFM Process Development Engineer (Teradyne, No Reading, MA, Agoura Hills, CA or Deer Park, IL) North Reading, MA We are the global test and automation specialists, powering next-generation technologies through sophisticated solutions. Behind every electronic device you use, Teradyne's test technology ensures your device works right the first time, every time! Our portfolio of automation solutions help manufacturers to develop and deliver products quickly, efficiently and cost-effectively. Together, Teradyne companies deliver manufacturing automation across industries and applications around the world! Our Purpose TERADYNE, where experience meets innovation and driving excellence in every connection. We are fueled by creativity and diversity of thought and in our workforce. Our employees are supported to innovate and learn something new every day. We cultivate a culture of inclusion for all employees that respects their individual strengths, views, and experiences. We believe that our differences enable us to be a better team - one that makes better decisions, drives innovation and delivers better business results. Location: North Reading, MA, Agoura Hills, CA or Deer Park, IL Opportunity Overview Teradyne's Semiconductor Test Division develops the world's leading equipment for testing electronics. Inside STD, our Operations New Product Introduction Group is looking for a dynamic, technically skilled Process Engineer to engage our Printed Circuit Board development space. This engineer will use their knowledge of PCBA's to influence next-generation test instrument product designs from con

### ASIC Design Verification Engineer, Google Cloud - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $116K-$166K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckdh6z7QLH_FnC6Q2djrOnB9cmLJUGexZNMyOfADhaIfQEjsACxwdTKN9LdtYKCpHAck9r9zWJdUED1OBNTZC2prwHCZewmRb_6OpZBlCYXztAonCoEpmbFQAyfK2Ow%3D%3D_V2&loc=US&title=ASIC+Design+Verification+Engineer
- Excerpt: ASIC Design Verification Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As an Application-Specific Integrated Circuit (ASIC) Design Verification Engineer, you will be part of a team developing ASICs used to accelerate computation in data centers. You will have dynamic, multi-faceted responsibilities in areas such as project definition, design verification, and silicon bringup. You will participate in the architecture, documentation, and verification of the next generation of data center accelerators. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with

### TPU Software Area Tech Lead, Cloud Platforms - Google
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdTIMxmCjFnf3IMLeXJ-5M6DxX0u8TCH23QNxDhhVWgGEjoACxwdTBQJpBWnf1JBwZkWXqMw3F6qeFepJzgqZJOeuLpNuE_KJyqS3T-ZEnRhhv9XjzAXZ8ZoO3E5_V2&loc=TW&title=TPU+Software+Area+Tech+Lead
- Excerpt: TPU Software Area Tech Lead, Cloud Platforms Taipei, Taiwan Google's software engineers develop the next-generation technologies that change how billions of users connect, explore, and interact with information and one another. Our products need to handle information at massive scale, and extend well beyond web search. We're looking for engineers who bring fresh ideas from all areas, including information retrieval, distributed computing, large-scale system design, networking and data storage, security, artificial intelligence, natural language processing, UI design and mobile; the list goes on and is growing every day. As a software engineer, you will work on a specific project critical to Google's needs with opportunities to switch teams and projects as you and our fast-paced business grow and evolve. We need our engineers to be versatile, display leadership qualities and be enthusiastic to take on new problems across the full-stack as we continue to push technology forward. With your technical expertise you will manage project priorities, deadlines, and deliverables. You will design, develop, test, deploy, maintain, and enhance software solutions. TPU is Google's custom-developed Application-Specific Integrated Circuits (ASICs) used to accelerate machine learning workloads, and is critical in Google's success in the ultra engaged AI space today. In this role, you will drive the end-to-end TPU software development and innovation across the full stack from hardware software interactions to large-scale distributed systems and networking protocols, and contribute directly to technology that enables Google's AI goal, and work with many cross-functional teams (e.g., hardware, system, data center deployment) to enable the

### ASIC RTL Engineer III, Silicon - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYpGadnwFrCxIRH2UMkhWyNCMxCjVAGVA6aWToBIpAPCEjsACxwdTFV479vqU9F4HM0FiVlOaWHkxUSgmkvseb_SWFfSDxd1pOKmRT3AsUAbimx9BACtuqm2yxWOjw%3D%3D_V2&loc=IN&title=ASIC+RTL+Engineer+III
- Excerpt: ASIC RTL Engineer III, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. In this role, you will be creating the micro-architecture and design of the critical IPs widely used across multiple mobile SOC's subsystems and running extensive quality checks including Lint, Clock Domain Crossing (CDC), low power checks (VCLP), synthesis, and timing and power analysis. You should be able to timely deliver IPs and work with various cross-functional teams (DV/DFT/PD/power) to ensure quality. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Define the block-level design document (e.g., interface protocol, block diagram, transaction flow, pipeline, etc.). Perform Register-Transfer Level (RTL) coding, function/performance simulation debug, and Lint/CDC/FV/UPF checks. Participate in synthesis, timing/power closure, and Field Programmable Gate Array (FPGA)/silicon bring-up. Participate in test plan and coverage analysis of the block and Application Specific Integrated Circuit (ASIC) level verification. Communicate and work with multi-disciplined and multi-site teams. Minimum qualifications: Bachelor's degree in Electrical

---
Source-backed benefit claims include source links; other benefit values are labeled separately.