# FewerJobs export - 100 curated jobs
Generated: 2026-06-15T07:04:42.760Z
Source: https://fewerjobs.com

## Filters applied
- **q**: Flow Engineering
- **quality_floor**: default
- **match_401k_strict**: true
- **parental_strict**: true
- **non_birth_strict**: true
- **pto_strict**: true
- **include_older**: false
- **verified_benefits_only**: true
- **apply_url_verified**: false
- **page**: 1
- **per_page**: 100
- **sort**: relevance

## Jobs
### Engineer - Flow & Thermal - Eaton Corporation
- Location: Hadapsar, Pune, Maharashtra, IND, 411013 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://eaton.eightfold.ai/careers/job/687237048671
- Excerpt: Engineer - Flow & Thermal Hadapsar, Pune, Maharashtra, IND, 411013

### Engineer - System modeling( Flow and Thermal ) - Eaton Corporation
- Location: Hadapsar, Pune, Maharashtra, IND, 411013 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://eaton.eightfold.ai/careers/job/687236281267
- Excerpt: Engineer - System modeling( Flow and Thermal ) Hadapsar, Pune, Maharashtra, IND, 411013

### 70th ISR Wing Task Flow and Process Manager - Leidos
- Location: Odenton, MD (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-20
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://leidos.wd5.myworkdayjobs.com/External/job/Odenton-MD/XMLNAME-70th-ISR-Wing-Task-Flow-and-Process-Manager_R-00183666
- Excerpt: 70th ISR Wing Task Flow and Process Manager Odenton, MD posted: Posted 23 Days Ago

### Technical Sales Specialist Flow Reagents and Antibodies - Thermo Fisher Scientific
- Location: London, United Kingdom (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Paisley-United-Kingdom/Technical-Sales-Specialist-Flow-Reagents-and-Antibodies_R-01351302-1/apply
- Excerpt: Technical Sales Specialist Flow Reagents and Antibodies London, United Kingdom Embrace the opportunity to become a Technical Sales Specialist and drive customer success with innovative flow reagents and antibodies solutions. Leverage your technical expertise and sales acumen to build strong relationships, exceed targets, and make a global impact in life sciences. Grow your career with Thermo Fisher Scientific and help shape the future of scientific advancement.

### Technical Sales Specialist, Flow Consumables - Chicago - Thermo Fisher Scientific
- Location: Chicago, Illinois, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-23
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Chicago-Illinois-USA/Techical-Sales-Specialist--Flow-Consumables_R-01349102/apply
- Excerpt: Technical Sales Specialist, Flow Consumables - Chicago Chicago, Illinois, United States of America Embrace the opportunity to become a Technical Sales Specialist and drive sales of innovative flow cytometry reagents to leading scientific and industrial clients. Leverage your expertise in research laboratory work and sales to build strong client relationships, exceed targets, and make a real impact in the life sciences sector. Grow your career with Thermo Fisher Scientific.

### Automation Lead - Warehouse & Material Flow (US Region) - Jabil
- Location: Salisbury, NC (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jabil.wd5.myworkdayjobs.com/Jabil_Careers/job/Salisbury-NC/Automation-Lead---Warehouse---Material-Flow--US-Region-_J2443309
- Excerpt: Automation Lead - Warehouse & Material Flow (US Region) Salisbury, NC posted: Posted 7 Days Ago

### Principal Data Flow Engineer - Leidos
- Location: Columbia, MD (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- Parental leave: 4 weeks (not source-backed)
- Non-birth-parent leave: 4 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://leidos.wd5.myworkdayjobs.com/External/job/Columbia-MD/Principal-Data-Flow-Engineer_R-00183648-1
- Excerpt: Principal Data Flow Engineer Columbia, MD posted: Posted 24 Days Ago

### Global Product Marketing Manager, Flow Cytometry Automation - Becton Dickinson
- Location: USA CA - Milpitas 135 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-11
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://bdx.wd1.myworkdayjobs.com/EXTERNAL_CAREER_SITE_USA/job/USA-CA---Milpitas-135/Global-Product-Marketing-Manager--Flow-Cytometry-Automation_R-544148-1
- Excerpt: Global Product Marketing Manager, Flow Cytometry Automation USA CA - Milpitas 135 posted: Posted Yesterday

### Technical Sales Specialist – Flow Cytometry - Thermo Fisher Scientific
- Location: Gangnam-gu, Seoul, Korea, Republic of (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Gangnam-gu-Korea-Republic-of/Technical-Sales-Specialist---Flow-Cytometry_R-01345586/apply
- Excerpt: Technical Sales Specialist – Flow Cytometry Gangnam-gu, Seoul, Korea, Republic of Embrace the opportunity to become a Technical Sales Specialist - Flow Cytometry and drive revenue growth across leading instrument and consumables solutions. Leverage your expertise in flow cytometry, technical sales, and application support to expand market share in immunology, cell therapy, and translational research. Make a global impact with Thermo Fisher Scientific.

### Director of Engineering - US Growth (Large Factor Assembly, Industrial Engineer, and Material Flow) - Jabil
- Location: 6 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jabil.wd5.myworkdayjobs.com/Jabil_Careers/job/Salisbury-NC/Director-of-Engineering---US-Growth--Large-Factor-Assembly--Industrial-Engineer--and-Material-Flow-_J2453183
- Excerpt: Director of Engineering - US Growth (Large Factor Assembly, Industrial Engineer, and Material Flow) 6 Locations posted: Posted Today

### Senior Systems Engineer, Variable Refrigerant Flow (VRF) - Carrier Global
- Location: CAI23: Carrier-Indianapolis, 7310 West Morris Street, Indianapolis, IN, 46231 USA (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-21
- Parental leave: 8 weeks (not source-backed)
- Non-birth-parent leave: 8 weeks (not source-backed)
- Apply: https://carrier.wd5.myworkdayjobs.com/Jobs/job/CAI23-Carrier-Indianapolis-7310-West-Morris-Street-Indianapolis-IN-46231-USA/Senior-Systems-Engineer--Variable-Refrigerant-Flow--VRF-_30205366
- Excerpt: Senior Systems Engineer, Variable Refrigerant Flow (VRF) CAI23: Carrier-Indianapolis, 7310 West Morris Street, Indianapolis, IN, 46231 USA posted: Posted 22 Days Ago

### EDA Design Flow Development Engineer - Intel
- Location: 4 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://intel.wd1.myworkdayjobs.com/External/job/US-California-Santa-Clara/EDA-Design-Flow-Development-Engineer_JR0284647-1
- Excerpt: EDA Design Flow Development Engineer 4 Locations posted: Posted Today

### Maintenance Technician 1 - Flow Center - Hampton, GA - Target Corporation
- Location: 1000 Site Pkwy, Hampton,GA 30228 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/1000-Site-Pkwy-HamptonGA-30228/Maintenance-Technician-1---Flow-Center---Hampton--GA_R0000441269
- Excerpt: Maintenance Technician 1 - Flow Center - Hampton, GA 1000 Site Pkwy, Hampton,GA 30228 posted: Posted 4 Days Ago

### Maintenance Technician 1 - Flow Center - Chicago, IL - Target Corporation
- Location: 3501 S Pulaski Rd, Chicago,IL 60623-4926 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/3501-S-Pulaski-Rd-ChicagoIL-60623-4926/Maintenance-Technician-1---Flow-Center---Chicago--IL_R0000441460
- Excerpt: Maintenance Technician 1 - Flow Center - Chicago, IL 3501 S Pulaski Rd, Chicago,IL 60623-4926 posted: Posted 8 Days Ago

### Senior Field Service Engineer – Life Sciences (Flow Cytometry & Centrifugation) - Danaher Corporation
- Location: FAERIE GLEN, South Africa (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://danaher.wd1.myworkdayjobs.com/DanaherJobs/job/ZAF---Remote/Senior-Field-Service-Engineer---Life-Sciences--Flow-Cytometry---Centrifugation-_R1310889/apply
- Excerpt: Senior Field Service Engineer – Life Sciences (Flow Cytometry & Centrifugation) FAERIE GLEN, South Africa Join our team as a Senior Field Service Engineer - Life Sciences and play a pivotal role in supporting advanced laboratory instrumentation across Gauteng. Leverage your expertise in flow cytometry and centrifugation systems to ensure instrument uptime, reliability, and customer satisfaction in a dynamic, high-impact scientific environment.

### Senior CPU Design Engineer- FE Integration and FE Flow - Intel
- Location: India, Bangalore (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://intel.wd1.myworkdayjobs.com/External/job/India-Bangalore/Senior-CPU-Design-Engineer--FE-Integration-and-FE-Flow_JR0283267
- Excerpt: Senior CPU Design Engineer- FE Integration and FE Flow India, Bangalore posted: Posted 30+ Days Ago

### Staff Engineer Physical Design Flow Expert / PD Methodology & Automation - Analog Devices
- Location: India, Bangalore, RMZ (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://analogdevices.wd1.myworkdayjobs.com/External/job/India-Bangalore-RMZ/Staff-Engineer-Physical-Design-Flow-Expert---PD-Methodology---Automation_R262830
- Excerpt: Staff Engineer Physical Design Flow Expert / PD Methodology & Automation India, Bangalore, RMZ posted: Posted 17 Days Ago

### Maintenance Technician 2 - Flow Center - Hampton, GA - Target Corporation
- Location: 1000 Site Pkwy, Hampton,GA 30228 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/1000-Site-Pkwy-HamptonGA-30228/Maintenance-Technician-2_R0000440404
- Excerpt: Maintenance Technician 2 - Flow Center - Hampton, GA 1000 Site Pkwy, Hampton,GA 30228 posted: Posted 4 Days Ago

### Senior STA Flow Engineer - NVIDIA Corporation
- Location: 2 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-18
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-STA-Flow-Engineer_JR2014682-1
- Excerpt: Senior STA Flow Engineer 2 Locations posted: Posted 25 Days Ago

### Global Product Marketing Manager, Flow Cytometry Instrument Growth Initiatives - Becton Dickinson
- Location: 58 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://bdx.wd1.myworkdayjobs.com/EXTERNAL_CAREER_SITE_USA/job/USA-CA---Milpitas-135/Global-Marketing-Manager--Product-Lifecycle-Management_R-539196-1
- Excerpt: Global Product Marketing Manager, Flow Cytometry Instrument Growth Initiatives 58 Locations posted: Posted 30+ Days Ago

### Heat Transfer & Fluid Flow Engineer - Fiber Manufacturing - Owens Corning
- Location: Granville, OH (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://careers.owenscorning.com/job/Granville-Heat-Transfer-&-Fluid-Flow-Engineer-Fiber-Manufacturing-OH-43023-1200/1285036800/
- Excerpt: Heat Transfer & Fluid Flow Engineer - Fiber Manufacturing Granville, OH PURPOSE OF THE JOB The Heat Transfer & Fluid Flow Engineer - Fiber Manufacturing leads development of new technologies from a fundamental science approach that delivers greater manufacturing productivity and product quality with capital-efficient operations. This position requires a deep understanding of the physics and engineering challenges involved in fiberizing at high temperatures and rotational speeds, as well as proficiency in mechanical engineering, heat transfer and turbulent fluid flow. This extends to the engineering challenges of collecting fibers from a high-flow, turbulent air stream to achieve uniform weight distribution and optimal pack structure that deliver desirable thermal and mechanical properties to the product. The engineer will utilize physical experimentation, theoretical models, and advanced numerical modeling tools for designing and analyzing fiberizing and collection systems with the goal to enhance performance while using scientific approaches that balance accuracy and cost. The engineer is also responsible to work with an extended team to translate the fundamental understanding into practical designs for evaluation in venues that range from a laboratory environment to an industrial manufacturing plant. Reports to: Fiberizing R&D Leader Span of Control : Individual contributor with strong collaboration across the team, labs and manufacturing plants JOB RESPONSIBILITIES Commitment to Safety Commit to our safety standard: all accidents are preventab

### Staff System Software Engineer, RTL-to-GDS Flow Platform - NVIDIA Corporation
- Location: US, CA, Santa Clara (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-22
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Staff-System-Software-Engineer--RTL-to-GDS-Flow-Platform_JR2018368
- Excerpt: Staff System Software Engineer, RTL-to-GDS Flow Platform US, CA, Santa Clara posted: Posted 21 Days Ago

### CAD Engineer - Timing for Gate-Level Flows & Methodologies - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $147K-$272K
- Posted: 2026-04-13
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200657612/cad-engineer-timing-for-gate-level-flows-methodologies?team=HRDWR
- Excerpt: CAD Engineer - Timing for Gate-Level Flows & Methodologies Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, youʼll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). Youʼll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means youʼll be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices! In this role as a member of the STA CAD team, you will be an integral part of the effort to improve the performance of Apple Silicon. You will be responsible for all aspects of static timing methodologies, addressing timing challenges on advanced tech nodes through the development of flows and methodologies used by all Apple Silicon teams in driving timing analysis and closure for first time right silicon. As a member of our STA CAD team, you will: • Develop, maintain, and enhance existing gate-level STA flows for Apple silicon designs • Work with design teams to understand and debug issues related to constraints, flow scripts, and timing closure • Facilitate and drive STA methodology changes to improve overall STA flows as it relates to efficiency/productivity and silicon timing correlation • Develop and maintain scripts and methods for timing analysis and power

### Senior Manager, Risk Product and Flows - Fiserv
- Location: New York, New York (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 2 weeks (not source-backed)
- Apply: https://fiserv.wd5.myworkdayjobs.com/EXT/job/New-York-New-York/Senior-Manager--Risk-Product-and-Flows_R-10388754
- Excerpt: Senior Manager, Risk Product and Flows New York, New York posted: Posted 2 Days Ago

### Inside Sales Technical Specialist Flow Cytometry reagents & Antibodies, on site France (Villebon) or Belgium (Merelbeke) - Thermo Fisher Scientific
- Location: Courtaboeuf, France (onsite)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Courtaboeuf-France/Inside-Sales-Technical-Sales-Specialist-Flow-Cytometry-reagents---Antibodies_R-01348881/apply
- Excerpt: Inside Sales Technical Specialist Flow Cytometry reagents & Antibodies, on site France (Villebon) or Belgium (Merelbeke) Courtaboeuf, France Embrace the opportunity to become an Inside Sales Technical Specialist - Flow Cytometry Reagents & Antibody, driving sales growth across France and Belgium. Leverage your consultative selling skills and scientific expertise to build strong customer relationships and exceed targets. Enjoy career development with a global leader in scientific solutions. Ready to make an impact? Apply today!

### Senior System Architecture Engineer – End-to-End Data and Control Flows - NVIDIA Corporation
- Location: 3 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/Israel-Yokneam/Senior-System-Architecture-Engineer---End-to-End-Data-and-Control-Flows_JR2015023
- Excerpt: Senior System Architecture Engineer – End-to-End Data and Control Flows 3 Locations posted: Posted 30+ Days Ago

### Senior Physical Design Methodology Engineer, Innovus Flows - NVIDIA Corporation
- Location: 4 Locations (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://nvidia.wd5.myworkdayjobs.com/NVIDIAExternalCareerSite/job/US-CA-Santa-Clara/Senior-Physical-Design-Methodology-Engineer--Innovus-Flows_JR2011617-1
- Excerpt: Senior Physical Design Methodology Engineer, Innovus Flows 4 Locations posted: Posted 15 Days Ago

### Physical Synthesis CAD Engineer - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $147K-$272K
- Posted: 2026-04-17
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200658232/physical-synthesis-cad-engineer?team=HRDWR
- Excerpt: Physical Synthesis CAD Engineer Austin, United States of America Do you want to directly impact the performance of every iPhone, iPad, and Mac? You'll push the boundaries of physical synthesis for Apple's cutting-edge processors, solving problems that determine whether our next-generation CPUs, GPUs, and NPUs can deliver breakthrough performance while maintaining industry-leading power efficiency. You'll own the synthesis challenges that matter most to Apple Silicon. You will apply your hands-on skills in developing, improving and supporting the implementation flow from RTL through GDS signoff. You will be directly responsible to improve physical synthesis techniques through innovative scripts, flows and automation. As the synthesis and flow expert, you'll partner closely with design teams to define what works best for their specific challenges. You'll develop the methodologies, tools, and optimized flows that enable design teams to achieve breakthrough PPA results. You'll push beyond conventional synthesis limits - developing innovative techniques and proving their effectiveness by running full validation flows from RTL through place-and-route and timing signoff to show actual PPA improvements. Your optimizations will directly translate to faster, more efficient Apple devices. You'll work directly with EDA vendors to shape tool roadmaps, build custom solutions for problems that push beyond industry standards, and see your work ship in millions of devices. Develop breakthrough physical synthesis techniques and validate them with full implementation flows (PNR, STA, power analysis) Apply advanced RTL optimization techniques to achieve substantial improvements in performance, power, and area (PPA) Partner with design teams to define optimal methodologies and flows,

### Senior Physical Design CAD Engineer - Cisco
- Location: Bangalore, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-18
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Bangalore-India/Senior-Physical-Design-Engineer_2010348-1
- Excerpt: Senior Physical Design CAD Engineer Bangalore, India Meet the team You'll join the CAD Physical Design team within Cisco Silicon One, responsible for end-to-end backend methodology and flow development from RTL to GDS. This team plays a vital role in delivering high-quality VLSI designs and enabling advanced silicon innovation. Our design center brings together experts across silicon hardware and software, encouraging a collaborative environment passionate about technical excellence and continuous improvement. Your impact As a member of our team, you'll help shape and enhance signoff and implementation flows that support the delivery of high-performance, large-scale, and highly complex devices. Your work will directly contribute to pushing the boundaries of modern chip design. Develop, maintain, and improve backend methodologies and flows from RTL to GDS to enable robust, high-quality VLSI designs. Contribute to the evolution of signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate closely with multi-functional engineering teams to support and improve implementation tool flows. Work with advanced silicon technologies and process nodes to deliver reliable, ground breaking designs. Minimum qualifications We are looking for a CAD Physical Design Engineer with 8+ years of experience in Physical Design CAD with strong PnR and STA expertise, or a Design Engineer with solid backend design experience. B.Sc. or M.Sc. in Electrical Engineering, Computer Engineering, or a related field. Strong understanding of Static Timing Analysis (STA) flows. Familiarity with place and route (PnR), physical verification (PV), and formal verification (FV). Hands-on experience with Physical Design

### Senior Physical Design Engineer - Signoff Methodology - Cisco
- Location: Armenia (hybrid)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960
- Excerpt: Senior Physical Design Engineer - Signoff Methodology Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you'll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You'll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what's possible in chip design. Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design. Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate with engineering teams to support and enhance implementation tool flows. Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. Strong understanding of STA flows. Familiarity with PnR,

### Field Marketing Manager Flow Cytometry Southeast North America - Danaher Corporation
- Location: Miami, Florida, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-25
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://danaher.wd1.myworkdayjobs.com/DanaherJobs/job/Miami-Florida-United-States/Field-Marketing-Manager-Flow-Cytometry-Southeast-North-America_R1311242/apply
- Excerpt: Field Marketing Manager Flow Cytometry Southeast North America Miami, Florida, United States of America Embrace the opportunity to become a Field Marketing Manager, Flow Cytometry, and drive impactful marketing strategies across Southeastern North America. Leverage your expertise in field marketing, event planning, and sales support to accelerate growth in the life sciences sector. Collaborate with cross-functional teams and key opinion leaders to shape innovative campaigns and make a real difference.

### SoC Power Flow Methodology Engineer - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $140K-$258K
- Posted: 2026-04-10
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200657085/soc-power-flow-methodology-engineer?team=HRDWR
- Excerpt: SoC Power Flow Methodology Engineer Austin, United States of America Are you passionate about crafting solutions to intricate challenges? Join the Low Power group at Silicon Technologies and contribute to the development of cutting-edge technology and capabilities for low-power chip design. Your work will fuel Apple's next-generation chips! Responsible for developing and improving low-power flow algorithms using AI and machine learning, which significantly impacts the work of many designers involved in mobile system-on- chips. In this role, you'll develop innovative automated tools and capabilities for the Silicon Engineering Power team. Your contributions will enable the creation of chips with unprecedented power efficiency. You'll be involved in the architecture, implementation, and validation of advanced low-power design and verification workflows. Additionally, you'll shape low-power strategies for emerging technologies. Your responsibilities will encompass the development of flows and tools for power analysis, optimization, and verification, seamlessly integrated into stages such as RTL development/ verification, synthesis, or place-and-route (P&R). You'll actively leverage various AI tools to innovate new solutions and enhance existing ones. Additionally, you'll collaborate with design teams to address queries, resolve issues, and ensure the smooth adoption of these methodologies. Minimum Qualifications: A minimum of a bachelor's degree in relevant field and a minimum of 3 years of relevant industry experience Preferred Qualifications: Solid grasp of VLSI designs and SOC design processes. Enthusiasm for scripting and leveraging low-power expertise to innovate software solutions. Enthusiasm for leveraging AI/ML to innovate low-power methodologies and flows. Experience in flow development and algorithm design using Python/Perl/TCL.

### STA CAD/Methodology Engineer - Cisco
- Location: Armenia (hybrid)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/STA-CAD-Methodology-Engineer_1451959
- Excerpt: STA CAD/Methodology Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco's Silicon One Engineering team offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. Contribute to the development, maintenance, and automation of STA signoff flows for complex SoC designs. Assist with timing constraint development (SDC) and validation for multi-mode, multi-corner analysis. Develop and enhance automation scripts and utilities (TCL, Python) to streamline timing flows and improve engineering efficiency. Work with senior engineers to support timing closure during the design cycle, assisting with debug and issue triage. Collaborate with RTL, DFT, and physical design teams to align on design intent and STA best

### Standard Cell Design Methodology & Flow Engineer - Apple
- Location: San Diego, United States of America (unspecified)
- Salary: $163K-$290K
- Posted: 2026-04-10
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200657030/standard-cell-design-methodology-flow-engineer?team=HRDWR
- Excerpt: Standard Cell Design Methodology & Flow Engineer San Diego, United States of America Do you have passion to join a world-class Digital Design Engineering group and take imaginative and revolutionary ideas and determine how to turn them into reality! You will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking and groundbreaking ideas to the real world. You'll help design the tools that allow us to bring customers experiences they've never-before envisioned. We have an extraordinary opportunity for Standard Cell Design Methodology and Flow Engineers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering quality products to market quickly. Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will have the opportunity to integrate and come-up with new insights, as well as work with a team of talent engineers. In this role on our custom circuits team, you will: - Be the interface to internal CAD team for planning production flows and with foundry on PDK requirements. - Collaborate with technology team on new process requirements and work with design/CAD team to enable relevant tools/flows - Implement sophisticated digital block in Verilog/SystemVerilog, run simulations or formal check for verification. - Use data analysis techniques and/or sophisticated Machine Learning models to study the circuit trends in timing, power, and area, and to potentially detect

### Strategic Partner Development Principal Lead, Flow Enterprise - Google
- Location: New York, NY, USA; +3 more (unspecified)
- Salary: $176K-$256K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdtMSLQK6WgF202UkB0RPTwZznJcRz_FY9mM_NbqRbPQEjsACxwdTOpCfwgIAdFa_ssazJGyDztW2PNNBDRfaBD_fu9nfc3QUxeO9H_xSnlF_EFBXZMuy6ZoepFQPA%3D%3D_V2&loc=US&title=Strategic+Partner+Development+Principal+Lead
- Excerpt: Strategic Partner Development Principal Lead, Flow Enterprise New York, NY, USA; +3 more As a Strategic Partner Development Manager, you'll open doors with potential partners, lead exploratory discussions and evaluate/develop business opportunities. You will lead cross-functional teams, provide thought leadership and serve as a mentor to managers and associates. You are comfortable escalating and presenting business development strategies and key issues to senior management. You'll work closely with Google Product, Engineering, Legal and Sales teams on new product initiatives and key strategic relationships that support our online advertising business. As a Strategic Partner Development Principal Lead, you will open doors with potential partners, lead exploratory discussions and evaluate/develop business opportunities. You will lead cross-functional teams, provide thought leadership and serve as a mentor to managers and associates. You will be comfortable in escalating and presenting business development strategies and key issues to executive management. You will work closely with Google Product, Engineering, Legal and Sales teams on new product initiatives and key relationships that support our online advertising business. The Flow Enterprise Partnerships team will play a critical role to help launch and scale an enterprise-grade version of Flow, Google's AI-powered, content creation suite. The team will help design the product business model, identify and establish a customer pipeline, and develop the channel partnerships to help bring it to market. The team will collaborate with a variety of cross-functional and product teams to utilize and navigate Google's existing enterprise offerings. The team's mission will be to maximize Flow Enterprise Annual

### Custom Circuit Methodology Engineer - Apple
- Location: Cary, United States of America (unspecified)
- Salary: $120K-$210K
- Posted: 2026-04-30
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200660689/custom-circuit-methodology-engineer?team=HRDWR
- Excerpt: Custom Circuit Methodology Engineer Cary, United States of America At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The people who work here have reinvented entire industries with Apple hardware products. That same passion for innovation that goes into our products also applies to our practices, strengthening our dedication to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple products. Multifaceted, smart people and inspiring, cutting-edge technologies are the norm here. As a member of the Mixed-Signal design team, you will build and support innovative design methodology, customize, and automate flows for sophisticated Mixed-Signal IP designs. The design flows are used by multiple different IPs of multiple projects at multiple sites. You will collaborate with mixed-signal design teams, CAD teams, and EDA vendors. Good interpersonal skills are essential. In this role, you will be involved in all aspects of the custom design process, from schematic capture, layout, and extraction to simulation and EMIR/timing analysis flows. You will work with design and CAD teams to identify inefficiencies in the mixed-signal design process and drive the improvement efforts to completion. You will prototype and develop innovative solutions to address design teams' needs and work closely with the CAD team to debug issues and enhance existing flows. You will test, deploy, and support new and existing tools and flows. As well as

### Senior Product Manager, Flow Music, Google Labs - Google
- Location: San Francisco, CA, USA (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fckdr3a213V35nI_2TGY0NPpglh2qXjlas1DXUKKaGe5-WEjsACxwdTHQpMwyLB7I6khxQ864vQsmJBQuJXJuP6uLorBFckk2BqgbHkL-bs9Tk6EiXzSowQSInDy2MFg%3D%3D_V2&loc=US&title=Senior+Product+Manager
- Excerpt: Senior Product Manager, Flow Music, Google Labs San Francisco, CA, USA At Google, we put our users first. The world is always changing, so we need Product Managers who are continuously adapting and excited to work on products that affect millions of people every day. In this role, you will work cross-functionally to guide products from conception to launch by connecting the technical and business worlds. You can break down complex problems into steps that drive product development. One of the many reasons Google consistently brings innovative, world-changing products to market is because of the collaborative work we do in Product Management. Our team works closely with creative engineers, designers, marketers, etc. to help design and develop technologies that improve access to the world's information. We're responsible for guiding products throughout the execution cycle, focusing specifically on analyzing, positioning, packaging, promoting, and tailoring our solutions to our users. Flow Music empowers the musician in all of us. We help our users craft, refine and share music they are proud of. The core of our product is an intelligent, agentic partner that collaborates with users to create songs, playlists, music videos, novel instruments, and new musical worlds. We sit at the intersection of frontier generative audio models, intuitive UX design, and the raw joy of the creative process. Flow Music is a new part of the Flow family, and marks the beginning of a new Google product line for creativity. We're building creative tools with the artists that are most eager

### ASIC Design for Testability Engineer, Silicon - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-11
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQoPfA80Ph6n6nw-gsFYkJ2uS0YV4a5IIppzAOakJ_NGEjsACxwdTLA4Bl9HjOS8oZzBY_mM11SsTia88G339R_-gVU8fqXpL2b8DWjb3tVBQ9t0deMHu8JcH34KMQ%3D%3D_V2&loc=IN&title=ASIC+Design+for+Testability+Engineer
- Excerpt: ASIC Design for Testability Engineer, Silicon Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Work with a team of DFT engineers, working with RTL, Physical Designer Engineers, SOC DFT and Product Engineering team. Work on Subsystem level DFT SCAN, MBIST Architecture with multiple voltage, power domains. Write basic to complex scripts to automate the DFT flow. Develop tests that can be used for Production in the ATE flow. Work with the members of the DFT team to deliver overall deliverables for 2 or more complex Subsystems in a SoC. Minimum qualifications: Bachelor's degree in Building Engineering, Electrical and Electronics Engineering, Controls, IT, or equivalent practical experience. 4 years of experience in DFT/DFD flows and methodologies. Experience with Scan insertion, Automatic Test Pattern Generation (ATPG), Gate Level Simulations and Silicon Debug, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. Experience with DFT EDA

### McCrometer - Veralto
- Location: Location not specified (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.veralto.com/global/en/mccrometer
- Excerpt: McCrometer Careers at McCrometer Careers at McCrometer Imagine a brighter future. At McCrometer, we are global leaders in flow instrumentation. The flow measurement equipment we design, develop and manufacture is crucial for the most demanding industry applications. That demand drives our need for results-driven people with a passion for making the world a better place. About McCrometer Propelled by our solutions-oriented approach, our global flow specialists have developed leading technologies in flow measurement that support diverse environments; our products are used in the oil and gas industry, agriculture and irrigation, water and wastewater systems management, and myriad industrial processes. Previous " pha-phslide-next-arrow=" Next " data-ph-id="ph-widget-element-1009530542809586-19" data-ps="aaa52bd6-div-8"> Watch the video Loading... Watch the video Loading... Watch the video Loading... Our People The people behind our innovations are a source of great pride to us. Thanks to their expertise in flow physics and real-world operating dynamics, our application engineers, researchers and designers have put McCrometer at the forefront of flow technologies. Our Culture More important than what we do is how we operate together as a team across our global organization. Each of our businesses has a unique local culture which is inspired by variety of perspectives our team members bring to the table. However, Veralto and all our businesses share the same foundation comprised of our values and passion for continuous improvement through the Veralto Enterprise System that enables our teams to bring our purpose - Safeguarding the World's Most Vital Resources TM - to life around the world. Previous Next

### Senior Software Engineer (iOS) - Harmonic Inc
- Location: New York (unspecified)
- Salary: Not disclosed
- Posted: 2025-12-02
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://job-boards.greenhouse.io/harmonic/jobs/4633777005
- Excerpt: Senior Software Engineer (iOS) New York About us Harmonic is the startup discovery engine. It pains us to see great startup opportunities consistently go unfunded not because of lack of talent, but lack of signal. We're fixing that by mapping the entire startup landscape and building the tools that put the right companies in front of the right people at the right time. Investors, corporate development, and GTM teams at Anthropic, OpenAI, General Catalyst, Kleiner Perkins, Brex and Notion use us to find breakout companies before they're obvious and turn that discovery into action. Whether that's a check, an acquisition, partnership or won business. We're growing revenue at a rate of 100%+ annually, backed by $30M from Craft, Floodgate, and Sozo Ventures. We're committed to ensuring hundreds of billions of dollars find the right founders, so the innovations that matters most flourish. If that resonates, let's talk. About Flow Flow is Harmonic's next generation AI-native workflow tool; the central operating hub for venture capital, collapsing multiple traditional software categories into one platform for sourcing, researching and triaging investment opportunities. Flow turns Harmonic into a system of record and context - enabling customers to sync their internal network and business data and combine it with Harmonic's knowledge graph of tens of millions of companies and hundreds of millions of people, each enriched with 400+ dimensions. This enables context-aware, actionable workflows and insights (agentic and otherwise) - at scale. While Flow has strong initial traction from users, it is still in its

### Sr. Product Manager, Listings Flow - eBay Inc.
- Location: Toronto, Ontario, Canada (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://ebay.wd5.myworkdayjobs.com/apply/job/Toronto/Sr-Product-Manager--Listings-Flow_R0073076-1/apply
- Excerpt: Sr. Product Manager, Listings Flow Toronto, Ontario, Canada Join our team as a Senior Product Manager, Seller Experience, and drive the vision for seamless digital experiences for our global sellers. Lead cross-functional teams, shape product strategy, and deliver impactful solutions in a dynamic, data-driven environment. Make your mark on millions of users and help shape the future of ecommerce at eBay.

### Application Specialist Flow Cytometry Germany South West (d/f/m) - Danaher Corporation
- Location: Dusseldorf, Germany (remote)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://danaher.wd1.myworkdayjobs.com/DanaherJobs/job/DEU---Remote/Application-Specialist-Flow-Cytometry-Germany-South-West--d-f-m-_R1313068/apply
- Excerpt: Application Specialist Flow Cytometry Germany South West (d/f/m) Dusseldorf, Germany Embrace the opportunity to become an Application Specialist Flow Cytometry and make a real impact in life sciences. Support and innovate with advanced flow cytometry solutions, collaborate with experts, and help drive clinical research and diagnostics. If you thrive in a dynamic, remote environment and have strong technical and communication skills, we want to hear from you!

### Virtuoso Custom CAD Engineer - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $120K-$181K
- Posted: 2026-04-15
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200658102/virtuoso-custom-cad-engineer?team=HRDWR
- Excerpt: Virtuoso Custom CAD Engineer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient display and image sensors. You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a CAD Engineer of Custom Infrastructure Support, you will provide support for digital, analog and mixed-signal designs using Cadence. Responsibilities include general user support for both layout and schematic designers, tool customizations, Unix/Linux support and development testing of new tools and flows. In this highly visible role, you will: - Provide full support for Cadence custom flows, tool development, installation and maintenance - Work with the design team to develop utilities and scripts. - Support Virtuoso Layout and schematic software and release flows based on revision control system - Drive design methodology to increase productivity - Work with CAD team to provide general CAD services support, utilities, scripts while also working closely with the Design and Layout teams - Support tool configuration and application - Involvement in test development, automation and regression flow support - Create and maintain relevant documentation Minimum Qualifications: Minimum requirement of BS

### Scientist (Flow Cytometry) - IQVIA
- Location: Singapore (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Singapore/Scientist--Flow-Cytometry-_R1328686-1
- Excerpt: Scientist (Flow Cytometry) Singapore posted: Posted 30+ Days Ago

### CAD Electromagnetic RFIC Simulation Engineer - Apple
- Location: Sunnyvale, United States of America (unspecified)
- Salary: $181K-$318K
- Posted: 2026-04-17
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200658115/cad-electromagnetic-rfic-simulation-engineer?team=HRDWR
- Excerpt: CAD Electromagnetic RFIC Simulation Engineer Sunnyvale, United States of America Imagine what you could accomplish here. At Apple, innovative ideas rapidly evolve into industry-defining products. Do you have the drive and technical depth to make a meaningful impact? The engineers who work here have transformed entire industries through Apple Hardware innovations. That same rigor and creativity also guide our design methodologies - continually advancing performance, reliability, and sustainability across every generation of our products. As a core member of our best-in-class CAD organization, you will help shape next-generation electromagnetic analysis methodologies for advanced RFIC and multi-die designs. You will apply first-principles understanding of Maxwell's equations and field theory to develop and validate EM simulation flows using Finite Element and Method of Moments techniques. Your work will involve modeling complex package and interposer structures, enabling high-accuracy extraction of S-parameters, and ensuring robust signal integrity, coupling, and shielding performance across advanced packaging and 3DIC systems. Join our team of world-leading engineers and contribute to the development of groundbreaking technologies that power the next generation of Apple products. In this highly visible role, your primary responsibilities will include: • Maintain and support state of the art leading vendors Electromagnetic Finite-Element 3D solvers and Method-of-Moments solvers. • Streamline and automate SOC EM analysis CAD flow with ownership of the entire flow. • Support and collaborate with design groups (Physical-design and integration, Circuit-design / Power / Package & System / Technology) on their Electromagnetics requirements for various post layout flows. • Work side by side

### Senior STA CAD/Methodology Engineer - Cisco
- Location: Armenia (hybrid)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/Senior-STA-CAD-Methodology-Engineer_1451957
- Excerpt: Senior STA CAD/Methodology Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact This role as a Static Timing Analysis (STA) CAD/Methodology Engineer on Cisco's Silicon One Engineering team offers a key opportunity to enable the next generation of high-performance networking SoCs and ASICs. You will lead the development of scalable STA flows and automation, enhancing the efficiency and quality of design processes. Working at the intersection of design, methodology, and infrastructure, you will help establish best practices and drive innovation within a leading silicon organization. Architect, develop, and maintain static timing analysis (STA) methodologies and flows to support full-chip and hierarchical signoff for high-speed networking ASICs. Support timing closure for SoCs with complex clocking structures, high-speed interfaces, and large-scale integration. Develop robust SDC management, checking, and validation infrastructure across multi-mode, multi-corner (MMMC) scenarios. Build and optimize automation scripts and infrastructure (TCL, Python, Makefiles, etc.) to scale timing flows for enterprise-level SoC programs. Collaborate with RTL design, DFT, P&R, and signoff teams to

### Sales Manager, Flow Cytometry, North America - Danaher Corporation
- Location: Los Angeles, California, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://danaher.wd1.myworkdayjobs.com/DanaherJobs/job/Los-Angeles-California-United-States/Sales-Manager--Flow-Cytometry--North-America_R1310773/apply
- Excerpt: Sales Manager, Flow Cytometry, North America Los Angeles, California, United States of America Embrace the opportunity to become a Regional Sales Manager, Flow Cytometry, and lead a high-performing sales team in the life sciences sector. Drive growth, mentor talent, and collaborate cross-functionally to deliver impactful solutions. If you have strong sales leadership experience in flow cytometry and a passion for innovation, this is your next career move.

### Flow Iron Supervisor - Caterpillar Inc.
- Location: Midland, Texas (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cat.wd5.myworkdayjobs.com/caterpillarcareers/job/Midland-Texas/Flow-Iron-Supervisor_R0000372083
- Excerpt: Flow Iron Supervisor Midland, Texas posted: Posted 3 Days Ago

### Medical Technologist I- Flow Cytometry - Labcorp
- Location: Singapore (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://labcorp.wd1.myworkdayjobs.com/External/job/Singapore/Medical-Technologist-I--Flow-Cytometry_2614841
- Excerpt: Medical Technologist I- Flow Cytometry Singapore posted: Posted 30+ Days Ago

### Material Flow Planner - Applied Materials
- Location: Treviso,ITA (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://amat.wd1.myworkdayjobs.com/External/job/TrevisoITA/Material-Flow-Planner_R2620538
- Excerpt: Material Flow Planner Treviso,ITA posted: Posted 8 Days Ago

### Silicon Physical Design CAD Engineer - Google
- Location: New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckaVqc_WTfQFyj9QaPk21Npl7L8tNhqgAQOhRskJ-dyLcEjsACxwdTATWVZnSCVyO7NjRhLARd_Llyfy6cvGeOUQTxxmeRjj8q7LdRxxscKz7KvV_PfSOfvH6RkN3YA%3D%3D_V2&loc=TW&title=Silicon+Physical+Design+CAD+Engineer
- Excerpt: Silicon Physical Design CAD Engineer New Taipei, Banqiao District, New Taipei City, Taiwan; +1 more Be part of a various team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Co-work with project team for a more efficient and effective flow execution and results review mechanism in PDV field. Co-work with the methodology team to define Physical Design Verification (PDV) flow requirements for technology nodes Design Rule Check (DRC), Layout Versus Schematic (LVS), and Programmable Electrical Rule Check (PERC) checks. Import new features, improve job efficiency, and maintain a stable flow in PDV analysis to meet technology and project needs. Provide flow usage and execution support with documentation, training and troubleshooting. Minimum qualifications: Bachelor's degree in Electrical Engineering, a similar field, or equivalent practical experience. 4 years of experience in scripting languages such as Perl, TCL, Shell, or Python. Preferred qualifications: Master's degree or PhD in Electrical Engineering, Computer Engineering, Computer Science, or a similar field. 5 years of experience

### Patient Flow Nurse - Teladoc Health Inc
- Location: CAN - Any Location (Remote) (remote)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://teladoc.wd503.myworkdayjobs.com/teladochealth_is_hiring/job/CAN---Any-Location-Remote/Patient-Flow-Nurse_JR20698
- Excerpt: Patient Flow Nurse CAN - Any Location (Remote) posted: Posted 7 Days Ago

### CPU Design Timing Engineer - Apple
- Location: Beaverton, United States of America (unspecified)
- Salary: $181K-$318K
- Posted: 2026-04-14
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200657909/cpu-design-timing-engineer?team=HRDWR
- Excerpt: CPU Design Timing Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products! The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver groundbreaking Apple products! In this role, you will be responsible for all aspects of timing including working with the implementation and RTL teams on timing changes, helping with construction/modify timing flows, timing analysis, and timing closure. As the CPU Design Timing Engineer, you will be responsible for the timing closure of the project. Responsibilities include but are not limited to: • Working with the CAD team to develop the timing flow that will be used on the project including scripting to improve analysis flows and engineer efficiency. • Work extensively with CPU micro-architects and Implementation engineers to drive timing closure for the CPU. Minimum Qualifications: Minimum BS and 10+ years of relevant experience Experience with a static timing analysis tool such as PrimeTime® or Tempus® Experience with timing analysis with multiple clock and power domains, noise analysis, and fixing noise in designs Experience with variation modeling

### Director, Material Flow & Continuous Improvement - Pfizer
- Location: Singapore - Tuas (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-20
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://pfizer.wd1.myworkdayjobs.com/PfizerCareers/job/Singapore---Tuas/Director--Material-Flow---Continuous-Improvement_4956602
- Excerpt: Director, Material Flow & Continuous Improvement Singapore - Tuas posted: Posted 23 Days Ago

### Flow Calibration Tech - Baxter International
- Location: Medina, New York (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://baxter.wd1.myworkdayjobs.com/baxter/job/Medina-New-York/Flow-Calibration-Tech_JR-198275-1
- Excerpt: Flow Calibration Tech Medina, New York posted: Posted 30+ Days Ago

### Clinical Laboratory Technologist - Flow Cytometry - Labcorp
- Location: Austin TX (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-21
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://labcorp.wd1.myworkdayjobs.com/External/job/Austin-TX/Clinical-Laboratory-Technologist---Flow-Cytometry_2610003-1
- Excerpt: Clinical Laboratory Technologist - Flow Cytometry Austin TX posted: Posted 22 Days Ago

### Technik ds. Industrializacji - Flow 4 (K/M) - Aptiv
- Location: Gdansk, Poland (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://aptiv.wd5.myworkdayjobs.com/APTIV_CAREERS/job/Gdansk-Poland/F4-Launch-Technician--Auto-assembly-_J000689953
- Excerpt: Technik ds. Industrializacji - Flow 4 (K/M) Gdansk, Poland posted: Posted 30+ Days Ago

### CAD Engineer - PDV - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $147K-$272K
- Posted: 2026-01-29
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200644242/cad-engineer-pdv?team=HRDWR
- Excerpt: CAD Engineer - PDV Austin, United States of America Do you love building elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions! Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices. As a member of our CAD team, you will architect, develop, maintain and improve physical design verification (PDV) flows. The role requires you to work on flow and runset development for various technology nodes and tool sets. Working alongside the CAD team, you will be collaborating with the custom digital/analog/mixed-signal design, physical design (PD) and chip integration teams. With good understanding of design rule checks (DRC) and layout versus schematic (LVS) runsets, you will develop rule decks from scratch and/or modify existing ones. You will also have opportunities to develop ML/LLM based automations and solutions. -Develop, improve and maintain various aspects of physical verification flow and methodology -Coordinate the effort of validating flows, improving for custom checks and data generation -Work with the design and PD teams to facilitate the chip design process -Code custom PDV rule decks such as Electrical rule checks (ERC) and Programmable ERCs -Collaborate

### CAD Engineer - Circuit Simulation Methodology - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $147K-$272K
- Posted: 2026-04-17
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200658203/cad-engineer-circuit-simulation-methodology?team=HRDWR
- Excerpt: CAD Engineer - Circuit Simulation Methodology Austin, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it. As a key member of our best-in-class CAD Group, you will be part of building state of the art designs. We will utilize your hands-on experience in Custom simulation and/or power EM/IR analysis to define, develop and refine the methodologies and flows. In this highly visible role, your primary responsibilities will include - Supporting transistor level simulation solutions that scale with accuracy and capacity challenges - Supporting and enhancing the custom transistor level simulation flows and/or EM/IR flows - Collaborating with various design groups (Physical-design and integration, Circuit-design / Power / Technology) to address their circuit verification requirements across different processes - Partnering with design, CAD and EDA teams to identify flow deficiencies and deliver state of art solutions Minimum Qualifications: Experience with custom design environment and transistor level circuit simulation Proficiency in at least one of the following programming languages: Python, Perl, C/C++ Minimum requirement of BS + 3 years of relevant industry experience

### Materials Flow and Warehouse Operations Lead - Eaton Corporation
- Location: Schrems, Baixa Áustria, AUT, 3943 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://eaton.eightfold.ai/careers/job/687236592147
- Excerpt: Materials Flow and Warehouse Operations Lead Schrems, Baixa Áustria, AUT, 3943

### Assoc Principal Sci, Lab Operations (Flow Cytometry) - IQVIA
- Location: Singapore (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Singapore/Assoc-Principal-Sci--Lab-Operations--Flow-Cytometry-_R1283555-1
- Excerpt: Assoc Principal Sci, Lab Operations (Flow Cytometry) Singapore posted: Posted 30+ Days Ago

### Lab Associate Flow Cytometry - IQVIA
- Location: Valencia, CA, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Valencia-CA-United-States-of-America/Lab-Associate-Flow-Cytometry_R1535921
- Excerpt: Lab Associate Flow Cytometry Valencia, CA, United States of America posted: Posted 3 Days Ago

### Laboratory Associate, Flow Cytometry - IQVIA
- Location: Valencia, CA, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Valencia-CA-United-States-of-America/Laboratory-Associate--Flow-Cytometry_R1545109
- Excerpt: Laboratory Associate, Flow Cytometry Valencia, CA, United States of America posted: Posted 24 Days Ago

### Associate Scientist, Flow Cytometry - IQVIA
- Location: Valencia, CA, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Valencia-CA-United-States-of-America/Associate-Scientist--Flow-Cytometry_R1545116
- Excerpt: Associate Scientist, Flow Cytometry Valencia, CA, United States of America posted: Posted 24 Days Ago

### Flow Cytometry Analyst - Labcorp
- Location: CHE - Geneva - 7 rue Moise-Marcinhes (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-14
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://labcorp.wd1.myworkdayjobs.com/External/job/CHE---Geneva---7-rue-Moise-Marcinhes/Flow-Cytometry-Analyst_2616424
- Excerpt: Flow Cytometry Analyst CHE - Geneva - 7 rue Moise-Marcinhes posted: Posted 29 Days Ago

### Supervisor Flow Cytometry - Labcorp
- Location: CHE - Geneva - 7 rue Moise-Marcinhes (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://labcorp.wd1.myworkdayjobs.com/External/job/CHE---Geneva---7-rue-Moise-Marcinhes/Supervisor-Flow-Cytometry_2619078
- Excerpt: Supervisor Flow Cytometry CHE - Geneva - 7 rue Moise-Marcinhes posted: Posted 8 Days Ago

### Director, Specialist Sales Commercial & New Payment Flows - Mastercard Incorporated
- Location: Shanghai, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://mastercard.wd1.myworkdayjobs.com/CorporateCareers/job/Shanghai-China/Director--Specialist-Sales-Commercial---New-Payment-Flows_R-275964
- Excerpt: Director, Specialist Sales Commercial & New Payment Flows Shanghai, China posted: Posted 30+ Days Ago

### Electrical Engineer - Decatur, IL - Archer Daniels Midland
- Location: Location not specified (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://sjobs.brassring.com/TGnewUI/Search/home/HomeWithPreLoad?partnerid=25416&siteid=5998&PageType=JobDetails&jobid=3354608
- Excerpt: Electrical Engineer - Decatur, IL Electrical Engineer - Decatur, IL This is a permanent, full-time, exempt-level position. Position Summary We are looking for an enthusiastic Electrical Engineer to join our North American Electrical team. In this role, you will support electrical system studies and learn how to analyze power distribution systems. You will gain hands on experience with short-circuit studies, arc flash analysis, load flow, motor starting, and harmonic studies under the guidance of experienced engineers. This is an excellent opportunity for recent graduates to grow technical skills, work on real-world electrical projects, and contribute to safe and reliable plant operations. What You'll Do - Work with senior engineers to review and update single-line diagrams and SKM electrical models - Assist in conducting electrical studies to include load flow, fault current analysis, motor start analysis and Harmonic analysis to evaluate system performance and the impact of changes on system dynamics - Learn how to review arc flash reports and electrical models to ensure compliance with industry standards (IEEE 1584, NFPA 70E) - Support plants in remediating overdutied equipment issues - Help perform load flow and related studies to inform design decisions, guided by IEEE standards - Contribute to maintaining and improving study guidelines and technical manuals - Take part in developing and updating our electrical safety program - Review engineering packages with mentorship to ensure compliance with scope and good engineering practices - Gain experience in guiding contractors and vendors on modeling guidelines and quality expectations Required Qualifications - A

### Marketing Analyst- Flow Cytometry/ Life Sciences - Becton Dickinson
- Location: USA CA - Milpitas 135 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://bdx.wd1.myworkdayjobs.com/EXTERNAL_CAREER_SITE_USA/job/USA-CA---Milpitas-135/Marketing-Analyst--Flow-Cytometry--Life-Sciences_R-544569-1
- Excerpt: Marketing Analyst- Flow Cytometry/ Life Sciences USA CA - Milpitas 135 posted: Posted 8 Days Ago

### Associate Scientist, Lateral Flow - Quidelortho Corp
- Location: US - CA - San Diego - Summers Ridge (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://orthoclinical.wd1.myworkdayjobs.com/Search/job/US---CA---San-Diego---Summers-Ridge/Associate-Scientist_R0016705
- Excerpt: Associate Scientist, Lateral Flow US - CA - San Diego - Summers Ridge posted: Posted 11 Days Ago

### AI Data Engineer - Hewlett Packard Enterprise
- Location: Bengaluru, Karnātaka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-05
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://hpe.wd5.myworkdayjobs.com/Jobsathpe/job/Bengaluru-Karntaka-India/AI-Data-Engineer_1205611-3/apply
- Excerpt: AI Data Engineer Bengaluru, Karnātaka, India We are looking for a technically sharp and detail-oriented Data Engineer to join our team. This role is pivotal in ensuring clean, governed data flows into AI models and dashboards, utilizing tools like Databricks and Power BI. Join us to redefine data engineering!

### Staff Front-End CAD Engineer, Silicon - Google
- Location: San Diego, CA, USA; +1 more (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2Fcken8ij5W_Kh3XMmz1jbl9ZBAN10Fgwmgx7s4lf1nLTATEjsACxwdTKysliKmgKuPRbfirPBZjsSCulpxsZj5NVLyBlA1xStkTzm6szSyNLpdkEd4cPWktNF6SC-Olw%3D%3D_V2&loc=US&title=Staff+Front-End+CAD+Engineer
- Excerpt: Staff Front-End CAD Engineer, Silicon San Diego, CA, USA; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As part of the Front-End CAD team, you will be responsible for developing CAD flows or tools for custom SoCs built for Google made devices. You will have a thorough understanding of very large scale Integration (VLSI) design and software skills and will be able to apply them to meet design goals. You will be working directly with designers to understand their needs and building efficient solutions that scale across multiple projects and nodes. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $192000 - $279000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Develop front-end CAD tools and flows for Google Silicon SoC projects in various domains (RTL generation, design verification, AI-enabled CAD flows, design/IP quality assurance and release management, design spec management, internal CAD tool development, etc.). Work with design teams to understand requirements and enable scalable and efficient CAD solutions to improve design quality and productivity. Work across functional domains to enable development and validation of CAD flows. Drive EDA vendors to improve their tools to deliver custom solutions for Google. Understand

### Director, Risk Management - Commercial & New Payment Flows (CNPF) - Mastercard Incorporated
- Location: London, England (Angel Lane) (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://mastercard.wd1.myworkdayjobs.com/CorporateCareers/job/London-England-Angel-Lane/Director--Risk-Management---Commercial---New-Payment-Flows--CNPF-_R-278305-1
- Excerpt: Director, Risk Management - Commercial & New Payment Flows (CNPF) London, England (Angel Lane) posted: Posted Today

### ASIC Physical Design Tools, Flows, Methodologies Manager - Google
- Location: Sunnyvale, CA, USA (unspecified)
- Salary: $192K-$279K
- Posted: 2026-06-05
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdA65qFUzIMVLO_qpz0DNp3VEGiDi--dD76uednIOm7mEjsACxwdTGTK8Ty7-tc9OpPxcMp3gpC2QfV58Ip69SKMasdvH2uZn6ZCXIhkWceu3r0ksfD-cHEB3yQhqA%3D%3D_V2&loc=US&title=ASIC+Physical+Design+Tools
- Excerpt: ASIC Physical Design Tools, Flows, Methodologies Manager Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will manage and lead a team of TFM engineers responsible for the physical design flows that power our Tensor Processing Unit (TPU) products. You will guide your team in developing, deploying, and supporting a register-transfer level (RTL)-to-GDS infrastructure. You will bridge design engineering and electronic design automation (EDA) capabilities, balancing resources and managing priorities across projects, feature requests, and bug resolutions to ensure silicon delivery. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by

### Timing Design Engineer - Apple
- Location: San Diego, United States of America (unspecified)
- Salary: $172K-$302K
- Posted: 2026-01-22
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200642251/timing-design-engineer?team=HRDWR
- Excerpt: Timing Design Engineer San Diego, United States of America At Apple, we work every single day to craft products that enrich people's lives. Do you love working on challenges that no one has solved yet? Do you like changing the game? We have an opportunity for a results-oriented and outstandingly hardworking Timing Design Engineer. As a member of our multifaceted group, you will have the outstanding and phenomenal opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every day. In this role, you will be at the center of a PHY design effort collaborating with architecture, CAD, logic design teams, with a critical impact on delivering outstanding PHY designs. You will be directly involved in timing closure and/or physical designs of outstanding PHY design As an ASIC STA Engineer, you will have responsibilities spanning all aspects of SoC design in terms of timing. Key responsibilities include timing sign-off, STA and sign-off flow development, ownership of IP and block level timing constraints both for regular and custom timing requirements from synthesis to sign-off to achieve sign-off quality timing constraints. You will closely interact with RTL designer to understand design intent and clock structure, with CAD to understand and develop flow, and with Physical design team to close and sign-off timing. You will also come up with ideas and plans to verify your own timing constraints. You will innovate timing constraints and flow to facilitate timing closure and any potential pessimism or fall outs in timing analysis.

### Operations Manager- Flow Center- Hampton GA - Target Corporation
- Location: 1000 Site Pkwy, Hampton,GA 30228 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-02
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/1000-Site-Pkwy-HamptonGA-30228/Operations-Manager--Flow-Center--Hampton-GA_R0000439720
- Excerpt: Operations Manager- Flow Center- Hampton GA 1000 Site Pkwy, Hampton,GA 30228 posted: Posted 10 Days Ago

### Operations Manager - Flow Center - Mililani, HI - Target Corporation
- Location: 229 Palii St, Mililani,HI 96789 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/229-Palii-St-MililaniHI-96789/Operations-Manager---Flow-Center---Mililani--HI_R0000439171-1
- Excerpt: Operations Manager - Flow Center - Mililani, HI 229 Palii St, Mililani,HI 96789 posted: Posted 17 Days Ago

### Flow Cytometry Sr. Product Manager - Single Colors Reagents and Dyes (d/f/m) - Danaher Corporation
- Location: Paris, France (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-31
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://danaher.wd1.myworkdayjobs.com/DanaherJobs/job/FRA---Remote/Flow-Cytometry-Sr-Product-Manager---Single-Colors-Reagents-and-Dyes--d-f-m-_R1308543/apply
- Excerpt: Flow Cytometry Sr. Product Manager - Single Colors Reagents and Dyes (d/f/m) Paris, France Nous recherchons un Responsable Produit Senior en Cytométrie en Flux pour définir et exécuter la feuille de route stratégique des colorants et réactifs. Ce rôle clé implique la gestion de partenariats OEM et l'analyse de marché pour soutenir la croissance du portefeuille. Rejoignez-nous pour faire une différence dans les sciences de la vie.

### Scientist III (Flow Cytometry Subject Matter Expert) - Thermo Fisher Scientific
- Location: Middleton, Wisconsin, United States of America (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://thermofisher.wd5.myworkdayjobs.com/ThermoFisherCareers/job/Middleton-Wisconsin-USA/Scientist-III--Flow-Cytometry-Subject-Matter-Expert-_R-01348919-1/apply
- Excerpt: Scientist III (Flow Cytometry Subject Matter Expert) Middleton, Wisconsin, United States of America Join us as a Scientist III, Flow Cytometry and lead advanced diagnostic testing, method validation, and quality assurance in a GMP-regulated lab. Mentor junior scientists, drive process improvements, and ensure compliance with industry standards. Make a global impact in clinical research and pharmaceutical innovation with Thermo Fisher Scientific.

### Operations Manager - Flow Center - Chicago, IL - Target Corporation
- Location: 3501 S Pulaski Rd, Chicago,IL 60623-4926 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-18
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/3501-S-Pulaski-Rd-ChicagoIL-60623-4926/Operations-Manager---Flow-Center---Chicago--IL_R0000437906
- Excerpt: Operations Manager - Flow Center - Chicago, IL 3501 S Pulaski Rd, Chicago,IL 60623-4926 posted: Posted 25 Days Ago

### (Sr.) Modeling Engineer - Corning
- Location: Location not specified (unspecified)
- Salary: Not disclosed
- Posted: 2026-02-08
- Parental leave: 12 weeks (not source-backed)
- Non-birth-parent leave: 12 weeks (not source-backed)
- Apply: https://career4.successfactors.com/career?company=CNGPROD&career_ns=job_listing_summary&resultType=XML
- Excerpt: (Sr.) Modeling Engineer Key Responsibilities Performing numerical simulations using in-house coding and Finite Element /Difference Analysis software for designing new manufacturing processes and equipment, or for trouble-shooting existing process upsets. Develop new models or help other engineers develop models if the existing models are insufficient. Apply physical principles to explain data and identify gaps for improving quality or reducing cost. Generate hypothesis to explain the existing gaps in knowledge. Use models or physical tests to confirm or deny hypothesis Collaborate with subject matter experts, division engineers and scientists to facilitate and collect data from plants to develop, calibrate and validate math models Experiences/Education - Required Education: Ph.D. in Mechanical Engineering, Chemical Engineering, Civil Engineering, Engineering Mechanics, Geophysics, Computational Science, or Physics or Masters in above with 3-5 years of experience Required Skills: Strong analytical skills for problem solving Familiar with computational techniques, used in heat transfer, combustion, chemical species, turbulent air flow with species Having a background in tackling complicated problems, defining the underlying physics using fundamental principles and simplifying the problem as much as needed, identifying solution paths, developing solution techniques, and delivering following timeliness Experiences - Desired Familiarity with commercial software such as Fluent/ANSYS, Star CCM+, MATLAB, COMSOL, AUTO CAD, Solid Works, Design Modeler, Gambit/Cubit Familiarity with Linux, C++, Python Familiarity with coupled heat transfer (conduction-convection-radiation)-fluid flow problems. Familiarity with problems related to radiation, surface-to-surface and participating media with discrete oordinates method, Rosseland approximation. Familiarity with turbulent flow in furnaces, burner design and/or analysis. Confidence in dissecting numerical

### Global Logistics Flow Coordinator - Bunge
- Location: Geneve (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- Parental leave: 6 weeks (not source-backed)
- Non-birth-parent leave: 6 weeks (not source-backed)
- Apply: https://jobs.bunge.com/job/Gen%C3%A8ve-Global-Logistics-Flow-Coordinator-Gene-1206/1390001033/
- Excerpt: Global Logistics Flow Coordinator Geneve Requisition Number: 45038 Global Logistics Flow Coordinator Location: Geneva, Switzerland Play a key role in global trade & logistics Are you curious about how commodities move across the world? Do you enjoy working in dynamic environments where decisions have real commercial impact? As a Global Logistics Flow Coordinator, you will operate at the intersection of trading, freight and supply chain, helping to translate trading strategies into efficient, real‑world ocean flows. This role offers broad exposure to global logistics, commercial decision‑making and international stakeholder collaboration. Your role You will support the planning, coordination and execution of ocean flows across commodities such as beans, meals and oils. Working closely with logistics managers, traders and operational teams around the globe, you will help ensure smooth and optimized port‑to‑port execution. Supply Chain & Logistics Optimization Contribute to Value Chain Supply Chain cost optimization & trading book value maximization Translate trading strategies into efficient supply chain plans Lead the planning and coordination of port‑to‑port ocean shipments, ensuring internal & external contractual commitments Build a strong understanding of how trading, freight and supply chains interact across the value chain Monitor seaflow shipments & cope with ongoing changes Track vessel movements, port activity and logistics plan fulfilment Adjust plans across time zones as situations evolve Support the handl

### Operations Manager - Flow Center - Riverside, California - Target Corporation
- Location: 23000 Van Buren Blvd, Riverside,CA 92518-2401 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-18
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/23000-Van-Buren-Blvd-RiversideCA-92518-2401/Operations-Manager---Flow-Center---Riverside--California_R0000439408-1
- Excerpt: Operations Manager - Flow Center - Riverside, California 23000 Van Buren Blvd, Riverside,CA 92518-2401 posted: Posted 25 Days Ago

### Human Resource Business Partner- Flow Center - Hampton, GA - Target Corporation
- Location: 1000 Site Pkwy, Hampton,GA 30228 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-07
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/1000-Site-Pkwy-HamptonGA-30228/Human-Resource-Business-Partner--Sortation-Center---Hampton--GA_R0000441116
- Excerpt: Human Resource Business Partner- Flow Center - Hampton, GA 1000 Site Pkwy, Hampton,GA 30228 posted: Posted 5 Days Ago

### Supply Chain Safety Manager - Flow Center - Chicago, IL - Target Corporation
- Location: 3501 S Pulaski Rd, Chicago,IL 60623-4926 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/3501-S-Pulaski-Rd-ChicagoIL-60623-4926/Supply-Chain-Safety-Manager---Flow-Center---Chicago--IL_R0000439838-1
- Excerpt: Supply Chain Safety Manager - Flow Center - Chicago, IL 3501 S Pulaski Rd, Chicago,IL 60623-4926 posted: Posted Today

### CAD Gate-level 3DIC EM/IR Engineer - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $147K-$272K
- Posted: 2026-04-14
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200657801/cad-gate-level-3dic-em-ir-engineer?team=HRDWR
- Excerpt: CAD Gate-level 3DIC EM/IR Engineer Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming phenomenal products very quickly. Do you want to bring passion and dedication to your job? There's no telling what you could accomplish at Apple. The people who work here have reinvented entire industries with Apple Hardware products. The same real passion for innovation that goes into our products also applies to our practices - we continue to strengthen our commitment to leave the world better than we found it! As a key member of our best-in-class CAD Group, you will be part of building innovative designs. We will apply your hands-on experience in power EM/IR analysis to develop, define and refine the methodologies and flows for gate-level, as well as transistor level designs. Major tasks will include functional static / dynamic IR analysis, scan mode IVD analysis, package and interposer model handling, 3DIC and multi die analysis, power EM analysis, SigEM, power switch modeling, design abstract and reuse for EM/IR purposes, IP / SoC level EMIR sign-off / ECO, and much more. Are you ready to join some of the world's leading engineers, and help us deliver the next generation of ground-breaking Apple products? In this highly visible role, your primary responsibilities will include: - Development of custom EM/IR solutions which scale with accuracy and capacity challenges. - Streamline and automate EM/IR flow with ownership of the entire flow. - Support and collaborate with design

### Human Resource Business Partner- Flow Center - Chicago, IL - Target Corporation
- Location: 3501 S Pulaski Rd, Chicago,IL 60623-4926 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/3501-S-Pulaski-Rd-ChicagoIL-60623-4926/Human-Resource-Business-Partner--Flow-Center---Chicago--IL_R0000440024
- Excerpt: Human Resource Business Partner- Flow Center - Chicago, IL 3501 S Pulaski Rd, Chicago,IL 60623-4926 posted: Posted 15 Days Ago

### Analog Simulation/Env Automation CAD Engineer - Apple
- Location: Austin, United States of America (unspecified)
- Salary: $181K-$318K
- Posted: 2026-04-08
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200656322/analog-simulation-env-automation-cad-engineer?team=HRDWR
- Excerpt: Analog Simulation/Env Automation CAD Engineer Austin, United States of America Interested in how Apple designs the world's most advanced silicon? Want to write software that helps create the next generation of processors and enables the next astonishing Apple innovation? There's no telling what you could accomplish at Apple! We're looking for an engineer who will bring passion for hardware and strong programming skills to our team of CAD engineers. You'll develop, maintain and enhance custom analog power intent methodology and circuit ERC solutions for transistor level analysis on Analog, RF and mixed-signal designs. In this role, you will have the opportunity to directly influence the circuit design on various technology nodes and develop CAD flows for analog circuit SPICE simulation, netlist, design environment, and analyze waveforms, results data processing. Your contributions will be instrumental in the analog, mixed-signal, and RF circuit design teams. You will lead and oversee efforts in developing and validating custom SPICE simulation flows, enhancing the custom design environment, and conducting results analysis. As you collaborate with layout design, technology, and third-party EDA tool vendors, your expertise will be invaluable in driving innovation and ensuring the success of these initiatives. In this highly visible role, your primary responsibilities will include: Solving issues related to transistor level simulations on Analog, RF and Microwave applications with Spice simulators on command-line and Virtuoso environment. Guide and assist designers in solving tool issues related to Analog Design Environment (ADE/XL, Maestro, OCEAN etc.) and develop automation flows. Steer Methodology on SPICE simulation

### Memory CAD Engineer - Cisco
- Location: Zhubei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-07
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/ASIC-Engineer_2012355
- Excerpt: Memory CAD Engineer Zhubei, Taiwan Who You'll Work With Join the Cisco Silicon One team in developing essential building blocks for web-scale and service provider networks. Our SRAM / TCAM design team unites a circuit architect, circuit designer, CAD engineer, and manager, each bringing specialized expertise to create advanced memory solutions. We focus on technical excellence, streamlined processes, and open collaboration to deliver robust SRAM / TCAM designs and meet ambitious project goals. Committed to innovation and teamwork, we tackle complex challenges and drive the future of memory technology together. What You'll Do IP Modeling Automation: Develop and maintain automation flows for generating and validating various IP models (e.g., Behavioral/Liberty/Redhawk...) Tcl Scripting: Utilize Tcl for integration with EDA tools to build flow for IP characterization, qualification, and behavioral verification. Assist RD in integrating macro GDS and Netlists, troubleshooting and resolving EDA-related issues during IP development Who You Are * Minimum Qualifications 5 years of relevant experience with MS/BS in Electrical Engineering, Computer Science, or related fields. Tcl & Shell Mastery: Tcl scripting skills for complex string parsing and EDA tool API manipulation; proficient in Linux Shell environments. Experience in Verilog, specifically in behavioral modeling Environment Management: Build efficient IP delivery and regression environments under Linux Strong documentation and communication skills in Chinese and English *Preferred Qualifications Experience with memory IP CAD flow development Experience in EDA tool (e.g. CustomSim/StarRC/ICV/Virtuoso/Totem) Python/Perl scripting skills is a plus We do not discriminate on the basis of race, religion, color, national origin, gender, sexual

### Lead Physical Design Engineer - Rambus INC
- Location: Bangalore, KA, IN (unspecified)
- Salary: Not disclosed
- Posted: 2025-12-10
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://careers-rambus.icims.com/jobs/22449/lead-physical-design-engineer/job
- Excerpt: Lead Physical Design Engineer Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional Lead Physical Design Engineer to join our MIC team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Complete ownership of Physical Design activities from Floorplan to GDS including PnR,STA,Physical Verification, Take complete ownership for implementation of both Top/Block level designs. Responsible for independent planning and execution of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, IP integration, extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out on 28nm nodes or below. Must have participated in all stages of the design. (floor planning, placement, CTS, routing, crosstalk avoidance, physical verification, IREM, Timing Closure, constraint (sdc) development) Well versed with the block and chip level timing closure (STA) and timing closure methodologies. Also need to have experience with constraints development. Experience in Hierarchical and Flat timing flow bring-up and timing analysis on interface paths. Block level/Fullchip/SOC level/Mixed signal timing path analysis and fixing. Must have knowledge of low power design. (cpf, upf CLP). Should be able to provide clear directions to the team on various implementation and signoff flows Should be well versed in LEC flow and debugging issues independently. Role involves tasks in estimating power using industry standard tool

### WSoC RF Test Automation Engineer - Apple
- Location: Los Angeles Metro Area, United States of America (unspecified)
- Salary: $120K-$210K
- Posted: 2026-04-25
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.apple.com/en-us/details/200630214/wsoc-rf-test-automation-engineer?team=HRDWR
- Excerpt: WSoC RF Test Automation Engineer Los Angeles Metro Area, United States of America Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. In this role, you will focus on delivering the automation frameworks used by Wireless SoC RF integration and validation team. You will architect and implement the automation framework for WSoC RF characterization and regression. You will get the opportunity to keep developing your technical skillsets in both HW and SW domains such as, understanding of wireless transceiver architecture, RF system and DSP knowledge, Software framework, RF driver and embedded system, and experience of delivery Apple products until productization. Capture requirements, architect, and implement and maintain the test automation framework covering the wireless SoC RF test flow. Develop SW routines for automating test equipment control, and data acquisition and processing. Enhance existing FW/SW regression framework and maintain it. Develop flow to manipulate data from database to data Viz. Develop automation infrastructure for GIT - CI/CD. Automate repetitive measurements using standard scripting languages (Python). Continually work to improve testing speed, coverage and accuracy. Familiar with RF Driver/FW development flow. Minimum Qualifications: Minimum requirement of a bachelors degree

### Senior AI Engineer - Danaher Corporation
- Location: Shanghai, Shanghai, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-09
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://app.mokahr.com/ex-web/danaher_com/main/careersite?reqId=R1310277
- Excerpt: Senior AI Engineer Shanghai, Shanghai, China Join our team as a Senior AI Engineer and drive the future of AI strategy at Beckman Coulter Life Sciences. Lead AI roadmap, collaborate with global teams, and shape innovative solutions for automation, flow cytometry, and more. Make a real impact by integrating cutting-edge AI capabilities to transform science and technology.

### Logistics Yard Operations Manager - Flow Center - Riverside, California - Target Corporation
- Location: 23000 Van Buren Blvd, Riverside,CA 92518-2401 (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/23000-Van-Buren-Blvd-RiversideCA-92518-2401/Logistics-Yard-Operations-Manager---Flow-Center---Riverside--California_R0000439730
- Excerpt: Logistics Yard Operations Manager - Flow Center - Riverside, California 23000 Van Buren Blvd, Riverside,CA 92518-2401 posted: Posted 17 Days Ago

### Quantitative Model Analyst – Cash Flow Modeling - U.S. Bancorp
- Location: Minneapolis, MN, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://usbank.wd1.myworkdayjobs.com/US_Bank_Careers/job/Minneapolis-MN/Quantitative-Model-Analyst_2026-0010277/apply
- Excerpt: Quantitative Model Analyst – Cash Flow Modeling Minneapolis, MN, United States At U.S. Bank, we're on a journey to do our best. Helping the customers and businesses we serve to make better and smarter financial decisions and enabling the communities we support to grow and succe

### Senior Operations Manager - Flow Center - Logan Township, NJ - Target Corporation
- Location: 300 Creekview Ave, Bldg H, Logan Township,NJ 08085-2597 (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://target.wd5.myworkdayjobs.com/targetcareers/job/300-Creekview-Ave-Bldg-H-Logan-TownshipNJ-08085-2597/Senior-Operations-Manager---Flow-Center---Logan-Township--NJ_R0000435566
- Excerpt: Senior Operations Manager - Flow Center - Logan Township, NJ 300 Creekview Ave, Bldg H, Logan Township,NJ 08085-2597 posted: Posted 4 Days Ago

### Technical Leader DFT & STA - Cisco
- Location: Armenia (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/Engineering-Technical-Leader_2006611
- Excerpt: Technical Leader DFT & STA Armenia Meet the team Join the Silicon One Team at Cisco, a group at the forefront of developing Cisco's groundbreaking silicon architecture. We are a collaborative unit focused on pushing the boundaries of ASIC design for advanced process nodes. As part of our team, you will contribute to defining innovative Physical Design methodologies and creating robust flows essential for developing our complex chips. You will also have the opportunity to work hands-on with the Physical Design of intricate chip partitions. Your Impact You are a detail-oriented DFT Timing Engineer with strong analytical skills and a deep understanding of timing constraints, such as clock groups, various exceptions, clock exclusivity. You will collaborate effectively with cross-functional teams, communicate complex timing data clearly. Responsibilities will include: Developing timing constraints at block, sub-chip, and full-chip levels in test modes, performing quality checks such as duplicated constraints, promotion/demotion between block and top level SDCs. Check timing for unconstrained endpoints, no clock, etc. Your role may include SDC validation, CDC delay check, and SDC flow development. Developing methodologies, guidelines, and checklists to streamline STA work, resolve design and flow issues, and drive execution to ensure progress and accuracy. Minimum Qualifications Bachelor's degree in electrical or computer engineering (or other equivalent field) with 8+ years of related work experience. Experience with block/full chip SDC development in test modes (scan shift, scan capture, atpg capture modes). Expertise in Static Timing Analysis and prior working experience with STA tools like PrimeTime. Programming skills in

### Electro-Mechanical Repair Technician - Ametek
- Location: Work Location (Country) United States | Remote/Onsite Onsite (remote)
- Salary: Not disclosed
- Posted: 2026-06-12
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://jobs.ametek.com/job/Chandler-Electro-Mechanical-Repair-Technician-AZ-85225/1374684400/
- Excerpt: Electro-Mechanical Repair Technician Work Location (Country) United States | Remote/Onsite Onsite The Electro-Mechanical Repair Technician position consists of reading and interpreting work instruction and drawings, maintaining safety and quality standards. The job requires proficiency in hand tools, digital measurement tools, conducting tests, and troubleshooting. Additionally, set-up and calibration of moisture analyzers and toxic gas analyzers. ESSENTIAL DUTIES AND RESPONSIBILITIES: Disassembling/reassembling Cleaning/Repairing Setting up Troubleshooting: Electronic problems to board level Pressure, flow, and leaks Solder components to circuit boards efficiently Assembly and calibration of gold film sensors Operating: Multimeters to read voltage and resistance Digital Flow Meters to read movement of air flow Reading, following, and submitting corrections for work instructions Safety: Electrical SDS PPE Capturing, evaluating, and recording test results Interpret schematics & wiring diagrams Logical progression of Repair, Calibration, and Verification for Laboratory Instruments in an ISO 9001 environment Daily use of an ERP (Enterprise Resource Planning system) REQUIRED EDUCATION AND EXPERIENCE: Associates degree or equivalent in Electrical & Electronics Engineering Technology (or a related technical field). 1-3 years of experience. Proven experience in an electronics repair and manufacturing environment. Strong knowledge of safety protocols and procedures. Excellent communication skills. Ability to navigate ERP systems. Attention to detail and commitment to quality. Str

### SoC Test Engineer Lead, Google Cloud - Google
- Location: Tel Aviv, Israel; +1 more (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-27
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckduLQ1SQsFfo583lbgjVz4DpVpQYGyQT-dqmOaeLwkb7EjsACxwdTLIL7lFVPAPcxNrVIYL7H84w3UOc_1nJ_kE9d0kasHqBshHnt2vLyZ7zrccxmk85GkXR8oyW9A%3D%3D_V2&loc=IL&title=SoC+Test+Engineer+Lead
- Excerpt: SoC Test Engineer Lead, Google Cloud Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's data centers are the most advanced in the world. In this role, you will help to manufacture the SoC's that power these data centers by developing and deploying comprehensive manufacturing test and data analytics solutions for high volume manufacturing at wafer fabs and Outsourced Semiconductor Assembly and Tests (OSAT's). You will have an opportunity to create silicon in the most advanced technologies and follow it into the field to close the loop back to design and test for the next generation of chips. You'll help to integrate SoC technologies into devices and drive manufacturing test flows to assure performance and screen devices. You will drive yield improvement, cost optimization and work closely with cross-functional teams to ensure the optimal test coverage in production to ensure high quality SoCs. You will need to have a strong understanding of IC flows, wafer processing, testing, qualification, diagnostics, and failure analysis. You will work with various groups to deploy screening methodologies and flows for data processing, analytics and diagnostics. You will drive the release of cost effective production test solutions into mass production to hit yield and quality goals. The AI and Infrastructure team is

### Senior Product Order Engineer - Emerson Electric
- Location: CHENNAI, TAMIL NADU, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-11
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_I_2024_Latest.zip
- Apply: https://hdjq.fa.us2.oraclecloud.com/hcmUI/CandidateExperience/en/sites/CX_1/requisitions/job/26005372
- Excerpt: Senior Product Order Engineer CHENNAI, TAMIL NADU, India If you are looking for an opportunity in the Bill of Materials team called Order Engineering, Emerson has this exciting role for you! The Senior Product Order Engineer II is based in FCEC Chennai, India, and will provide technical and order engineering support for all the Emerson Flow Control products to meet customer requirements. We value autonomy, self-reliance, fast movers, a passion for robust and maintainable tests, and the ability to ship a quality product.

### Full Chip Front-End DFT Engineer - Google
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-04
- Parental leave: 18 weeks (not source-backed)
- Non-birth-parent leave: 18 weeks (not source-backed)
- 401(k) match: listed (source-backed)
  - Source: https://www.askebsa.dol.gov/FOIA%20Files/2024/Latest/F_SCH_H_2024_Latest.zip
- Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckQmkGMNxEOLf5fszHuCRgysyUDjQcfqY4byMnLQI2BgXEjsACxwdTPQB1LJ0MmFugAgDm9vsquT2hri_nGQRdGkdTdujyF3UPmYh2_ryhsz6eTBASkWhAUbnXCgIow%3D%3D_V2&loc=IN&title=Full+Chip+Front-End+DFT+Engineer
- Excerpt: Full Chip Front-End DFT Engineer Bengaluru, Karnataka, India Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Define and document the Design for Testability (DFT) architecture for multi-core System on Chips (SoCs), including strategies for hierarchical scan compression, MBIST (Memory BIST), Logic BIST and Analog Mixed Signal circuits. Implement DFT logic, boundary scan, MBIST, scan chains, DFT compression, Clock Control block, and other DFT Internet Protocol (IP) blocks. Work with the Register Transfer Level (RTL) and Physical Design (PD) team at SoC level, and with the subsystem DFT teams. Write scripts to automate the DFT flow. Develop tests that can be used for Production in the Automatic Test Equipment (ATE) flow. Minimum qualifications: Bachelor's degree in Science or Electrical or Electronics Engineering or a related technical field or equivalent practical experience. 5 years of experience with ATPG, Low Power designs, Built-In Self-Test (BIST), Joint Test Action Group (JTAG), Internal JTAG (IJTAG) tools and flow. 3

---
Source-backed benefit claims include source links; other benefit values are labeled separately.