# FewerJobs export - 100 curated jobs
Generated: 2026-06-14T19:50:33.619Z
Source: https://fewerjobs.com

## Filters applied
- **q**: Astera Labs
- **quality_floor**: default
- **match_401k_strict**: true
- **parental_strict**: true
- **non_birth_strict**: true
- **pto_strict**: true
- **include_older**: false
- **apply_url_verified**: false
- **page**: 1
- **per_page**: 100
- **sort**: relevance

## Jobs
### Senior Business Systems Analyst - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702305005
- Excerpt: Senior Business Systems Analyst San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support next-generation workloads. Our portfolio spans high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. We are committed to open standards, continuous innovation, and building a collaborative environment to solve complex challenges at scale. Role Overview Astera Labs is seeking a hands-on Senior Business System Analyst to own and scale our CRM and business operations systems. This role is responsible for system administration, workflow automation, integrations, and continuous enhancements to support Sales, Operations, Finance, Product, and IT teams. In addition to core Salesforce platform

### Senior Firmware Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $160K-$195K
- Posted: 2026-05-30
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701247005
- Excerpt: Senior Firmware Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Astera Labs is seeking a Senior Firmware Engineer to develop and deliver core firmware for our next-generation connectivity, chiplet, and system products. Firmware is a core differentiator for Astera Labs' products and is treated as a first-class engineering discipline, on par with hardware and silicon design. Key Responsibilities - Architect, develop, and maintain bare-metal and low-level firmware running on embedded microcontrollers within Astera Labs SoCs and systems. - Design and implement device drivers, core firmware services, and hardware abstraction layers for high-speed connectivity products. - Define and implement HW-SW interfaces in close collaboration with RTL, PD, and Architecture teams. - Lead bring-up, debug, and validation of firmware on silicon and system platforms. - Develop and maintain C/C++ firmware codebases, SDKs, and supporting infrastructure. - Build automation, tooling, and diagnostics using Python and scripting frameworks. - Participate in system-level debug involving PCIe, Ethernet, memory subsystems, and interconnect fabrics. -

### Hardware Lab Technician - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $135K-$165K
- Posted: 2026-04-08
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674410005
- Excerpt: Hardware Lab Technician San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Astera Labs Inc. is seeking a proactive and self-driven Hardware Lab Technician to join our team in developing world class connectivity products for AI infrastructure. Job Description This role works closely with various teams within our lab, including SI/PI, validation, design, NPI, and more. You will also be responsible for organizing and managing an inventory of consumables and peripherals while providing comprehensive support for lab infrastructure and daily operations. The ideal candidate will have hands-on technical skills, a strong work ethic, and the ability to manage various responsibilities in a fast-paced, collaborative environment. Key Responsibilities - Operate a manual probe station (MPI TS600-PCB) to probe printed circuit boards and components - Perform DC and signal integrity measurements on PCBs and evaluation hardware - Manage critical inventories of Astera products, tools, consumables, and peripherals, including purchasing, organizing, monitoring, and forecasting - Assemble, inspect, and test modules/subassemblies - Optimize and

### Senior Pricing Manager - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702286005
- Excerpt: Senior Pricing Manager San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs (NASDAQ: ALAB) is a pioneering fabless semiconductor company headquartered in Silicon Valley, driving the evolution of AI and cloud infrastructure through purpose-built connectivity solutions. As a leader in rack-scale architecture, Astera Labs is enabling the shift to AI Infrastructure 2.0, where compute is optimized at the rack level to support next-generation workloads. Our portfolio spans high-performance silicon, software, and system-level solutions that address critical bottlenecks in data movement across compute, memory, and networking domains. We are committed to open standards, continuous innovation, and building a collaborative environment to solve complex challenges at scale. Role Overview Astera Labs is seeking a Senior Pricing Manager to lead pricing strategy, governance, and execution across our product portfolio. This role will define how we price products and solutions, improve revenue and margin outcomes, and influence cross-functional decision-making through market insight, analytics, and commercial leadership. The ideal candidate brings

### Distinguished Formal Verification - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $230K-$285K
- Posted: 2026-02-23
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4664853005
- Excerpt: Distinguished Formal Verification San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Distinguished Engineer, Formal Verification to join our world-class engineering team in San Jose, California. As a hyper-growth leader in AI infrastructure connectivity, we're revolutionizing how data centers handle explosive AI workloads through cutting-edge PCIe Gen 6/7, CXL, Ethernet, UCIe, and UALink technologies. This is a rare opportunity to shape the formal verification strategy across our entire product portfolio while working on the most advanced connectivity solutions powering the AI revolution. In this highly strategic role, you'll serve as Astera Labs' technical authority on formal verification, defining methodologies and best practices that ensure the highest quality standards across all our next-generation connectivity products. You'll work at the intersection of innovation and reliability, leading efforts to catch critical corner-case bugs that traditional verification methods miss, while mentoring a global team of engineers and representing Astera Labs as a thought leader in the formal verification community. This position offers

### System Validation Engineering Director - Astera Labs
- Location: Vancouver, British Columbia, Canada (unspecified)
- Salary: $200K-$250K
- Posted: 2026-03-11
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4671898005
- Excerpt: System Validation Engineering Director Vancouver, British Columbia, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking an exceptional Director of System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs' fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. Job Description - Seeking a strong technical leader who has delivered multiple SoC products. - Lead and scale the system validation organization for Astera Labs'

### Principal Engineer, Ecosystem Partnership & Marketing - Astera Labs
- Location: Shanghai, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-05
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4667065005
- Excerpt: Principal Engineer, Ecosystem Partnership & Marketing Shanghai, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Engineer, Ecosystem Partnership & Marketing - Asia Region Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Learn more at www.asteralabs.com . Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced Principal Ecosystem Partnership & Marketing Manager drive business growth, product adoption, and ecosystem innovation across

### Senior Diagnostic Platform Software Engineer - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-14
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695219005
- Excerpt: Senior Diagnostic Platform Software Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions grounded in open standards. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. Discover more at www.asteralabs.com . Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on project from conception to the final production stage at contract manufacturer. The role requires strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in

### Firmware QA Manager - Astera Labs
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695019005
- Excerpt: Firmware QA Manager Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Title : Lead Firmware QA Engineer , A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Software QA Manager for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Basic Qualifications : - Bachelor's degree in electrical engineering (EE) or Computer Science is required; a master's or PhD in EE is preferred with minimum 15 years of experience. Required Experience : - Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol. - Estimate work, identify dependencies and develop schedules. - Responsible for designing and executing functional, performance, interoperability and stress tests. - Work closely with Silicon team, architecture team, FW development team to understand the design and

### System Validation Engineer (Various Levels) - Astera Labs
- Location: Vancouver, BC, Canada (unspecified)
- Salary: $125K-$290K
- Posted: 2026-03-11
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4671900005
- Excerpt: System Validation Engineer (Various Levels) Vancouver, BC, Canada Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking System Validation Engineers across multiple levels to lead post‑silicon bring‑up and system validation for high‑performance PCIe and CXL memory expansion products used in AI and cloud data centers. You will design and execute validation plans, automate data‑centric test flows, drive root‑cause investigations across silicon, firmware, hardware, and systems, and work directly with customers to validate real world performance and interoperability. This role is based in our Vancouver office , which is a strategic growth hub for Astera Labs' validation team. You'll have the opportunity to be a foundational member of this expanding site while collaborating closely with our core team in San Jose. This is a unique chance to help shape the team's culture, processes, and technical direction as we scale our validation capabilities to meet surging demand for AI infrastructure connectivity. What Success Looks Like: - New silicon and platforms brought up

### Principal Product Applications Engineer - Astera Labs
- Location: Shanghai, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-05
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4655275005
- Excerpt: Principal Product Applications Engineer Shanghai, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of cloud and AI infrastructure. Our Intelligent Connectivity Platform integrates PCIe, CXL and Ethernet semiconductor-based solutions based on a software-defined architecture that is both scalable and customizable. Inspired by trusted partnerships with hyperscalers and the data center ecosystem, we are an innovation leader with products that are flexible, interoperable, and reliable. We are headquartered in the heart of California's Silicon Valley, with R&D centers and offices in Texas, Taiwan, China, Canada, and Israel. As an Astera Labs Product Applications Engineer, you will be part of a team that supports design-in of Astera Labs' portfolio of connectivity products by the world's leading cloud service providers and server and network OEMs. In this role, you will need to provide technical guidance to customers to overcome design challenges, generate collateral for existing and new products, and drive innovation by

### Principal Optical Module Validation Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $160K-$240K
- Posted: 2026-05-21
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4697341005
- Excerpt: Principal Optical Module Validation Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview As a Principal Optical Module Validation Engineer at Astera Labs, you will be working alongside many functions in the company, from Marketing to Engineering, Validation and Applications. You will be responsible for validating optical systems that incorporate Astera Labs' diverse range of connectivity and memory products that are widely used by leading cloud service providers, server manufacturers, and network OEMs. You will be involved in every stage of design, from concept, test, to mass production. In addition to your core responsibilities, you will have the opportunity to drive innovation within the organization by providing insightful feedback to internal teams. Your expertise and suggestions will contribute to the continuous improvement of our products and processes. You may also collaborate on or even lead activities that are closely related, such as manufacturing, customer engagement, and post-production support. We are looking for an ideal candidate who brings industry

### Field Quality Engineer Intern - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-10
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4670943005
- Excerpt: Field Quality Engineer Intern Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is a global leader in purpose-built connectivity solutions that unlock the full potential of AI and cloud infrastructure. Our Intelligent Connectivity Platform integrates PCIe®, CXL®, and Ethernet semiconductor-based solutions and the COSMOS software suite of system management and optimization tools to deliver a software-defined architecture that is both scalable and customizable. Inspired by trusted relationships with hyperscalers and the data center ecosystem, we are an innovation leader delivering products that are flexible and interoperable. Discover how we are transforming modern data-driven applications at www.asteralabs.com. Job Summary We are seeking a student intern to drive product quality improvements across both Astera Lab's semiconductor and board-level products. In this role, the candidate will perform failure analysis for customer returns. The candidate will also compile 8D reports to communicate the analysis findings to the customers. Key Responsibilities · Perform system-level test for the customer returns on a bench in the lab. ·

### Product Integration, Senior Principal - Active Electric Cable / Smart Cable Module Business - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4704545005
- Excerpt: Product Integration, Senior Principal - Active Electric Cable / Smart Cable Module Business San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume - and as OEM customers increasingly adopt Astera Labs silicon into their own designs - we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success. We are hiring a Senior Principal Engineer, AEC Product Integration to serve as the senior technical integration leader for Astera Labs' Active Electrical Cable product line. This is a deeply technical, hands-on individual contributor role at the most senior level - responsible for ensuring that every element of an AEC product

### Principal Field Applications Engineer - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4696806005
- Excerpt: Principal Field Applications Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Principal Field Applications Engineer, you will support the world's leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs' portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer. Basic qualifications: - BS in electrical engineering. Master's degree in engineering is preferred. - Minimum of 8 years' experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications. - Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites

### Director of System Validation Engineering - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: Not disclosed
- Posted: 2025-09-25
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4612429005
- Excerpt: Director of System Validation Engineering San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs' firmware and software are critical differentiators that have helped us win business across all CSPs and hyperscalers. We are seeking a Director of System Validation Engineering to build and scale our system validation organization, ensuring our products meet the performance, reliability, and interoperability demands of next-generation AI and data center systems. Job Description - Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. - Own the development of a comprehensive validation plan and drive its execution. Devise test automation of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior and report results and specification compliance. - Engage with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions. Basic Qualifications -

### Field Application Engineering Intern - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-06
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4670627005
- Excerpt: Field Application Engineering Intern Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking highly motivated Interns to join Field Application Engineering team in their Taipei, Taiwan. As an FAE, you will work to establish the team as trusted technical advisors to the world's leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs' portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer. If you are: - A Junior going into Senior year or Senior graduating by the end of this year - Have strong in academics and technical background in Electrical Engineering - Someone with professional attitude, ability to

### Principal Supplier Quality Engineer - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-15
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4649978005
- Excerpt: Principal Supplier Quality Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com. Job Description: We are seeking an experienced leader to drive Supplier / Manufacturing Quality Engineering to anchor our global supplier quality efforts across both Astera Lab's semiconductor and board-level products. In this role, candidates will drive leading supplier quality across key manufacturing partners including IC fabs, OSAT's, and PCB/PCBA vendors. A strong foundation in supplier quality engineering, uniquely paired

### Senior Director System Validation Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $240K-$300K
- Posted: 2026-02-21
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4661550005
- Excerpt: Senior Director System Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking an exceptional Senior Director System Validation to lead our AI Fabric Validation organization. Connectivity is a critical component of every AI accelerator deployment and hyperscale data center architecture. As part of the AI Fabric Engineering group, you will play a key role in ensuring that Astera Labs' fabric solutions perform at scale and deliver system-level performance across the most demanding AI and ML workloads. This role offers a unique opportunity to shape validation strategy for cutting-edge connectivity silicon and gain deep insight into next-generation AI infrastructure platforms. Your primary responsibility will be to build and lead a world-class validation organization tasked with validating all silicon, firmware, and system-level solutions at scale, ensuring performance, reliability, and production readiness across customer deployments. Job Description - Seeking a strong technical leader who has delivered multiple SoC products. - Lead and scale the system validation organization for Astera Labs'

### Field Applications Engineer - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674945005
- Excerpt: Field Applications Engineer Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Principal Field Applications Engineer, you will support the world's leading cloud service providers, server and network OEMs by working with them to design solutions that use Astera Labs' portfolio of connectivity products. In this role, you will need to identify and understand customer requirements, propose Astera Labs solutions that provide clear value to the customer and provide hands-on design-in support. You will drive innovation by listening to the customer requirements, working with our engineering teams to implement into the product roadmap and delivering the results back to the customer. Basic qualifications: - BS in electrical engineering. Master's degree in engineering is preferred. - Minimum of 8 years' experience working with Cloud service providers and server OEM customers to design in complex SoC/silicon products for Server, Storage, and/or Networking applications. - Customer-oriented, Goal-driven, Self-motivated, be able to work independently and be able to travel frequently to customer sites -

### Senior Principal Product Manager - Cosmos - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-28
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4699876005
- Excerpt: Senior Principal Product Manager - Cosmos San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Senior Principal Product Manager to lead the strategic direction and execution of a unified management and configuration suite that sits at the critical interface between host software, firmware, and silicon across our entire portfolio of connectivity products. This is not a traditional software PM role - it requires deep technical fluency in how software communicates with and runs on chips, how firmware orchestrates silicon behavior, and how all of it comes together inside modern AI server platforms. As the owner of the product roadmap, you will drive standardization of the full-stack software and firmware experience across all Astera products, ensuring that every touchpoint - from chip-level firmware execution to the host drivers and management tools running on the server - delivers a cohesive, powerful, and scalable experience for hyperscaler and enterprise customers. This role sits at the heart of Astera's hyper-growth

### Open Application - Join Our Talent Network! - Astera Labs
- Location: Multiple Locations (unspecified)
- Salary: Not disclosed
- Posted: 2025-07-15
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4586713005
- Excerpt: Open Application - Join Our Talent Network! Multiple Locations Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Why Apply Now? Even if there's no active posting for your expertise, we're always on the lookout for exceptional talent to join our future product and team innovations. We are considering resume of all levels. - Early connection: Be on our radar for upcoming openings that match your skills - Show your passion: Tell us how you can contribute to enterprise‑scale AI connectivity - Stay informed: Receive priority updates on relevant job opportunities at Astera Labs Who We Want to Meet We welcome professionals across disciplines, including but not limited to: - Hardware Engineering (ASIC, mixed‑signal, PCB) - Firmware & Embedded Systems (CXL, PCIe, DDR) - Software & Validation (Firmware QA, system validation, diagnostic SW) - Product & Program Management - Operations & HR - Sales, Customer Programs, and Field Applications Astera Labs champions diversity in technical expertise and career stages from senior engineers and managers to internship

### Hardware Design Engineering, Senior Director - Active Electric Cable / Smart Cable Module Business - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702153005
- Excerpt: Hardware Design Engineering, Senior Director - Active Electric Cable / Smart Cable Module Business San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our product portfolio expands in complexity, performance, and volume - and as OEM customers increasingly adopt Astera Labs silicon into their own designs - we need a senior engineering leader to build and scale the hardware design engineering organization that creates industry-defining products and enables our customers' success. About the Role We are hiring a Senior Director, Hardware Design Engineering to lead and scale Astera Labs' hardware design engineering organization across Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms (SVB/EVB), rack-scale products, and OEM/customer design enablement. This is a senior leadership role with full ownership

### Product Quality Engineer (NCG) - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $120K-$140K
- Posted: 2026-05-13
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695147005
- Excerpt: Product Quality Engineer (NCG) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Quality Engineer to join our Product Quality Engineering team in San Jose, CA. This is an exciting opportunity for an early-career engineer to dive into the heart of AI infrastructure connectivity, working hands-on with cutting-edge semiconductor devices that power the world's most advanced data centers. In this role, you will be instrumental in driving root-cause analysis of failures across circuit, package, firmware, and protocol layers - directly impacting the reliability and quality of our PCIe and Ethernet connectivity solutions. You'll work with state-of-the-art lab instrumentation, build infrastructure to accelerate failure analysis, and collaborate across engineering disciplines to ensure Astera Labs continues to deliver best-in-class silicon to hyperscale customers. If you're passionate about high-speed SERDES, signal integrity, and solving complex hardware problems at the intersection of AI and connectivity, this is the role for you. Key Responsibilities - Failure Analysis & Root-Cause

### System Validation Engineer (NCG 2026) - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2025-10-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4610812005
- Excerpt: System Validation Engineer (NCG 2026) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About Astera Labs Astera Labs is a rapidly growing semiconductor company redefining connectivity for AI and cloud infrastructure. Our intelligent connectivity solutions-built on PCIe®, CXL™, Ethernet, and custom fabrics-enable seamless data movement across compute, memory, and storage. As part of our team, you'll help validate the silicon that powers the world's most advanced AI platforms. Role Overview As an Entry-Level System Validation Engineer on the Taurus team, you will validate Astera Labs' Taurus Ethernet Smart Cable Modules and Taurus ASICs . You'll work on chip bring-up, system-level debug, and interoperability testing across real-world AI server and networking platforms, collaborating closely with electrical validation, firmware, and product applications teams. Key Responsibilities - Execute system validation test plans for Taurus Ethernet Smart Cable Modules. - Perform chip bring-up and debug for Taurus ASICs in lab environments using oscilloscopes, protocol analyzers, BERTs, and network switches - Validate high-speed interconnects and

### Staff/ Principal Architect - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4699636005
- Excerpt: Staff/ Principal Architect Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview We are seeking an experienced Staff/ Principal Architect to lead the architecture of high-performance connectivity solutions, with a strong focus on PCIe, high-speed networking, and Ethernet-based systems. This role will define next-generation architectures for AI infrastructure, working at the intersection of silicon, system, and protocol design . You will play a key role

### Hardware Design Engineering, Director - Active Electric Cable / Smart Cable Module Business - China - Astera Labs
- Location: Shanghai Shi, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702154005
- Excerpt: Hardware Design Engineering, Director - Active Electric Cable / Smart Cable Module Business - China Shanghai Shi, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Director, Hardware Design Engineering - AEC / SCM & China Customer Support Reports to: Senior Director, Hardware Design Engineering Location: Shanghai, China - Astera Labs Shanghai Design Center About Astera Labs Astera Labs is the connectivity backbone of rack-scale AI infrastructure. Our Active Electrical Cables (AEC), Smart Cable Modules (SCM), Silicon Evaluation Platforms, and rack-scale products deliver purpose-built, high-speed connectivity for the world's most demanding AI clusters. As our AEC and SCM product lines scale rapidly to meet hyperscale AI infrastructure demand - and as China-based OEM customers, hyperscale cloud providers, and system integrators increasingly adopt Astera Labs silicon and connectivity products - we are establishing a Shanghai-based hardware design center to drive product development, manufacturing collaboration, and customer engineering support in close proximity to our manufacturing partners and China-based customers. About the Role We are hiring a Director

### DFT Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-15
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4649842005
- Excerpt: DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is flawless and scalable.

### Senior Strategic Procurement Specialist - Corporate Services & Facilities Operations - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-09
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703780005
- Excerpt: Senior Strategic Procurement Specialist - Corporate Services & Facilities Operations Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, Astera Labs is seeking a hands-on Senior Strategic Procurement Specialist & Facilities Operations to support regional procurement activities across a growing set of international sites. This role is responsible for executing day-to-day sourcing, vendor management, and procurement operations to support labs, facilities, and office expansion. You will act as the primary procurement point of contact for your region, working closely with engineering, IT, facilities, and operations teams to ensure timely vendor onboarding, material availability, and resolution of purchasing issues. This role is critical to enabling site ramp and ongoing operations as Astera scales globally. Key Responsibilities - Strategic procurement specialist -

### Staff DFT Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703792005
- Excerpt: Staff DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Staff DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Staff DFT Engineer at Astera Labs, you will be at the intersection of architecture, design, and production. You won't just run tools-you will be a foundational member of the team responsible for the entire lifecycle of our silicon's reliability. From defining initial DFT architecture to supporting post-silicon bring-up, your work ensures that the backbone of AI infrastructure connectivity is

### Senior/Staff Physical Design Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $135K-$195K
- Posted: 2026-01-28
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4654857005
- Excerpt: Senior/Staff Physical Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer is required, and a Master's degree is preferred. - ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in

### Physical Design Engineer (Place & Route) - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $135K-$195K
- Posted: 2026-05-07
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4691424005
- Excerpt: Physical Design Engineer (Place & Route) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred. - 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and

### Senior Manager of Corporate Development - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $170K-$230K
- Posted: 2026-03-28
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4678056005
- Excerpt: Senior Manager of Corporate Development San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Are you passionate about driving strategic growth through impactful corporate development initiatives in the AI and cloud infrastructure space? Astera Labs is seeking a Senior Manager of Corporate Development to lead and support strategic transactions including acquisitions, investments, and strategic partnerships that will shape the future of AI connectivity. In this high-visibility role, you will report to the Head of Corporate Development and work closely with cross-functional teams including engineering, product management, and executive leadership to identify and evaluate opportunities that align with Astera Labs' long-term growth strategy. You will be at the forefront of emerging AI infrastructure technologies, developing new business models and driving transactions that accelerate our position as the leader in purpose-built connectivity solutions. This is a unique opportunity to join a hyper-growth company at the intersection of semiconductors and AI infrastructure, where your work will directly influence strategic decisions and contribute

### Sr. Director of Product Marketing - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $240K-$300K
- Posted: 2026-05-13
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695205005
- Excerpt: Sr. Director of Product Marketing San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Director of Product Marketing to lead go-to-market strategy for our industry-leading fabric switch and memory controller solutions. This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our connectivity products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate customers' needs into competitive roadmaps and compelling value propositions that resonate with decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape

### Lead Firmware Engineer - Astera Labs
- Location: Shanghai Shi, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-08
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4693668005
- Excerpt: Lead Firmware Engineer Shanghai Shi, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description The mission of this role is to architect and develop firmware and microcontroller subsystems for Astera Labs' SoC and systems products. Firmware is responsible for implementing the major differentiating features of Astera Labs' products. As such, firmware is considered equally important to the hardware, and the firmware team is often customer-facing accordingly to ensure the needs of the customer are fully comprehended. Basic qualifications - Strong academic and technical background in Electronics/Electrical/Computer Science engineering. At a minimum, a Bachelor's is required, and a Master's is preferred. - Minimum 5 years' experience supporting or developing complex SoC /silicon products for Server, Storage, and/or Networking applications. - Experience developing firmware to execute in on-chip microcontrollers as well as C-language software development kits (SDKs) to execute on system management controllers (e.g. BMC ). - Experience working with logic designers to architect and verify HW-SW interfaces on complex SoCs. - Professional attitude with

### Physical Design/CAD Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $135K-$195K
- Posted: 2026-03-31
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4679751005
- Excerpt: Physical Design/CAD Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design/CAD Engineer you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires RTL to GDS ownership across design stages (Synthesis/PnR/STA/Signoff), deep technical expertise, and close collaboration with RTL and verification teams to ensure robust full-chip signoff. This role is fully on-site and in-person. Key Responsibilities - As Physical Design CAD Engineer you will support and build flows for world class EDA tools. - Drive various Physical Design flow related activities, ensuring robust signoff across complex SoCs or sub-systems. - Architect and recommend flow improvements and enhance existing methodology for high performance design. - Good understanding of flow development related to backend tools like Synthesis/PnR/Extraction/DRC/LVS etc. - Work with cross function teams to define requirements and specifications

### Lead Product Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $133K-$185K
- Posted: 2026-03-25
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4677686005
- Excerpt: Lead Product Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Tech Lead Product Engineer to join our team in San Jose, CA. In this role, you will be at the intersection of silicon development and production excellence, ensuring our industry-leading connectivity solutions meet the highest standards of performance, reliability, and quality as they scale to volume production. As a key technical contributor, you will own the RF and signal integrity aspects of product engineering - from silicon characterization and validation through production test development and customer-facing debug. You'll work across the full product lifecycle, partnering with design, applications, and operations teams to drive our connectivity products from tape-out to high-volume manufacturing. This is a high-impact role at a company experiencing explosive growth, where your work directly enables the AI infrastructure revolution. With Astera Labs' portfolio spanning PCIe retimers, Ethernet solutions, and next-generation switching silicon operating at the bleeding edge of SerDes performance,

### Firmware Engineering Director/ Manager - Astera Labs
- Location: San Jose (unspecified)
- Salary: $230K-$265K
- Posted: 2025-10-22
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4608186005
- Excerpt: Firmware Engineering Director/ Manager San Jose Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Overview As a Firmware Engineering Director/ Manager , you will lead and scale firmware development efforts for Astera Labs' SoC and systems products used in data-center and AI infrastructure. You will be responsible for technical direction, people leadership, and execution across core firmware, bare-metal software, and device driver development. Firmware is a first-class differentiator at Astera Labs. In this role, you will build, mentor, and guide high-performing firmware teams while partnering closely with hardware, silicon architecture, validation, product, and customers to ensure successful delivery of complex firmware programs. This role supports two leadership levels: - Firmware Engineering Manager - Firmware Engineering Director Key Responsibilities - Own the firmware execution strategy across one or more SoC or systems programs, ensuring alignment with product and silicon roadmaps. - Lead and manage firmware teams responsible for bare-metal firmware, RTOS-based firmware, and device drivers. - Provide technical oversight and architectural guidance without being the

### Sr. Principal Product Marketer - Leo - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $180K-$250K
- Posted: 2026-01-14
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4646965005
- Excerpt: Sr. Principal Product Marketer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal, Product Marketing to serve as the strategic marketing leader for our Leo Smart Memory Extender product line - the industry's most advanced CXL-based solution enabling memory expansion and disaggregation for AI and cloud infrastructure at rack scale. This is a senior individual contributor role with outsized influence, where you'll define how the market understands, evaluates, and adopts CXL memory technology. As AI models scale to hundreds of billions of parameters and memory capacity becomes the defining bottleneck in modern data centers, Leo is uniquely positioned to unlock new levels of performance and efficiency. In this role, you'll operate as the authoritative voice of the Leo product line - shaping narratives that influence hyperscaler architecture decisions, driving industry thought leadership, and partnering with Astera Labs' most senior technical and business leaders to accelerate market creation. This is a

### Executive Sales Representative - Astera Labs
- Location: Taipei, Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674947005
- Excerpt: Executive Sales Representative Taipei, Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Regional Sales Executives will work closely with Field Sales Engineers (FAEs) and the sales management team to develop and execute an account strategy to effectively engage with leading cloud service providers on Astera Labs' portfolio of connectivity products. Responsibilities - Develop a customer specific sales plan that identifies revenue generating opportunities and outlines steps to effectively develop relationships within key influencers in R&D, Procurement, Executive level GM/CTO - Drive sales efforts by teaming up with FAEs engaging with customers to provide roadmap updates, technology training, product sampling, technical support and gather customer forecasts - Be a strong voice for your customers to communicate their product roadmap feedback, customer support issues and to drive a timely response from Astera Labs HQ - Establish regular communication with your customer's procurement, ODM ecosystem and other industry partners to be able to accurately forecast your region's quarterly revenue and annual demand forecast Qualifications - Bachelor's

### Principal AEC / AOC Program Manager - Astera Labs
- Location: Suzhou Qu, Gansu, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-09
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4683285005
- Excerpt: Principal AEC / AOC Program Manager Suzhou Qu, Gansu, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs Principal AEC / AOC Program Manager you will play a crucial role in overseeing the planning, coordination, and execution of manufacturing projects featuring Astera Labs' AEC / AOC portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. You will ensure that production processes run smoothly, meet quality standards, and are completed on time and within budget and responsible for manufacturing from NPI to mass production phases. To accomplish that, you will be working closely with designers, the manufacturing team, suppliers, and contract manufacturers. This role is expected to travel up to 30% of the year and will require business English skills. Job Responsibilities - Project Planning and Execution - Develop Project Plans: Create detailed project plans, including schedules, budgets, resource allocation, and timelines. - Coordinate Production Activities: Oversee all aspects of the manufacturing process,

### Director Product Marketing - Signal Connectivity Products - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $180K-$250K
- Posted: 2026-05-28
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4688393005
- Excerpt: Director Product Marketing - Signal Connectivity Products San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Director of Product Marketing to lead go-to-market strategy for our industry-leading connectivity solutions . This is a high-impact leadership role at the intersection of technology and market strategy, where you'll shape how the world's largest hyperscalers and AI infrastructure builders understand and adopt our PCIe signal conditioning products. As a senior leader on the product marketing team, you'll drive positioning, messaging, and competitive strategy for products enabling the next generation of AI and cloud data centers. You'll partner closely with engineering, sales, and executive leadership to translate deep technical capabilities into compelling value propositions that resonate with technical decision-makers. This role requires someone who can move fluidly between silicon-level technical discussions and strategic market conversations. With AI infrastructure demand accelerating and Astera Labs at the forefront of solving critical connectivity bottlenecks, this is an opportunity to shape the

### Benefits Manager - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $140K-$195K
- Posted: 2026-05-05
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4692326005
- Excerpt: Benefits Manager San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a strategic and knowledgeable Benefits Manager to join our Human Resources team in San Jose, California. As we continue our hyper-growth trajectory as a leader in AI infrastructure connectivity, this role will be instrumental in designing, managing, and optimizing our global benefits programs that attract and retain world-class talent. This is a high-impact position that goes beyond day-to-day benefits administration. You'll serve as a strategic partner to HR leadership, analyzing market trends, ensuring compliance across multiple geographies, and driving initiatives that enhance the employee experience. The ideal candidate brings a global mindset, thrives in a fast-paced environment, and is passionate about building benefits programs that support our rapidly scaling workforce across the US, Canada, Asia, and EMEA. Key Responsibilities Benefits Strategy & Program Management - Develop and execute a comprehensive global benefits strategy aligned with Astera Labs' growth objectives and talent acquisition goals - Evaluate and

### Principal Firmware QA Engineer - Astera Labs
- Location: Bengaluru, Karnataka, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695017005
- Excerpt: Principal Firmware QA Engineer Bengaluru, Karnataka, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Title : Lead Firmware QA Engineer , A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Basic Qualifications : - Bachelor's degree in electrical engineering (EE) or Computer Science is required; a master's or PhD in EE is preferred with minimum 4 years of experience. Required Experience : - Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol. - Estimate work, identify dependencies and develop schedules. - Responsible for designing and executing functional, performance, interoperability and stress tests. - Work closely with Silicon team, architecture team, FW development team to understand the

### Lead Firmware QA Engineer - Astera Labs
- Location: Bangalore, India (unspecified)
- Salary: Not disclosed
- Posted: 2026-02-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4655216005
- Excerpt: Lead Firmware QA Engineer Bangalore, India Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Title : Lead Firmware QA Engineer , A stera Labs, Bengaluru, India. Astera Labs Inc., a leader in purpose-built connectivity solutions for data-centric systems, is seeking Lead Software QA Engineer for their Bengaluru (India) Design Center. Partnering with leading processor and GPU vendors, cloud service providers, world-class manufacturing companies, Astera Labs is helping data-centric system designers remove performance bottlenecks in compute-intensive workloads such as Artificial Intelligence and Machine Learning. Basic Qualifications : - Bachelor's degree in electrical engineering (EE) or Computer Science is required; a master's or PhD in EE is preferred with minimum 4 years of experience. Required Experience : - Experienced and detail oriented PCIe switch test engineer with solid understanding of PCIe protocol. - Estimate work, identify dependencies and develop schedules. - Responsible for designing and executing functional, performance, interoperability and stress tests. - Work closely with Silicon team, architecture team, FW development team to understand the design

### Senior Embedded Software Engineer - Ethernet Retimers - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $133K-$185K
- Posted: 2026-06-05
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703734005
- Excerpt: Senior Embedded Software Engineer - Ethernet Retimers San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs' Taurus product line includes Ethernet retimers and gearboxes deployed in active electrical cables and in-system applications at the heart of AI infrastructure. As AI clusters scale to tens of thousands of GPUs connected by high-speed Ethernet fabrics, the firmware running on these connectivity devices is mission-critical - and so is the ability to debug it fast when something breaks. We're looking for a Firmware Engineer who can bridge our system validation team and firmware development organization. When something goes wrong in the lab or in the field, you won't be waiting on others to dig into the firmware. You'll be the person in the room who understands both sides - can pull up the code, identify the problem, and fix it. If you've worked at a networking company, know how Ethernet actually works from the MAC down through the PHY, have

### Hardware Lab Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $160K-$230K
- Posted: 2026-04-02
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674439005
- Excerpt: Hardware Lab Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview Astera Labs Inc. is seeking an experienced and self-driven Hardware Lab Engineer to join our dynamic team in developing world class connectivity products for AI infrastructure. Job Description This role will work closely with firmware, system validation, quality, and product engineers to support silicon bring-up, characterization, and debug activities through hands-on lab execution. The ideal candidate will have a deep understanding of circuits, hands-on experience with PCBAs and silicon test environments, and the ability to work on complex, open-ended tasks with minimal oversight. Key Responsibilities - Setup and maintain test environments for silicon validation and characterization. Configure and update hardware, software, firmware, and applications. Replicate BKCs. - Conduct hands-on testing of silicon devices including PCIe Gen5/6/7, CXL, Ethernet, and other high-speed interfaces - Install and configure servers, including FW, BIOS, OS, and network - RMA intake/triage: inspection, electrical verification, screening (including CSAM inspection), and prioritization - Manage logistics

### Senior Lab Validation Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $160K-$195K
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4699439005
- Excerpt: Senior Lab Validation Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Senior Lab Validation Engineer , you will take a hands-on role to find the root cause of any customer quality concerns and develop corrective actions. You will: - Directly root-cause failures to the circuit, package, firmware, or protocol-level interactions. Collaborate with design, validation, and system engineering teams as needed. - Modify device firmware to test out engineering theories leading to potential fixes or production screens. - Investigate failures such as link training issues, lane margining failures, eye closure, jitter sensitivity, protocol errors, and interoperability problems. - Debug retimer specific failures, including pass-through path issues, clock forwarding problems, equalization settings, and link bring-up reliability. - Analyze high speed link failures, including lane mapping, bifurcation errors, hot-plug issues, compliance test failures, and error propagation across multiple ports. - Use advanced lab instrumentation (BERT, high-bandwidth oscilloscopes, protocol analyzers, VNAs, TDR, spectrum analyzers) to characterize and isolate failures.

### Senior Principal Hardware Systems Engineer - Astera Labs
- Location: United States, Remote (remote)
- Salary: Not disclosed
- Posted: 2026-05-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4692960005
- Excerpt: Senior Principal Hardware Systems Engineer United States, Remote Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview The explosive growth of AI workloads is fundamentally reshaping how server platforms are designed - demanding unprecedented bandwidth, accelerator density, and intelligent connectivity at every layer of the stack. Astera Labs is powering this transformation with purpose-built connectivity solutions that enable the world's most advanced AI and cloud infrastructure, and we need exceptional hardware systems engineers to help architect what comes next. The AI Platform Solutions Group is seeking a Senior Principal Hardware Systems Engineer to lead the architecture and delivery of high-performance compute platforms with deep focus on PCIe subsystem design, GPU/accelerator integration, high-speed Ethernet networking, and system-level platform development. You will own the end-to-end system design from architecture definition through bring-up and validation, working at the critical intersection of compute, networking, storage, and Astera Labs' connectivity portfolio - including our PCIe retimers, switches, and fabric controllers. This role combines hands-on engineering depth with system-level architectural

### Hardware Engineering Operations / Manufacturing, AVP - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-04
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702155005
- Excerpt: Hardware Engineering Operations / Manufacturing, AVP San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . AVP of Hardware Engineering Operations/Manufacturing Role Overview Astera Labs is scaling rapidly as the connectivity backbone of rack-scale AI infrastructure, and our hardware manufacturing footprint is scaling with it. Smart Cable Modules (SCM), Active Electrical Cables (AEC), evaluation boards, AI Chassis-class systems, and ODM-built products are central to how we deliver purpose-built connectivity at hyperscale. We're hiring an AVP of Hardware Engineering Operations/Manufacturing to bring focused, senior leadership to this growing function. This is a wide-ranging role spanning the full breadth of Astera Labs' hardware portfolio - from Smart Cable Modules to rack-scale chassis-based products. You'll own manufacturing strategy and execution across SCM, AEC, evaluation boards (SVB/EVB), AI Chassis-class systems, and ODM-built products such as switch trays and CEM cards. You'll be the primary leader partnering with our contract manufacturers across China and the rest of Asia, driving quality, capacity, cost, and time-to-market as we scale

### Principal Physical Design Engineer, STA - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $209K-$250K
- Posted: 2026-05-20
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4691422005
- Excerpt: Principal Physical Design Engineer, STA San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview As an Astera Labs Principal Physical Design Engineer (STA) you will play a crucial role in driving the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This role requires end-to-end STA ownership across design stages, deep technical expertise, and close collaboration with RTL, physical design, and verification teams to ensure robust full-chip timing convergence. This role is fully on-site and in-person. Key Responsibilities - Drive timing closure from RTL through sign-off, ensuring robust timing across complex SoCs. - Develop and validate SDC constraints, including MMMC setup, to enable accurate and efficient STA analysis. - Define and manage I/O timing budgets across hierarchical designs. - Apply advanced sign-off methodologies at TSMC 7nm and below, including OCV/AOCV and PVT effects. - Leverage ETM libraries for hierarchical timing analysis and correlation,

### Distinguished Engineer – System & Rack Hardware Architecture - Astera Labs
- Location: United States, Remote (remote)
- Salary: Not disclosed
- Posted: 2026-05-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4692970005
- Excerpt: Distinguished Engineer – System & Rack Hardware Architecture United States, Remote Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater - and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, UAlink, CXL, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration,

### Senior Principal System Validation Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $205K-$255K
- Posted: 2026-04-29
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4690490005
- Excerpt: Senior Principal System Validation Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description - Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers' system requirements in the highest regard and is solely responsible for certifying a product's conformance to this high bar. - Understand the performance and functionality requirements our ICs must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. - Formulate a comprehensive validation plan, automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion. - Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions. Basic qualifications - Strong academic and technical background in Electrical or Computer Engineering. At a minimum, a Bachelor's

### Director of Product Engineering - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $187K-$260K
- Posted: 2026-06-03
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4702088005
- Excerpt: Director of Product Engineering San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Director of Product Engineering to lead our product engineering organization in San Jose, CA. This is a critical leadership role responsible for driving next-generation high-speed, high-performance, and low-power semiconductor products from silicon bring-up through high-volume manufacturing in advanced process nodes. As the AI infrastructure market accelerates at an unprecedented pace, Astera Labs needs a seasoned leader who can build and scale a world-class product engineering team while maintaining the technical depth to solve the hardest problems in high-speed connectivity. You will own the complete post-silicon product development lifecycle - from characterization and qualification through production ramp and sustaining - across our portfolio of purpose-built connectivity solutions enabling rack-scale AI. This role demands a unique combination of hands-on technical expertise in high-speed signaling and ATE test fundamentals, coupled with the organizational leadership to build teams, establish best-known methods, and deliver products to

### Distinguished Engineer – Server Firmware & System Architecture - Astera Labs
- Location: United States, Remote (remote)
- Salary: Not disclosed
- Posted: 2026-05-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4692566005
- Excerpt: Distinguished Engineer – Server Firmware & System Architecture United States, Remote Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is at the epicenter of the AI infrastructure revolution, building the intelligent connectivity solutions that power the world's most advanced data centers. As AI workloads scale to unprecedented levels, the demand for purpose-built, rack-scale platforms that seamlessly integrate high-speed connectivity, firmware intelligence, and composable architectures has never been greater - and neither has the opportunity to shape what comes next. The AI Platform Solutions Group is seeking a Distinguished Engineer to serve as the technical visionary for next-generation AI infrastructure, spanning server firmware, high-speed connectivity, and rack-scale system design. In this role, you will define the end-to-end architecture for AI platforms that integrate cutting-edge technologies such as PCIe Gen5/6, composable rack architectures, and advanced interconnect solutions including Astera Labs' portfolio of retimers, switches, and fabric controllers. This is a high-impact, high-visibility role where you will drive innovation across silicon integration, platform firmware,

### Tech Lead Field Application Engineer - Astera Labs
- Location: Seattle, Washington, United States, Remote (remote)
- Salary: Not disclosed
- Posted: 2026-05-14
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4695548005
- Excerpt: Tech Lead Field Application Engineer Seattle, Washington, United States, Remote Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Tech Lead Field Application Engineer to serve as the technical bridge between our customers and engineering teams, supporting our industry-leading connectivity solutions across the Aries PCIe retimer, Scorpio Ethernet fabric switch, and Leo CXL memory connectivity platforms. This is a high-impact, customer-facing role where you'll be embedded with hyperscaler and OEM partners, helping them design, validate, and deploy Astera Labs silicon into the AI infrastructure systems that are reshaping the data center landscape. As AI clusters scale to tens of thousands of GPUs and accelerators, the connectivity fabric binding compute, memory, and networking together has never been more critical. You'll operate at the intersection of cutting-edge silicon and real-world system deployment-solving complex signal integrity, interoperability, and performance challenges that directly influence product roadmaps and customer success. This role demands a self-starter who thrives in ambiguity, can independently drive technical engagements,

### Senior / Staff System Validation Engineer - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $135K-$195K
- Posted: 2026-03-30
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4677663005
- Excerpt: Senior / Staff System Validation Engineer San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description - Develop and perform system validation tests using leading-edge Data Center equipment and scalable automation platforms. The validation team holds customers' system requirements in the highest regard and is solely responsible for certifying a product's conformance to this high bar. - Understand the performance and functionality requirements our AI fabric Switches must deliver to enable customers developing Data Center systems using Astera Labs' game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. - Formulate a comprehensive validation plan for AI fabric switch products. automate the testing of ICs and board products in a data-centric manner, design experiments to root-cause unexpected behavior, report results and specification compliance in an automated fashion. - Work with key customers directly to understand their care-abouts and highlight the unique capabilities and performance of Astera Labs' solutions. Basic Qualifications - Strong academic and technical background in Electrical

### Hardware Design Engineering, Director - Active Electric Cable / Smart Cable Module Business - Taiwan - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-10
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4704546005
- Excerpt: Hardware Design Engineering, Director - Active Electric Cable / Smart Cable Module Business - Taiwan Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . We are hiring a Director of Hardware Design Engineering - OEM, Silicon Validation Platforms & Rack-Scale Design to establish and lead Astera Labs' Taiwan hardware engineering center. This role serves as the primary hardware engineering hub for OEM customer engagement across Asia, while simultaneously owning the design and development of Silicon Validation Platforms (SVB/EVB) and rack-scale products (AI chassis, switch trays, CEM cards). This is a high-impact leadership role that combines three critical functions: - OEM Design Enablement & Customer Support - Serving as the front-line hardware engineering partner for OEM customers in Asia (hyperscale cloud, server/switch OEMs, cable/module manufacturers) who are integrating Astera Labs silicon into their own products - Silicon Validation Platform Design (SVB/EVB) - Designing and delivering the evaluation boards and system validation platforms that enable silicon bring-up, characterization, customer evaluation, and reference design seeding - Rack-Scale

### Physical Design Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-16
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4649866005
- Excerpt: Physical Design Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Physical Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the backend execution and methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer , you will be a key architect of our silicon's physical reality. You won't just execute a flow-you will help establish our local execution culture and technical standards, owning the transformation of complex logic into high-performance silicon. You will drive the physical implementation journey from synthesis through signoff, ensuring our connectivity solutions meet the extreme performance, power, and area targets

### Expert IC Package Design Lead - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-02-22
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4664075005
- Excerpt: Expert IC Package Design Lead Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Expert IC Package Design Lead to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters. As an Expert IC Package Design Lead , you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will own package flow, architecture, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for defining package technologies

### Senior ASIC Design Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-16
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4649872005
- Excerpt: Senior ASIC Design Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior ASIC Design Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful product ownership in a new site, designing the digital blocks that sit at the heart of our most ambitious connectivity projects. As a Senior ASIC Design Engineer , you won't just build chips-you will be part of a team defining the next generation of AI infrastructure main components. The complex digital blocks under your micro-architecture and implementation responsibilities will power the world's largest AI clusters. You will own the journey from high-level definition through RTL implementation and backend support, transforming complex logic challenges into

### Senior/ Staff Physical Design Engineer - CAD Extraction - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674516005
- Excerpt: Senior/ Staff Physical Design Engineer - CAD Extraction Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Extraction to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with the highest precision from RTL to GDSII. Key Responsibilities - Develop, qualify, and maintain automated RC extraction flows for high-performance AI SoCs - Own the

### Senior Emulation Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-01-16
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4649850005
- Excerpt: Senior Emulation Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Emulation Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, implementing the emulation strategy for chips that power the world's largest AI clusters. As an Senior Emulation Engineer , you will be a core technical driver of our Israel R&D center, working at the intersection of hardware and software to ensure our silicon meets extreme quality and performance targets. You will execute end-to-end emulation flows, bridge the gap between RTL and functional validation, and partner with cross-functional teams to enable seamless hardware-software integration. If you thrive on solving complex technical challenges

### Senior/ Staff Physical Design CAD Engineer - Automation & Signoff - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674511005
- Excerpt: Senior/ Staff Physical Design CAD Engineer - Automation & Signoff Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design CAD Engineer specializing in CAD Automation and Signoff to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the backend execution environment and methodologies for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the physical implementation environment. Your primary mission is to develop, optimize, and support automated flows from RTL to manufacturable GDSII tape-out, ensuring a methodical and efficient work environment for the entire PD team. Key Responsibilities - Develop and

### Senior/ Staff Package Design Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674501005
- Excerpt: Senior/ Staff Package Design Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Package Design Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, Driving the physical implementation strategy for chips that power the world's largest AI clusters. As a Package Design Engineer, you will be a core technical contributor in the development of advanced IC packaging solutions for high-performance connectivity silicon. You will execute the package flow, design, and qualification from concept through production, working closely with silicon, signal integrity, power integrity, mechanical, manufacturing, and external OSAT partners. You will be responsible for implementing package technologies that meet aggressive electrical, thermal,

### Staff/ Principal Formal Verification Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674496005
- Excerpt: Staff/ Principal Formal Verification Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Formal Verification Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, defining the formal verification strategy for chips that power the world's largest AI clusters. As the Formal Verification Engineer, you will be a foundational member of our Israel R&D center. You won't just execute tasks; you will define the Formal verification strategy for chips that drive the world's largest AI clusters. You will dive deep into the technical details, proving the correctness of complex designs and ensuring they flawlessly meet specifications. Key Responsibilities - Own and develop formal

### Principal Product Manager - Ethernet - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: Not disclosed
- Posted: 2025-10-24
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4602854005
- Excerpt: Principal Product Manager - Ethernet San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Are you passionate about creating differentiated products and working with hyperscale and AI platform providers to deploy the next generation of data center infrastructure? We are seeking a highly technical and experienced product manager to join our team at Astera Labs. As a key member of our product management team, you will work closely with customers, product marketing, engineering and other internal cross-functional teams to define and deliver competitive silicon, hardware and software solutions. This is a unique opportunity to play a pivotal role in the success of our Taurus Ethernet Retimer portfolio. We are scaling our Taurus product management team to support our worldwide customers, offering ample opportunities for growth and advancement within the product team. Based in San Jose, this position requires an in-person presence with travel to customers. Key Responsibilities - Own product definition: Define detailed product requirements and prioritize features, enhancements, and bug fixes based

### Sales Intern - Astera Labs
- Location: Taipei, Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-10
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4670952005
- Excerpt: Sales Intern Taipei, Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking highly motivated Interns to join the Sales team in the TW team. If you are: - A Junior going into Senior year or Senior graduating by the end of this year - Have strong academics and technical background in Electrical Engineering - Someone with a professional attitude, ability to prioritize a dynamic list of multiple tasks and work with minimal guidance and supervision - Strong in analytical skills, self-motivated and a challenge taker What we are looking for: - Develop regional sales analysis and planning materials by identifying market segments, opportunity sizing, and internal execution strategies - Support sales initiatives by partnering closely with FAEs and internal stakeholders to prepare product information, roadmap materials, technology training content, and internal documentation - Consolidate and analyze input from internal teams to support product planning, roadmap alignment, and internal issue tracking - Coordinate cross-functional information flow among sales, operations, and supply-related teams

### Principal Electronics Engineer - Board Validation - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $185K-$230K
- Posted: 2025-12-30
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4644664005
- Excerpt: Principal Electronics Engineer - Board Validation San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As a Principal Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products. Key Responsibilities: - Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out. - Develop comprehensive hardware electrical validation plans using correct test methods and processes. - Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board. - Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc. - Rework components on the PCBAs to unblock debugging activities. - Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams. -

### Senior/Staff Electronics Engineer - Board Validation - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $135K-$195K
- Posted: 2025-05-20
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4567359005
- Excerpt: Senior/Staff Electronics Engineer - Board Validation San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As a Senior/Staff Electronics Engineer you will join the Hardware Electrical Validation team at Astera Labs, linking between the Hardware Electrical Design teams and Post-Silicon Electrical Validation teams, among others. Note: This role is not post-silicon electrical validation; it is electrical validation of PCBAs and related hardware products. Key Responsibilities - Support the Hardware Electrical Design teams with de-risking circuits and modules from project kick-off to gerber out. - Develop comprehensive hardware electrical validation plans using correct test methods and processes. - Bring up the PCBAs upon arrival in the lab, and execute the electrical validation plans to validate all circuits on the board. - Debug complex multi-point failures in hardware - power regulators, DPMs, clock synthesizers, digital control paths, I2C, SPI, etc. - Rework components on the PCBAs to unblock debugging activities. - Pre-empt and de-risk system validation architectures - collaborate with the System Validation teams. -

### Principal Signal and Power Integrity Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $203K-$250K
- Posted: 2026-02-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4666076005
- Excerpt: Principal Signal and Power Integrity Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . At Astera Labs, we seek motivated Principal Signal and Power Integrity Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will execute the SI planning, design, modeling, simulation, and lab validation with various system configurations. This position will be onsite. Basic Qualifications - Strong academic/technical background in electrical engineering; Bachelor's is required; Master's preferred. - 8+ years of experience supporting or developing complex SoC/silicon products for Server and Networking applications. - 8+ years of hands-on high-speed SI/PI design, simulation, and measurement experience. - Have a proven track record with defining hardware system constraints and high-speed technology roadmaps. - Cross-functional design mentality with the electrical design community to develop systems. - Self-starting, professional, and hands-on work ethic that can execute intense research in a dynamic environment. - Proven track record solving problems independently, preferably as a tech

### Senior Principal Digital Design Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $205K-$255K
- Posted: 2026-03-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4672620005
- Excerpt: Senior Principal Digital Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Senior Principal Digital Design Engineer to drive the architecture and implementation of next-generation digital designs powering AI infrastructure connectivity. This is a high-impact technical leadership role where you'll define micro-architecture strategies for better power, performance and area tradeoff, own complex chip-level design decisions, and guide multiple blocks from concept through silicon bring-up for industry-leading products supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols. As a senior technical leader, you'll shape design methodologies, mentor engineering teams, and collaborate cross-functionally with verification, physical design, DFT, and post-silicon teams to deliver high-performance, production-quality silicon. You'll also influence roadmap decisions and drive design excellence across the organization, ensuring Astera Labs continues to set the standard for AI connectivity solutions. Key Responsibilities - Architecture & Technical Leadership - Define and drive micro-architecture for complex digital blocks and subsystems across multiple product lines - Establish

### Manager, Package Design Engineering - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $230K-$265K
- Posted: 2026-03-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4678037005
- Excerpt: Manager, Package Design Engineering San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is seeking a Manager, Package Design Engineering to lead and scale our Package Design team in San Jose. In this high-impact role, you'll own the end-to-end delivery of advanced IC packaging solutions-from early architecture definition through production ramp-enabling the next generation of AI infrastructure and connectivity products. As the semiconductor industry races toward chiplet-based architectures, 2.5D/3D integration, and ever-increasing bandwidth demands, packaging has become a critical differentiator. You'll build and mentor a high-performing team while driving cross-functional execution with silicon architecture, SIPI, PCB, validation, manufacturing, and external partners including substrate vendors and OSATs. Your work will directly impact Astera Labs' ability to deliver industry-leading PCIe, CXL, and Ethernet connectivity solutions to the world's most demanding hyperscale and AI customers. This role offers the opportunity to shape design methodology, establish scalable standards, and enable chip-package-board co-design frameworks across multiple product lines in a fast-moving, innovation-driven

### Chip Lead, Senior Director - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: Not disclosed
- Posted: 2026-04-09
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4677688005
- Excerpt: Chip Lead, Senior Director San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking an Senior Director OR Associate Vice President, Product Technical Lead (Chip Lead) to drive the end-to-end success of our next-generation UALink switching products in San Jose. This is an executive technical leadership role where you will connect architecture, design, validation, firmware, systems, and operations to ensure clarity, alignment, and predictable execution across the full product lifecycle. As the technical integrator for the product line, you will lead through influence and cross-functional authority, working on cutting-edge UALink, UCIe, and PCIe Gen6/Gen7 technologies that power the largest AI clusters in the world. You'll be the central technical voice ensuring our switching products scale with Astera's hyper-growth while delivering world-class silicon to customers enabling rack-scale AI and hyperscale data centers. Location - San Jose, CA OR Israel Key Responsibilities - Product Technical Ownership - Own the full technical lifecycle of the product line-architecture assumptions, design integration, validation

### Senior/Tech Lead Silicon Validation Engineer - Astera Labs
- Location: San Jose, United States (unspecified)
- Salary: $148K-$195K
- Posted: 2025-05-27
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4564787005
- Excerpt: Senior/Tech Lead Silicon Validation Engineer San Jose, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: At Astera Labs, we are looking for motivated Senior / Tech Lead Post-Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers' requirements in the highest regard and is solely responsible for certifying a product's parametric conformance to this high bar. Basic Qualifications: - Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred. -

### Senior/ Staff Physical Design Engineer - EMIR CAD - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674955005
- Excerpt: Senior/ Staff Physical Design Engineer - EMIR CAD Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in EMIR CAD to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As a Physical Design Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will continuously develop the Electro-Migration and IR Drop (EMIR) flow, working closely at the intersection of Physical Design, Analog/Mixed-Signal design, and Package Engineering. Key Responsibilities - Take

### Lead HVM Product Engineer - Astera Labs
- Location: Taipei,Taiwan (unspecified)
- Salary: Not disclosed
- Posted: 2025-08-29
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4602437005
- Excerpt: Lead HVM Product Engineer Taipei,Taiwan Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As an Astera Labs HVM Product and Test Engineering, you will support existing products already in HVM (high volume manufacturing) at our Asia OSAT partners. Maintaining smooth manufacturing to ensure on-time customer shipments is one key objective. In this role, you will complement the New Product Introduction Product Engineers as products are released into production and own the engineering manufacturing during mass production. The ideal candidate possesses breadth of industry experience in high-speed product development in the field of product and/or test engineering, can apply fundamentals in circuit, ATE, and test program to aid problem solving, and is a self-driven, result focused go-getter in the pursuit of goals and objectives. Basic qualifications: · Minimum of 5 years of experience in the field of post silicon product development dealing with high-speed XCVR (product, test or validation) · Experience in working with PCIe Gen3 and above · Have gone through at least

### Staff Physical Design Engineer - SoC EMIR Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-07
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703779005
- Excerpt: Staff Physical Design Engineer - SoC EMIR Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance and

### Staff/ Principal Design Verification Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701334005
- Excerpt: Staff/ Principal Design Verification Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Staff/ Principal Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Staff/ Principal Design Verification Engineer , you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the

### Senior/ Staff Physical Design STA Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674520005
- Excerpt: Senior/ Staff Physical Design STA Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Static Timing Analysis (STA) Engineer to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the sign-off methodology for chips that power the world's most advanced AI clusters. As an STA Engineer, you will be deeply involved in the STA activities from chip partition and time budgeting through to final sign-off. You will bridge the gap between Architecture, Design, DFT, and Physical Design to ensure our high-performance silicon meets the aggressive timing targets required for next-generation connectivity. Key Responsibilities - Execute the STA flow and sign-off methodologies, ensuring our

### Senior/ Staff Front-End CAD Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-19
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4675017005
- Excerpt: Senior/ Staff Front-End CAD Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Front-End CAD Engineer to join our local engineering powerhouse from the ground up. As a Front-End CAD Engineer, you will be the backbone of our chip design ecosystem. You won't just be using tools; you'll be architecting the methodologies, automation scripts, and design flows that enable our hardware teams to push the limits of silicon performance. Your work directly impacts the productivity of the design team and the time-to-market for our next-generation processors. Key Responsibilities - Develop, maintain, and optimize RTL generation tools, building automated IPs and SoC schemes - Create robust applications using Python and Tcl to automate models build, regression and analysis tools and

### Staff/ Principal Physical Design CAD Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701340005
- Excerpt: Staff/ Principal Physical Design CAD Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for a Physical Design CAD Engineer with at least 3 years of hands-on experience in digital implementation flows. The ideal candidate is highly technical, curious, and eager to drive innovation by combining strong physical design knowledge with modern automation and GenAI-based methodologies. This is a unique opportunity to take on meaningful technical ownership in a new site, implementing the parasitic extraction (PEX) methodologies and flows for chips that power the world's largest AI clusters. As a foundational member of the team, you will be responsible for the accuracy and efficiency of our extraction environment, ensuring that our high-speed designs are modeled with

### Principal Engineer, SOC IP Systems & Lifecycle Management - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $175K-$230K
- Posted: 2026-04-29
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4690506005
- Excerpt: Principal Engineer, SOC IP Systems & Lifecycle Management San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Objective As the gatekeeper of IP Management, Methodology and Quality at Astera Labs, you will lead the strategic development of our AI-powered IP Lifecycle Management and IP Quality Assurance Platform. You won't just run tools; you will architect a scalable, user-friendly system that serves as the foundation for our "AI-first" IP ecosystem. Your mission is to ensure every IP, whether internal or external is easily accessible, physically, logically, and structurally "SOC-ready," preventing late-stage integration breaks that delay tape-outs. Our vision is to revolutionize IP Management and Quality Assurance with an AI-first approach. The candidate will be responsible for developing the platform, auditing and qualifying internal and external IP (Hard/Soft Macros, PHYs, Memories and standard cells libraries among other IPs). The IPLM and IPQA tools will scale to cover SOC QA and be a key element of the tape out sign-out requirements. The successful

### Senior Design Verification Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701333005
- Excerpt: Senior Design Verification Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Senior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Senior Design Verification Engineer , you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of

### Senior/ Staff Chip Top Physical Design Engineer - Astera Labs
- Location: Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-03-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4674527005
- Excerpt: Senior/ Staff Chip Top Physical Design Engineer Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Chip Top Physical Design Engineer focusing on implementation to join our local engineering powerhouse from the ground up. If you thrive on solving complex, unnamed challenges in deep-submicron processes, your place is with us. As a Physical Design Engineer, you will be a key hands-on member of our PD Team in the Israel R&D center. You will execute the physical design of the SoC Top level for chips that drive the world's largest AI clusters. You will be deeply involved in all PD disciplines of the chip, driving the tape-out (T.O.) GDS to meet strict signoff criteria (Timing, LVS, EMIR, DRC, PV, etc.), ensuring

### Senior Data Science Engineer - Astera Labs
- Location: Haifa, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2025-12-11
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4640055005
- Excerpt: Senior Data Science Engineer Haifa, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description Astera labs is seeking a skilled and motivated Data Scientist. This individual will play a pivotal role in identifying key data points for collection, developing strategies to accumulate data and deriving actionable insights an anomaly based on a solid foundation of relevant know-how. Also, will also be responsible for creating, testing, and deploying scripts and methods for data collection and analysis to support decision-making. The Engineer will collaborate with cross-functional teams to identify critical data sources to determine the most effective data collection strategies, will develop automated and scalable data collection pipelines, will ensure data quality, integrity, and consistency across all sources and may use AI techniques to refine the results toward failures predictions. Basic Qualifications - Bachelor's degree in computer science, Data Science, Engineering, Mathematics, or a related field. - Advanced degrees in data science or Machine learning / AI - Advance. - Proficiency in programming languages such

### Staff/ Principal Physical Design Engineer - SoC EMIR Expert - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-07
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703778005
- Excerpt: Staff/ Principal Physical Design Engineer - SoC EMIR Expert Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a highly skilled Physical Design Engineer specializing in SoC EMIR to join our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful technical ownership in a new site, executing the backend power methodologies for chips that power the world's largest AI clusters. As an EMIR Engineer, you will be a core technical contributor ensuring the power robustness and long-term reliability of our high-performance connectivity silicon. You will be responsible for SoC EMIR Analysis to ensure our products meet aggressive voltage drop and reliability targets in advanced FinFET process nodes, directly impacting the performance

### Office Administration Manager - Astera Labs
- Location: Haifa District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4699143005
- Excerpt: Office Administration Manager Haifa District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, We are looking for an experienced and proactive Office Administration Manager to oversee the daily operations of our Haifa site and ensure a smooth, organized, and employee-focused work environment. This role combines office operations, facilities coordination, employee welfare, logistics, and administrative support. Key Responsibilities - Manage day-to-day office operations and administrative processes - Support employee welfare initiatives, site events, and office experience activities - Coordinate office facilities, maintenance, and vendor relationships - Handle procurement and operational purchasing activities - Manage office logistics, including import/export coordination - Monitor office supplies, services, and operational budgets - Support onboarding and offboarding processes, including seating arrangements and site setup - Coordinate meetings, office activities, and

### Principal Product Manager - Smart Cable Modules - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $158K-$220K
- Posted: 2026-03-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4678070005
- Excerpt: Principal Product Manager - Smart Cable Modules San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Principal Product Manager - Smart Cable Modules Astera Labs is at the center of the AI infrastructure revolution, and our Smart Cable Modules are critical to enabling the high-bandwidth, low-latency connectivity that next-generation data centers demand. We're looking for a Principal Product Manager to own and drive this exciting product portfolio-working directly with hyperscalers and AI platform providers to define solutions that push the boundaries of what's possible. In this role, you'll be the connective tissue between our customers, engineering teams, and go-to-market functions. You'll translate complex customer requirements into differentiated products, guide development from concept through launch, and help secure design wins with the world's most demanding infrastructure builders. This is a high-visibility, high-impact opportunity to shape products that will power the future of AI and cloud computing. Based in San Jose, this position requires an in-person presence with regular travel to customers. Key

### Hardware Diagnostics Senior Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $120K-$195K
- Posted: 2026-02-24
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4664494005
- Excerpt: Hardware Diagnostics Senior Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As a Senior Software Diagnostics Engineer on the Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture of cutting-edge high-speed datacenter products. You will be working on a project from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and a good understanding of hardware design and manufacturing practices. At the same time, we welcome candidates with deep experience in smaller areas and desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities: - Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. - Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product - Bring-up newly manufactured boards and port the first level of

### Principal Design Verification Engineer - Astera Labs
- Location: San Jose, United States (unspecified)
- Salary: $185K-$230K
- Posted: 2026-03-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4676963005
- Excerpt: Principal Design Verification Engineer San Jose, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs is seeking a Principal Design Verification Engineer with strong problem-solving abilities and a passion for developing robust verification methodologies for complex ASICs. The ideal candidate will have a solid background in SystemVerilog and experience with C/C++, Python, or similar scripting languages. This role involves full lifecycle verification-from planning and test development to debugging and coverage closure-contributing to the success of cutting-edge SoC designs. Key Responsibilities - Lead the functional verification of advanced ASICs, including test planning, development, execution, and coverage analysis. - Collaborate closely with software and system validation teams to create and execute test plans on emulation platforms. - Apply both directed and constrained-random verification techniques using SystemVerilog/UVM and other relevant tools. - Debug test failures, analyze coverage results, and close functional coverage gaps to ensure comprehensive verification. - Work with RTL designers to troubleshoot and resolve design issues. - Drive verification strategy and methodology for

### Principal Diagnostic Platform Software Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $203K-$230K
- Posted: 2025-08-26
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4601154005
- Excerpt: Principal Diagnostic Platform Software Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Description: As member of Astera Labs Hardware Engineering team you will be responsible for building diagnostics and manufacturing software to allow design, test, and manufacture cutting edge high speed datacenter products. You will be working on projects from conception to the final production stage at contract manufacturer. The role requires a strong and broad software background and good understanding of hardware design and manufacturing practices. At the same time we welcome candidates with deep experience in smaller areas with the desire to learn. Depending on your experience, you may be focusing on design/validation or automation/manufacturing. Key Responsibilities - Design, implement & test production-grade diagnostics for high-speed digital boards and ASICS to help with hardware validation. - Design, implement & test manufacturing tests to validate mass production of digital boards used in data center networking product - Bring-up newly manufactured boards and develop the first level of software. -

### Production/Test Engineer - Astera Labs
- Location: Suzhou Qu, Gansu, China (unspecified)
- Salary: Not disclosed
- Posted: 2026-05-12
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4693337005
- Excerpt: Production/Test Engineer Suzhou Qu, Gansu, China Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Astera Labs Inc. is a fabless semiconductor company who is a leader in developing purpose-built connectivity solutions that remove performance bottlenecks in compute-intensive workloads such as artificial intelligence and machine learning. To support rapid international business growth, we are hiring Production/Test Engineer who is based in Suzhou area and have experience supporting the development and manufacturing in semiconductor products for high-speed communication protocols like PCIe, Ethernet, Infiniband, DDR, NVMe, USB, etc. Job Description: As the Production/Test Engineer, you will report to Head of PCBA manufacturing. In this role, you will be responsible for PCBA / outsourcing manufacture production management, testing and validation, troubleshooting and issue resolution in production lines. Collaborate with quality organization, engineering team on manufacturing process management and functional validation. Basic qualifications: - BS in manufacturing, operations, electrical engineering (or other disciplines directly related to manufacturing). Master's degree is - Minimum of 5 years' experience working or managing in

### Silicon Technical Program Manager - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-02
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701820005
- Excerpt: Silicon Technical Program Manager Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Silicon Technical Program Manager to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, leading the physical implementation strategy for chips that power the world's largest AI clusters. As an Technical Program Manager, you will be the key architect of our silicon's operational reality. You won't just track timelines - you will help establish our local execution culture and technical standards, owning the cross-functional journey of transforming complex logic into high-performance silicon. Key Responsibilities - Drive and manage ASIC development and subsystems from concept through to production

### Physical Design Student - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-02
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701792005
- Excerpt: Physical Design Student Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we are seeking a motivated Physical Design Student to join our founding local engineering team. This is a unique opportunity to kickstart your career in the semiconductor industry. Working alongside senior industry veterans, you will gain hands-on experience in backend execution and advanced methodologies for cutting-edge chips that power the world's largest AI clusters. If you are passionate about silicon hardware, eager to learn, and thrive on solving complex engineering challenges, this role offers the perfect bridge between your academic studies and a high-impact career. Key Responsibilities Guided Implementation & Learning - Partner with and learn from senior engineers to support the physical implementation journey, including synthesis, floorplanning,

### Junior Design Verification Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-01
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4701302005
- Excerpt: Junior Design Verification Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a talented Junior Design Verification Engineer to help build our local engineering powerhouse from the ground up. This is an exciting opportunity to take on meaningful ownership in a new site, developing the verification environments that ensure our next-generation AI silicon performs flawlessly. As a Junior Design Verification Engineer , you will be a vital contributor to the quality and reliability of our Israel R&D center. You will work on the front lines of functional verification, developing testbenches and environments that validate high-performance digital blocks, subsystems, and full-chip designs. You will tackle complex verification challenges that ensure our connectivity solutions meet the rigorous demands of

### Principal DFT Engineer - Astera Labs
- Location: Tel Aviv-Yafo, Tel Aviv District, Israel (unspecified)
- Salary: Not disclosed
- Posted: 2026-06-08
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4703793005
- Excerpt: Principal DFT Engineer Tel Aviv-Yafo, Tel Aviv District, Israel Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Role Overview Astera Labs is establishing a strategic R&D center in Israel to drive the development of complex semiconductor chips that solve the critical 'data bottlenecks' enabling the future of AI at scale. As we expand our presence in Israel, we're seeking a visionary Principal DFT Engineer to help build our local engineering powerhouse from the ground up. This is a unique opportunity to take on meaningful product ownership in a new site, ensuring the reliability and testability of chips that power the world's largest AI clusters. As a Principal DFT Engineer, you will provide technical leadership across the full DFT lifecycle-from architecture and specification through implementation, verification, and silicon bring-up. You will define and drive DFT strategy, establish robust methodologies, and lead execution to ensure high test quality and manufacturability. This role requires deep expertise, cross-functional influence, and the ability to drive DFT excellence across projects and

### Principal Silicon Validation Engineer, SerDes/PAM4 - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $185K-$230K
- Posted: 2026-02-18
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4662564005
- Excerpt: Principal Silicon Validation Engineer, SerDes/PAM4 San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview The mission of this role is to develop and execute electrical validation tests to quantify parametric device performance and margins over all system conditions. The validation team holds customers' requirements in the highest regard and is solely responsible for certifying a product's parametric conformance to this high bar. At Astera Labs, we are looking for motivated Principal Silicon Validation Engineers to work on our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role you will formulate a comprehensive post-Silicon validation plan, automate the testing of ICs and board products, design experiments to root-cause unexpected behavior, report results and specification compliance, and work with key internal customers to quantify margins and ensure robustness. Basic Qualifications: - Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred. - 8 + years'

### Principal Product Application Engineer - Leo - Astera Labs
- Location: San Jose, California, United States (unspecified)
- Salary: $175K-$230K
- Posted: 2026-04-29
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4690430005
- Excerpt: Principal Product Application Engineer - Leo San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . About the Role As a Principal Product Applications Engineer on the Leo team, you will sit at the intersection of firmware engineering and customer-facing technical engagement. You will be a key technical resource for enabling Leo CXL Smart Memory Controllers at hyperscale customers and OEM partners - owning firmware bring-up, validation, and customer issue resolution from early silicon through production ramp. Firmware is considered equally important to hardware at Astera Labs, and this role reflects that. You will work directly with customers to ensure their needs are fully understood and translated into firmware solutions, while collaborating closely with the internal firmware, hardware, and systems engineering teams. This position is required onsite in San Jose, CA. Key Responsibilities - Lead firmware-focused customer engagements for Leo CXL Smart Memory Controllers, including bring-up support, feature enablement, and issue triage on customer platforms - Develop, validate, and debug firmware using

### Principal Silicon Validation Engineer - Astera Labs
- Location: San Jose, CA (unspecified)
- Salary: $250K-$250K
- Posted: 2025-12-23
- Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4613831005
- Excerpt: Principal Silicon Validation Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Overview: The mission of this role is to develop and execute electrical validation tests that quantify parametric device performance and operating margins across all system conditions. The validation team upholds customer requirements to the highest standard and serves as the final authority in certifying a product's parametric compliance. Astera Labs is seeking motivated Principal / Senior Principal Post-Silicon Validation Engineers to support our game-changing portfolio of connectivity products for Artificial Intelligence and Machine Learning applications. In this role, you will define comprehensive post-silicon validation plans, automate IC- and board-level testing, and design experiments to identify and root-cause unexpected behavior. You will analyze and report validation results against specifications, collaborate closely with key internal stakeholders, quantify performance margins, and ensure robust, production-ready designs. Basic Qualifications: - Strong academic and technical background in Electrical or Computer Engineering. At minimum, a Bachelor's is required, and a Master's is preferred. - ≥10 years experience

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