# FewerJobs export - 100 curated jobs Generated: 2026-11-10T01:29:23.993Z Source: https://fewerjobs.com ## Filters applied - **q**: Synopsys - **quality_floor**: default - **match_401k_strict**: true - **parental_strict**: true - **non_birth_strict**: true - **pto_strict**: true - **include_older**: false - **apply_url_verified**: false - **page**: 2 - **per_page**: 100 - **sort**: relevance ## Jobs ### DevOps Engineer - Zoom Communications, Inc. - Location: Remote (VA) (remote) - Salary: Not disclosed - Posted: 2026-06-12 - Apply: https://zoom.wd5.myworkdayjobs.com/zoom/job/Remote--VA/DevOps-Engineer_R18865 - Excerpt: DevOps Engineer Remote (VA) posted: ### Senior CAD Engineer - Cisco - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Caesarea-Israel/Senior-CAD-Engineer_2003345 - Excerpt: Senior CAD Engineer 2 Locations Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As part of our team, you'll contribute to the development of our next-generation network devices-Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical Synthesis, Place and Route, ### Enterprise Account Executive - Gumloop - Location: San Francisco Office | OnSite | Vancouver Office (onsite) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.ashbyhq.com/gumloop/02a4e41c-ca1e-4dd7-88b6-d14fd8c8d401 - Excerpt: Enterprise Account Executive San Francisco Office | OnSite | Vancouver Office ABOUT US Gumloop is the AI automation platform for the enterprise. We give teams the power to easily build and deploy AI agents, in Slack, Microsoft Teams, or standalone, that automate real work across hundreds of integrations with no engineering background required. The platform has three pillars: 1. Agents - Conversational AI assistants that use tools (integrations, workflows, code sandbox, MCP servers) to accomplish open-ended tasks. Unlike workflows that follow fixed paths, agents decide which tools to use and when, adapting based on context. Users configure agents with a system prompt, a model, and a set of tools. Agents can be deployed to a chat UI, Slack, or Microsoft Teams, and can run autonomously via scheduled or event-based triggers. 2. Workflows - Visual, drag-and-drop automations composed of connected nodes on a canvas. Each node is a discrete operation (call an API, run AI, read a spreadsheet, send an email). Workflows are deterministic and repeatable. They can be triggered manually, on a schedule, via webhook, or by external events (new email, Slack message, etc.). Workflows can also be attached to agents as callable tools - the agent orchestrates, the workflow executes. 3. Gumstack - Enterprise-grade MCP hosting, observability, and AI governance. Organizations provision managed MCP servers, control which AI models are available, audit every tool call, and enforce security policies across all agents and workflows. We're moving fast. Teams at Gusto, Ramp, Shopify, Samsara, Instacart, and Opendoor are already building ### Full Stack Software Engineer - Gumloop - Location: San Francisco Office | OnSite | Vancouver Office (onsite) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.ashbyhq.com/gumloop/a7b6de54-8e37-4d69-ac03-f9c1d4075205 - Excerpt: Full Stack Software Engineer San Francisco Office | OnSite | Vancouver Office ABOUT US Gumloop is the AI automation platform for the enterprise. We give teams the power to easily build and deploy AI agents, in Slack, Microsoft Teams, or standalone, that automate real work across hundreds of integrations with no engineering background required. The platform has three pillars: 1. Agents - Conversational AI assistants that use tools (integrations, workflows, code sandbox, MCP servers) to accomplish open-ended tasks. Unlike workflows that follow fixed paths, agents decide which tools to use and when, adapting based on context. Users configure agents with a system prompt, a model, and a set of tools. Agents can be deployed to a chat UI, Slack, or Microsoft Teams, and can run autonomously via scheduled or event-based triggers. 2. Workflows - Visual, drag-and-drop automations composed of connected nodes on a canvas. Each node is a discrete operation (call an API, run AI, read a spreadsheet, send an email). Workflows are deterministic and repeatable. They can be triggered manually, on a schedule, via webhook, or by external events (new email, Slack message, etc.). Workflows can also be attached to agents as callable tools - the agent orchestrates, the workflow executes. 3. Gumstack - Enterprise-grade MCP hosting, observability, and AI governance. Organizations provision managed MCP servers, control which AI models are available, audit every tool call, and enforce security policies across all agents and workflows. We're moving fast. Teams at Gusto, Ramp, Shopify, Samsara, Instacart, and Opendoor are already ### Principal Engineer, ASIC Development Engineering (Physical Design, PNR, floor plan) 8 to 12 years of experience - SanDisk - Location: Bengaluru, KA, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.smartrecruiters.com/Sandisk/744000130521939-principal-engineer-asic-development-engineering-physical-design-pnr-floor-plan-8-to-12-years-of-experience - Excerpt: Principal Engineer, ASIC Development Engineering (Physical Design, PNR, floor plan) 8 to 12 years of experience Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance, and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: Position Overview: We are seeking a highly skilled and experienced Principal Engineer for our PNR function. The successful candidate will be part to a team of talented engineers responsible for ensuring the PNR convergence of our complex semiconductor designs. This role requires a deep understanding of PNR methodologies, leadership skills, and a strategic vision to drive continuous improvement in our PNR ### DevOps Engineer (New York) - Torq - Location: New York, United States (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Apply: https://job-boards.greenhouse.io/torq/jobs/6010964004 - Excerpt: DevOps Engineer (New York) New York, United States Skeletons, lasers, tattoo buses - the Torq brand grabs attention like nothing else in cybersecurity. And we're growing like crazy, backed by Series D funding, 200% employee growth, and 300% revenue growth. Fueling Torq's momentum is our game-changing AI SOC platform, backed by a team and culture that makes Torq one of Forbes' Best Startup Employers in America, and a Business Insider 'startup to bet your career on'. Life at Torq is all gas, no brakes. We're a team of relentless, collaborative go-getters pushing the boundaries of what's possible for security automation. Every role is an essential driver of Torq's success as the AI-native autonomous SecOps platform of choice for security teams across the Fortune 500. We're looking for a DevOps Engineer to join our fast-growing company at a breakthrough stage - building our dream team with the most passionate and professional people in the industry. This is a US-based position, joining a global DevOps team primarily based in Israel. We're looking for someone highly independent, adaptable, and proactive - a self-starter who thrives in a fast-moving environment and can collaborate effectively across time zones. Our team thinks differently and moves quickly, delivering high-quality, innovative solutions using the latest technologies and frameworks - all while enjoying the ride! What You'll Be Doing: - Champion a DevOps mindset: Identify friction points and implement scalable automation to improve reliability, delivery speed, and developer experience. - Operate and optimize production environments: Use infrastructure as code ### FPGA Engineer - Belvedere Trading - Location: Chicago, Illinois (unspecified) - Salary: Not disclosed - Posted: 2026-04-30 - Apply: https://jobs.lever.co/belvederetrading/67c39285-40b4-436f-9e12-5644f070f46f - Excerpt: FPGA Engineer Chicago, Illinois Belvedere Trading is a leading proprietary trading firm proudly headquartered in downtown Chicago. Our traders work hard to provide liquidity to the market through their market-making activities and are the masters of a diverse set of commodities, interest rates, exchange-traded funds (ETF), and equity index options. From the beginning, we began iteratively investing in our proprietary technology and committing to building our systems from the ground up. Our trading models and software systems are continually re-engineered, optimized, and maintained to stay on top of the industry. This wouldn't be possible without the dedicated efforts of our technology teams who utilize and perfect our innovative technology solutions. High-performance proprietary development is the source of our success and competitive advantage at Belvedere, further fueling our passion for performance. We are a team driven by intellectual curiosity, seeking answers that will change not only how we trade in this technological age, but also the future landscape of the trading industry. We place a high premium on defining, developing, and deploying high-performance trading software using a team-based, holistic development approach. We look for passionate team members that excel and their contribution is critical to our continued success. Belvedere Trading is looking for an FPGA Developer to supplement the team and drive projects that will optimize our options market marking systems. Successful candidates will have a proven track record of success delivering complex FPGA systems on a chip design, possess excellent problem-solving abilities, possess a can-do/self-driven attitude, and have the ability ### GPU Top Level Physical Design Engineer - Apple - Location: Austin, United States of America (unspecified) - Salary: $181K-$318K - Posted: 2026-04-14 - 401(k) match: listed (not source-backed) - Apply: https://jobs.apple.com/en-us/details/200657709/gpu-top-level-physical-design-engineer?team=HRDWR - Excerpt: GPU Top Level Physical Design Engineer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU! You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices! This role requires a mix of strategic engineering along with hands-on, technical work. You will be responsible for implementing complete chip design from netlist to tapeout. You will have hands on experience in physical design and large chip integration. As a GPU Top Level Physical Design engineer, you will collaborate with FE team to understand RTL and drive physical aspects early in design cycle. You will drive innovation with the physical design team, as you develop methodologies and “best known methods” that will enable best-in-class GPU design. You will develop PD guidelines and checklists, drive execution, and supervise progress. Be the focal point for place and route integration at the top level. You will need to communicate and drive the needs of PD with cross-functional teams that will enable achieving the goals of the back-end design for the project. Minimum Qualifications: BS + 10 years of relevant experience Experience with ASIC integration including one ### Partner Enablement Manager - Netomi - Location: San Mateo, CA (unspecified) - Salary: Not disclosed - Posted: 2026-06-07 - Apply: https://jobs.lever.co/netomi/92530f98-83fa-4623-a0c6-633650b91514 - Excerpt: Partner Enablement Manager San Mateo, CA About the Company: Netomi is the leading agentic AI platform for enterprise customer experience. We work with the largest global brands like Delta Airlines, MetLife, MGM, United, and others to enable agentic automation at scale across the entire customer journey. Our no-code platform delivers the fastest time to market, lowest total cost of ownership, and simple, scalable management of AI agents for any CX use case. Backed by WndrCo, Y Combinator, and Index Ventures, we help enterprises drive efficiency, lower costs, and deliver higher quality customer experiences. Want to be part of the AI revolution and transform how the world's largest global brands do business? Join us! About the Role: We are looking for a high-energy, execution-oriented Partner Enablement Manager to build and scale our partner enablement function. This role will own the strategy and execution of training, certification, and activation programs that make Netomi a “go-to” solution across our partner ecosystem. Reporting to the VP, Alliances, Partners & Channels, you will work to ensure our partners teams are trained, incentivized, and excited to position and deliver Netomi solutions. This role is critical to scaling Netomi's partner ecosystem-ensuring our partners are not just trained, but activated, aligned, and driving meaningful revenue and customer impact. Responsibilities: Requirements: Who You Are: ### Principal Designer, Mask Design Engineering • Memory Technology - SanDisk - Location: Seoul, Seoul, Korea, republic of (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.smartrecruiters.com/Sandisk/744000126907919-principal-designer-mask-design-engineering-memory-technology - Excerpt: Principal Designer, Mask Design Engineering • Memory Technology Seoul, Seoul, Korea, republic of Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: We are seeking a Principal Designer, Mask Design Engineering specializing in Memory Technology to join our innovative team in Seoul, South Korea. In this Principal Designer role, you will work on module layout design (OPAMP, PUMP, Regulator, etc) for peripheral circuit and working across global teams to enable successful tape‑outs. This role is intended for recognized layout expertise (Standard Cell, Block layout, Block Floor & Signal Planning), ### Clinical Trial Manager - Iovance Biotherapeutics Inc - Location: Remote (remote) - Salary: $145K-$165K - Posted: 2026-06-01 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/iovancebiotherapeutics/jobs/5235729008 - Excerpt: Clinical Trial Manager Remote Iovance Biotherapeutics aims to be the global leader in innovating, developing and delivering tumor infiltrating lymphocyte (TIL) therapy for people with cancer. We are pioneering a transformational approach to treating cancer by harnessing the ability of the human immune system to recognize and attack diverse cancer cells in each patient. The Iovance TIL platform has demonstrated promising clinical data across multiple solid tumors. We are committed to continuous innovation in cell therapy, including gene-edited cell therapy, which may be a promising option for patients with cancer. Overview The Clinical Trial Manager has operations experience within the biotech/biopharma arena. This individual has a high level of core competencies and technical skills to be applied within the management of clinical programs leading to registrational submissions of Biologic License Applications (BLAs). The Clinical Trial Manager position is an opportunity for an individual to join a cross-functional clinical team having high-visible and dynamic input in a therapeutic indication of unmet medical need and orphan disease status. Essential Functions and Responsibilities - Support the overall operational execution of clinical studies on one or more clinical programs from initial study synopsis through final project deliverables (ie, database hard-lock, final TLFs, CSR, etc.) - Manage the implementation, on-time execution and conduct of clinical studies; including the development of budget items, milestones and timelines, in addition to scope and management of resources (including vendor selection). All leading to overall quality, safety, and compliance throughout the duration of the clinical studies and program. - Oversight ### Staff Engineer, Physical Design - Renesas Electronics - Location: Hyderabad, TS, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://jobs.smartrecruiters.com/RenesasElectronics/744000111304225-staff-engineer-physical-design - Excerpt: Staff Engineer, Physical Design Hyderabad, TS, India Company Description: Renesas is one of the top global semiconductor companies in the world. We strive to develop a safer, healthier, greener, and smarter world, and our goal is to make every endpoint intelligent by offering product solutions in the automotive, industrial, infrastructure and IoT markets. Our robust product portfolio includes world leading MCUs, SoCs, Analog and power products, plus Winning Combination solutions that curate these complementary products. We are a key supplier to the world's leading manufacturers of electronics you rely on every day; you may not see our products, but they are all around you. Renesas employs roughly 21,000 people in more than 30 countries worldwide. As a global team, our employees actively embody the Renesas Culture, our guiding principles based on five key elements: Transparent, Agile, Global, Innovative, and Entrepreneurial. Renesas believes in, and has a commitment to, diversity and inclusion, with initiatives and a leadership team dedicated to its resources and values. At Renesas, we want to build a sustainable future where technology helps make our lives easier. Join us and build your future by being part of what's next in electronics and the world. Job Description: We are looking for a Staff/Senior Staff Engineer with deep expertise in Logic Synthesis and/Or Static Timing Analysis (STA). This role involves driving RTL-to-gate-level implementation, timing closure, and optimization for complex SoCs across advanced technology nodes. Key Responsibilities Perform logic synthesis for large-scale ASIC designs using Synopsys Design Compiler and Cadence Genus. ### Senior Associate, Cloud FinOps Engineer - Pfizer - Location: Greece-Thessaloniki Chortiatis (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Parental leave: 12 weeks (not source-backed) - Non-birth-parent leave: 12 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://pfizer.wd1.myworkdayjobs.com/PfizerCareers/job/Greece-Thessaloniki-Chortiatis/Senior-Associate--Cloud-FinOps-Engineer_4959132 - Excerpt: Senior Associate, Cloud FinOps Engineer Greece-Thessaloniki Chortiatis posted: Posted 2 Days Ago ### FPGA Verification Engineer (Level 3 or 4) - Northrop Grumman - Location: United States-Maryland-Linthicum (unspecified) - Salary: $120K-$179K - Posted: 2026-05-12 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Relocation assistance: no (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://ngc.wd1.myworkdayjobs.com/Northrop_Grumman_External_Site/job/United-States-Maryland-Linthicum/FPGA-Verification-Engineer--Level-3-or-4-_R10227618 - Excerpt: FPGA Verification Engineer (Level 3 or 4) United States-Maryland-Linthicum RELOCATION ASSISTANCE: No relocation assistance available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Top Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work - and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history. Join Northrop Grumman Eastern Region Engineering Team on our continued mission to push the boundaries of possible across space systems. Enjoy a culture where your voice is valued and start contributing to our team of passionate professionals providing real-life solutions to our world's biggest challenges. We take pride in creating purposeful work and allowing our employees to grow and achieve their goals every day by Defining Possible. With our competitive pay and comprehensive benefits, we have the right opportunities to fit your life and launch your career today. ### RevOps GTM Systems Architect - Cohere Health - Location: New York (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://jobs.ashbyhq.com/cohere/a03e02e4-76be-4666-a71d-e7b1d51e4a0f - Excerpt: RevOps GTM Systems Architect New York Who are we? Our mission is to scale intelligence to serve humanity. We're training and deploying frontier models for developers and enterprises who are building AI systems to power magical experiences like content generation, semantic search, RAG, and agents. We believe that our work is instrumental to the widespread adoption of AI. We obsess over what we build. Each one of us is responsible for contributing to increasing the capabilities of our models and the value they drive for our customers. We like to work hard and move fast to do what's best for our customers. Cohere is a team of researchers, engineers, designers, and more, who are passionate about their craft. Each person is one of the best in the world at what they do. We believe that a diverse range of perspectives is a requirement for building great products. Join us on our mission and shape the future! RevOps GTM Systems Architect Department: Revenue Operations Function: GTM Systems Location: NYC, SF, Toronto The Revenue Operations team's mission is to build and maintain the systems, data, and processes that power our go-to-market engine. We are looking for a RevOps GTM Systems Architect to join the team, reporting to the Head of Revenue Operations, focused on owning and evolving our full GTM tech stack including Salesforce, Marketo, CPQ, and our ERP integrations. In this role you may: - Own and administer our core GTM platforms: Salesforce CRM, Marketo, CPQ, and supporting tools (e.g., Outreach, ### CPU CDC/RDC/STA Engineer - Apple - Location: Beaverton, United States of America (unspecified) - Salary: $181K-$318K - Posted: 2026-04-14 - 401(k) match: listed (not source-backed) - Apply: https://jobs.apple.com/en-us/details/200657914/cpu-cdc-rdc-sta-engineer?team=HRDWR - Excerpt: CPU CDC/RDC/STA Engineer Beaverton, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, intelligent people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Do you want to join us in these pursuits? Join us to help deliver the next groundbreaking Apple product! As a CPU CDC/RDC/STA Engineer, you will play a major role analyzing the design and driving fixes as well as developing, maintaining and improving our Lint, Clock Domain Crossing (CDC), Reset Domain Crossing (RDC) and Static Timing Analysis (STA) constraints and methodology for our CPUs across multiple design sites. In this role, you will be: • Responsible for developing, improving, and maintaining the CDC and RDC sign-offs for CPU designs • Working with RTL and DV teams to recommend System Verilog assertions needed to support CDC/RDC/STA constraints and assumptions • Highlighting to the RTL team any CDC/RDC issues and recommending solutions to them and educating them on CDC/RDC issues and the importance of structurally safe solutions to each issue • Responsible for developing, enhancing, and maintaining key STA checks and associated sign-offs for ### VP of Operations - Torq - Location: USA (unspecified) - Salary: Not disclosed - Posted: 2026-05-02 - Apply: https://job-boards.greenhouse.io/torq/jobs/5986929004 - Excerpt: VP of Operations USA Skeletons, lasers, tattoo buses - the Torq brand grabs attention like nothing else in cybersecurity. And we're growing like crazy, backed by Series D funding, 200% employee growth, and 300% revenue growth. Fueling Torq's momentum is our game-changing AI SOC platform, backed by a team and culture that makes Torq one of Forbes' Best Startup Employers in America, and a Business Insider 'startup to bet your career on'. Life at Torq is all gas, no brakes. We're a team of relentless, collaborative go-getters pushing the boundaries of what's possible for security automation. Every role is an essential driver of Torq's success as the AI-native autonomous SecOps platform of choice for security teams across the Fortune 500. THE ROLE VP of Operation is a high-impact role that brings together Business Operations, Data, and AI Transformation under one unified leadership charter. This is a seat at the senior leadership table, a direct partnership with the CEO, and a mandate to build the systems, processes, and AI-powered infrastructure that will take Torq from hypergrowth to market leader. You will drive cross-functional operational excellence and build the scalable infrastructure required for the hypergrowth torq is at. WHAT YOU'LL OWN - Lead a world-class team of Business Operations function spanning GTM Operations, Marketing Operations, Sales Operations, and Customer Operations - Design and optimize end-to-end GTM and internal business processes to support scale - Identify and eliminate operational bottlenecks across revenue-generating functions - Set the strategic direction for how data infrastructure evolves ### DevOps Engineer - Schellman - Location: Remote - Nationwide (remote) - Salary: Not disclosed - Posted: 2026-06-10 - 401(k) match: listed (not source-backed) - Apply: https://schellman.wd1.myworkdayjobs.com/Careers/job/Remote---Nationwide/DevOps-Engineer_R-1013-1 - Excerpt: DevOps Engineer Remote - Nationwide posted: ### SOC Emulation Engineer - Hardware Emulation Infrastructure - TensTorrent - Location: Austin, Texas, United States; Santa Clara, California, United States (unspecified) - Salary: Not disclosed - Posted: 2026-03-08 - Apply: https://job-boards.greenhouse.io/tenstorrent/jobs/5070207007 - Excerpt: SOC Emulation Engineer - Hardware Emulation Infrastructure Austin, Texas, United States; Santa Clara, California, United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are seeking a junior-to-mid level SOC Emulation Engineer to support our hardware emulation infrastructure and internal chip design teams. This role focuses on integrating vendor and custom hardware transactors, developing Python-based test frameworks, and providing technical support to emulation users across multiple chip projects. This role is hybrid, based out of Santa Clara, CA or Austin, TX. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - Background in Electrical/Computer Engineering or Computer Science with 1-3 years of experience in chip design, verification, or emulation. - Proficient in Python for automation and test development, with a working knowledge of C++ and the ability to navigate SystemVerilog RTL. - Skilled ### FinOps Team Lead - Amdocs - Location: Israel- RAANANA (Amdocs Site) (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://amdocs.eightfold.ai/careers/job/563431011651669 - Excerpt: FinOps Team Lead Israel- RAANANA (Amdocs Site) ### Design Verification Engineer, PhD, Early Career - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2025-10-17 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckYOBeiohrwR487pnr3iR-XEJHyHsILXPvRCqziwybQrKEjsAbDj5iJUHD57rYn4jjXHgLSc2uXWg26-n-iK47qapqxSLX6j3HgouFCL_DsRK6PyYE3iFJHaEyohaRA%3D%3D_V2&loc=IN&title=Design+Verification+Engineer - Excerpt: Design Verification Engineer, PhD, Early Career Bengaluru, Karnataka, India In this role, you will shape the future of AI/ML hardware acceleration as a Silicon Architect/Design Engineer and drive TPU (Tensor Processing Unit) technology that fuels Google's most demanding AI/ML applications. You will collaborate with hardware and software architects and designers to architect, model, analyze, define and design next-generation TPUs. You will have dynamic, multi-faceted responsibilities in areas such as product definition, design, and implementation, collaborating with the Engineering teams to drive the optimal balance between performance, power, features, schedule, and cost. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs. Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis. Partner with hardware design, software, compiler, Machine Learning (ML) model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces. Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification ### DevOps and Cloud Engineer - Tyler Technologies - Location: Location not specified (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - 401(k) match: listed (not source-backed) - Apply: https://jobs.jobvite.com/tylertech/job/o9iJzfwt - Excerpt: DevOps and Cloud Engineer DevOps and Cloud Engineer ### Principal ASIC Physical Design Engineer - K2 Space - Location: United States- Remote (remote) - Salary: $190K-$280K - Posted: 2026-04-07 - Apply: https://job-boards.greenhouse.io/k2spacecorporation/jobs/5180271008 - Excerpt: Principal ASIC Physical Design Engineer United States- Remote K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply. The Role We are looking for a Principal ASIC Physical Design Engineer to lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow-from RTL handoff to GDSII-and collaborate closely with architecture, RTL design, DFT, and packaging teams. This role also ### VP, Reasoning Systems - Dataiku - Location: United States, New York; United States, Remote (remote) - Salary: $270K-$320K - Posted: 2025-03-27 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/dataiku/jobs/5486496004 - Excerpt: VP, Reasoning Systems United States, New York; United States, Remote Dataiku is the Platform for AI Success, the enterprise orchestration layer for building, deploying, and governing AI. In a single environment, teams design and operate analytics, machine learning, and AI agents with the transparency, collaboration, and control enterprises require. Sitting above data platforms, cloud infrastructure, and AI services, Dataiku connects the full enterprise AI stack - empowering organizations to run AI across multi-vendor environments with centralized governance. The world's leading companies rely on Dataiku to operationalize AI and run it as a true business performance engine delivering measurable value. For more, visit the Dataiku blog , LinkedIn , X , and YouTube . The opportunity: Enterprises are shifting from using data for insight to deploying AI for continuous, high-stakes operational decisions. In many core functions, such as manufacturing operation, supply chain, and financial risk, decision logic has long escaped core systems into fragile custom code and manual processes. Agentic AI intensifies the pressure to change - but also exposes the limits of existing architectures: agent sprawl, rising costs, governance risk. Adding agents on top of legacy workflows does not scale. This creates a new category above agents: Reasoning Systems - domain-specific, end-to-end decision processes that orchestrate data, models, rules, agents, and human judgment around explicit business workflows. Dataiku is uniquely positioned to lead it: already embedded at the data and ML layer of complex, regulated environments, operating as an open control plane across systems, clouds, and AI stacks. The role ### Power and Signal Integrity Engineer, PhD Graduate - Google - Location: Tel Aviv, Israel; +1 more (unspecified) - Salary: Not disclosed - Posted: 2026-02-18 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer - Excerpt: Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical ### Devops Technical Support Intermediate Analyst - Citigroup Inc. - Location: WARSAW, Poland (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://citi.eightfold.ai/careers/job/859034439156 - Excerpt: Devops Technical Support Intermediate Analyst WARSAW, Poland ### Demand Generation Manager - Pave - Location: San Francisco, CA & New York, NY (unspecified) - Salary: $136K-$160K - Posted: 2025-10-28 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4623370005 - Excerpt: Demand Generation Manager San Francisco, CA & New York, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Marketing Team @ Pave You'll be part of a small but mighty marketing team that's scaling rapidly alongside the business. We're looking for a Demand Marketing Manager who can dig into the data, find a gap, and build a plan to drive what's next. You'll be an architect of campaigns that target key personas within the accounts that matter to make Pave a “must have” in their HR tech stack. You'll experiment with different motions to drive new leads, and turn free product users into customer champions. You won't wait for new products to launch; you create demand by telling the right story, at the right time, across all the right ### DevOps Engineer - Sisense - Location: Ukraine (unspecified) - Salary: Not disclosed - Posted: 2026-04-28 - 401(k) match: listed (not source-backed) - Apply: https://www.sisense.com/about/careers/7861157?gh_jid=7861157 - Excerpt: DevOps Engineer Ukraine About Sisense Sisense is a leading AI-powered Analytics Platform as a Service (AnPaaS) that empowers product teams and developers to embed conversational, predictive, and agentic intelligence directly into applications and workflows. Our API-first, developer-first platform turns complex data into faster, smarter, actionable decisions for over 2,000 global customers across financial services, retail, healthcare, and technology. With the recent launch of Sisense Intelligence (Intelligence Assistant, MCP server, Managed LLM), we are accelerating innovation in embedded analytics at scale. The Role As a DevOps Engineer , you will play a key role in designing, building, and maintaining the scalable, reliable infrastructure that powers Sisense's AI-powered embedded analytics platform. You will work on cloud-native environments, CI/CD pipelines, automation, monitoring, and production stability - helping ensure our platform delivers high performance and developer experience at scale. This is a hands-on role with significant ownership and impact on both internal development velocity and customer-facing reliability. Key Responsibilities - Design, implement, and maintain scalable infrastructure for our SaaS platform using modern cloud-native technologies. - Build and improve CI/CD pipelines, automation tools, and deployment processes to increase development velocity and reliability. - Own production environments: monitoring, troubleshooting, performance tuning, and incident response. - Work closely with development teams to support infrastructure needs for new features and services. - Research, evaluate, and introduce new tools and technologies to improve platform efficiency and observability. - Develop and maintain Infrastructure as Code (Terraform, Crossplane, Helm, Argocd, etc.). - Collaborate on improving observability, logging, and alerting across distributed ### Senior Formal Verification Engineer - Waymo - Location: Mountain View, CA, USA (unspecified) - Salary: $204K-$259K - Posted: 2026-02-09 - Apply: https://careers.withwaymo.com/jobs?gh_jid=7593534 - Excerpt: Senior Formal Verification Engineer Mountain View, CA, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Waymo's Compute Team is tasked with a critical and exciting mission: We deliver the compute platform responsible for running the fully autonomous vehicle's software stack. To achieve our mission, we architect and create high-performance custom silicon; we develop system-level compute architectures that push the boundaries of performance, power, and latency; and we collaborate closely with many other teammates to ensure we design and optimize hardware and software for maximum performance. We are a multidisciplinary team seeking curious and talented teammates to work on one of the world's highest performance automotive compute platforms. This role follows a hybrid work schedule and you will report to a Silicon Engineering Lead. You will: - Define and drive formal strategy for first-pass silicon success. Own the formal verification sign-off approach across complex IP and SoC ### Programmable Logic (PL) Engineer - Viasat INC - Location: Carlsbad, California (unspecified) - Salary: $132K-$210K - Posted: 2026-04-09 - 401(k) match: listed (not source-backed) - Apply: https://careers-viasat.icims.com/jobs/5848/login - Excerpt: Programmable Logic (PL) Engineer Carlsbad, California About us One team. Global challenges. Infinite opportunities. At Viasat, we're on a mission to deliver connections with the capacity to change the world. For more than 35 years, Viasat has helped shape how consumers, businesses, governments and militaries around the globe communicate. We're looking for people who think big, act fearlessly, and create an inclusive environment that drives positive impact to join our team. What you'll do In this role you will help develop high speed signal processing algorithms, cryptography, and/or network protocols in FPGAs. The individual will be responsible for the full design phase starting from the requirements phase to documentation, block diagrams, implementation of source code, simulation, place & route, testing in hardware, and integration. The individual will collaborate with other engineers from different fields and must be capable of working in both a small team setting and a larger team setting. Experience in the development of high-performance FPGA designs, network encryptors and cryptographic devices is a plus. The day-to-day Design FPGA module and system level architectures with Verilog and/or VHDL Develop simulations for modules and systems Synthesizes Verilog and/or VHDL to FPGA products Develop timing constraints, analyze timing results, and implement design changes required to close timing Generate and collaborate on required design documents, development requirements, specifications and verification protocols Work closely with hardware and hardware engineers, bringing up boards, interpreting data sheets and schematics Conduct code and design reviews and participate in multi-functional reviews Maintain and control FPGA code ### Senior Physical Design Engineer - TensTorrent - Location: Tokyo, Japan (unspecified) - Salary: Not disclosed - Posted: 2026-04-20 - Apply: https://job-boards.greenhouse.io/tenstorrent/jobs/5104550007 - Excerpt: Senior Physical Design Engineer Tokyo, Japan Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a senior physical design engineer to join Tenstorrent's AIDC Yayoi project, driving chiplet-level and chip-top physical implementation of high-performance CPU-based SoCs in a cutting-edge system-in-package environment. This role is hybrid, based out of Tokyo, Japan. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - You have a Bachelor's, Master's, or PhD in electrical engineering, computer engineering, or computer science, with extensive experience (typically 10+ years) in SoC/ASIC/GPU/CPU physical design on taped-out designs. - You are highly skilled with industry-standard tools (e.g., Synopsys/Cadence) and physical verification, and comfortable scripting in TCL and at least one other language (e.g., Python). - You are a strong collaborator who can guide and mentor junior engineers, communicate clearly with global ### Senior AI Backend Engineer - SumUp - Location: Berlin, Germany (unspecified) - Salary: Not disclosed - Posted: 2026-04-09 - 401(k) match: listed (not source-backed) - Learning budget: yes (not source-backed) - Apply: https://sumup.com/careers/positions/8468006002?gh_jid=8468006002 - Excerpt: Senior AI Backend Engineer Berlin, Germany Team description SumUp Edge is our most ambitious product bet right now - an AI-powered co-pilot that transforms raw merchant data into proactive, real-time business insights. We're moving from being a payments processor to becoming an intelligent operating system for small businesses, and the backend infrastructure powering that shift needs to be world-class. This role sits at the very centre of that build: you'll architect the systems that connect our data platform, LLM orchestration layer, and merchant-facing APIs - and the work you do here will directly shape how millions of small businesses understand and grow their business. We are seeking a skilled and passionate Senior Backend Engineer to help lay the foundations of this vision. In this role, you will design, architect, and develop infrastructure and systems that enables AI products to be successful, and that turn complex, real-world merchant data into scalable, production-grade information for AI solutions. Your expertise in backend and infrastructure combined with AI will be instrumental in shaping the intelligence layer and building sustainable infrastructure that powers our next generation of products. You will collaborate closely with machine learning engineers, data scientists, product managers, and business stakeholders to translate business challenges into robust, high-impact AI capabilities. Your work will directly influence how small businesses operate, compete, and grow, positioning SumUp at the forefront of applied AI in fintech. What you'll do - Architect, design, develop and deploy our AI solutions and systems in production environments, ensuring reliability, high performance ### People Operations Generalist - Pave - Location: San Francisco, CA & Salt Lake City, UT (unspecified) - Salary: $145K-$165K - Posted: 2026-02-13 - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4662284005 - Excerpt: People Operations Generalist San Francisco, CA & Salt Lake City, UT Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The People Team @ Pave We're a strategic, high-impact team that partners directly with leadership to build world-class employee experience and people infrastructure. We own the full employee lifecycle - from offer acceptance through growth and development - and serve as trusted advisors who shape how we support, retain, and develop talent in a competitive market. People Operations isn't just about administering programs. It's about building the systems, culture, and experience that will define how Pave scales and how our team shows up every day. You'll have the tools to succeed, autonomy to innovate on process, and direct exposure to high-impact company-building decisions that shape our culture, compensation philosophy, and how ### Senior Specialist, Supply Chain Management - Apogee Therapeutics Inc - Location: Remote (remote) - Salary: $115K-$130K - Posted: 2026-06-08 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/apogeetherapeutics/jobs/5158901007 - Excerpt: Senior Specialist, Supply Chain Management Remote About Apogee Therapeutics Founded in 2022, Apogee Therapeutics, Inc. (Ticker: APGE) is a well-funded, Nasdaq listed company that offers the opportunity to work in a fast-paced, highly dynamic environment. At Apogee, you can actively contribute to shaping the company culture, take on various roles and responsibilities, and grow professionally. Apogee Therapeutics is a clinical-stage biotechnology company advancing novel biologics with potential for differentiated efficacy and dosing in the largest I&I markets, Apogee's antibody programs are designed to overcome limitations of existing therapies by targeting well-established mechanisms of action and incorporating advanced antibody engineering to optimize half-life and other properties. Zumilokibart (APG777), the company's most advanced program, is being initially developed for the treatment of atopic dermatitis (AD), which is the largest and one of the least penetrated I&I markets, as well as asthma. With four validated targets in its portfolio, Apogee is seeking to achieve best-in-class efficacy and dosing through monotherapies and combinations of its novel antibodies. Based on a broad pipeline and depth of leadership and expertise, the company believes it can deliver value and meaningful benefit to patients underserved by today's standard of care. We are a fast-paced company committed to building an exceptional culture, founded on our C.O.R.E. values: C aring, O riginal, R esilient and E goless and a commitment to refusing to stop at “good enough”. If this sounds like you, keep reading! Role Summary - Review clinical trial synopsis and/or protocols to understand IMP supply and demand requirements. ### Databricks AWS Engineer - Vice President - Citigroup Inc. - Location: PUNE, Mahārāshtra, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://citi.eightfold.ai/careers/job/859035574426 - Excerpt: Databricks AWS Engineer - Vice President PUNE, Mahārāshtra, India ### IT FinOps Data Engineer - Thales - Location: Jakarta, Indonesia (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - 401(k) match: listed (not source-backed) - Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Jakarta/IT-FinOps-Data-Engineer_R0327960-1/apply - Excerpt: IT FinOps Data Engineer Jakarta, Indonesia Join our team as a Senior IT FinOps Data Engineer in Jakarta! Leverage your expertise in Talend, ETL, and cloud data solutions to drive FinOps activities and data transformation. Collaborate with international teams, design robust data pipelines, and help shape the future of cloud operations at Thales. Make a real impact in a dynamic, innovative environment. ### Insights Analyst - Pave - Location: San Francisco, CA & New York, NY (unspecified) - Salary: $115K-$144K - Posted: 2026-06-04 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4703200005 - Excerpt: Insights Analyst San Francisco, CA & New York, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Data Team @ Pave Data is truly at the heart of what we do here at Pave. So, it's no surprise that Pave data team members are integral collaborators and strategic owners with company-wide impact, enabling us to build a stellar product experience. The Insights pod is the team that turns Pave's one-of-a-kind real-time compensation dataset into stories: research reports, market indices, content campaigns, and data products that shape how the market thinks about pay. We're looking for a Data Analyst to join this pod and help us scale our storytelling, serve our customers better, and build the measurement foundation to make smarter decisions about where we invest next. What You'll Do ### ASIC Physical Design Tools, Flows, Methodologies Manager - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $192K-$279K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckdA65qFUzIMVLO_qpz0DNp3VEGiDi--dD76uednIOm7mEjsACxwdTGTK8Ty7-tc9OpPxcMp3gpC2QfV58Ip69SKMasdvH2uZn6ZCXIhkWceu3r0ksfD-cHEB3yQhqA%3D%3D_V2&loc=US&title=ASIC+Physical+Design+Tools - Excerpt: ASIC Physical Design Tools, Flows, Methodologies Manager Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. In this role, you will manage and lead a team of TFM engineers responsible for the physical design flows that power our Tensor Processing Unit (TPU) products. You will guide your team in developing, deploying, and supporting a register-transfer level (RTL)-to-GDS infrastructure. You will bridge design engineering and electronic design automation (EDA) capabilities, balancing resources and managing priorities across projects, feature requests, and bug resolutions to ensure silicon delivery. Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible. Individual pay is determined by ### Unisys Technical Support/Application Support - Dine Development Corporation - Location: Remote (remote) - Salary: Not disclosed - Posted: 2026-05-12 - Apply: https://ddcdine.wd501.myworkdayjobs.com/DDC_Careers/job/Remote/Unisys-Technical-Support-Application-Support_JR100008 - Excerpt: Unisys Technical Support/Application Support Remote posted: Posted 30+ Days Ago ### Clinical Trial Manager - Crinetics Pharmaceuticals INC - Location: Remote (remote) - Salary: $122K-$152K - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://crinetics.wd12.myworkdayjobs.com/CrineticsCareers/job/Remote/Clinical-Trial-Manager_JR000623 - Excerpt: Clinical Trial Manager Remote Position Summary: The Clinical Trial Manager is responsible for managing the execution of clinical studies and data collection. The incumbent oversees the review, monitoring and adherence to clinical protocols, as well as fulfilling activities related to study completion. The Clinical Trial Manager will interact internally and externally with members of the cross-functional study team. Essential Job Functions and Responsibilities: These may include but are not limited to: Provide oversight of clinical research studies across all functional areas of the drug development process. Provide operational and strategic input into study documents such as synopsis, protocol, ICF, CRFs, CRF Completion Guidelines, Study Execution Plans, Clinical Data Review Plan, Clinical Database edit specifications, Clinical Study Report (CSR) development, etc. Develop the subject recruitment/retention strategy and related initiatives. Oversight of TMF set-up, ongoing quality review, and final reconciliation of study documents including review of site regulatory documents/packages and obtaining of appropriate site insurance, and/or supervision of team members performing these activities. Development of training materials for study team, investigational sites, and vendors. Proactive management of information sharing with key stakeholders using standardized reports and other mechanisms. Assure clinical studies are compliant with ICH/GCP and other regulations as appropriate. Oversee preparation of RFPs and prepare bid templates to facilitate selection of the CROs/vendors, and/or collaboration/supervision with team members performing these activities. Collaborate with counsel to negotiate and draft research contracts and agreements with CROs/vendors and clinical study sites, as needed. Acts as liaison with Regulatory Affairs to assure adherence to GCPs; ### FinOps Program Manager, AI Enablement - Stripe - Location: IN-Bengaluru (unspecified) - Salary: Not disclosed - Posted: 2026-06-07 - Non-birth-parent leave: 16 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Fertility benefits: yes (not source-backed) - Childcare support: yes (not source-backed) - Apply: https://stripe.com/jobs/search?gh_jid=7975826 - Excerpt: FinOps Program Manager, AI Enablement IN-Bengaluru Who we are About Stripe Stripe is a financial infrastructure platform for businesses. Millions of companies-from the world's largest enterprises to the most ambitious startups-use Stripe to accept payments, grow their revenue, and accelerate new business opportunities. Our mission is to increase the GDP of the internet, and we have a staggering amount of work ahead. That means you have an unprecedented opportunity to put the global economy within everyone's reach while doing the most important work of your career. About the team The FinOps organization at Stripe is responsible for the financial operations that sustain our business at scale. It comprises five specialized service teams: Accounts Payable (AP)-managing supplier invoices, vendor payments, and procurement workflows Accounts Receivable (AR)-overseeing customer billing, collections, and revenue operations Travel and Expense (T&E)-managing employee expense processes and ensuring policy compliance Payroll-guaranteeing accurate and timely compensation for Stripe employees Monetization Operations (MonOps)-handling unique billing arrangements with our largest clients Supporting all five of these teams is FinOps Strategic Enablement-a dedicated function aimed at driving efficiency, scalability, and strategic value across the entire FinOps organization. This team provides expertise in process design, data management, and increasingly, artificial intelligence. As AI capabilities advance, FinOps Strategic Enablement is strategically investing in resources to ensure our service teams can fully harness these tools. This role is pivotal to achieving that objective. What you'll do We're seeking a FinOps Program Manager to act as a strategic catalyst for positive change. This high-impact position focuses ### DevOps Engineer (Smart Delivery) - Thales - Location: Bucharest, Romania (unspecified) - Salary: Not disclosed - Posted: 2026-03-10 - 401(k) match: listed (not source-backed) - Apply: https://thales.wd3.myworkdayjobs.com/Careers/job/Bucharest/DevOps-Engineer--Smart-Delivery-_R0317043/apply - Excerpt: DevOps Engineer (Smart Delivery) Bucharest, Romania Join our team as a DevOps Engineer and play a crucial role in designing and maintaining CI/CD pipelines. Collaborate with talented engineers, utilize cutting-edge technologies, and drive innovation in a dynamic environment. If you have a passion for DevOps and cloud services, we want to hear from you! ### Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design) - SanDisk - Location: Bengaluru, KA, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.smartrecruiters.com/Sandisk/744000120194599-principal-engineer-asic-development-engineering-io-and-high-speed-design- - Excerpt: Principal Engineer, ASIC Development Engineering (IO and High‑Speed Design) Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: Principal Engineer will contribute to the design and development of IO and high‑speed interface solutions for next‑generation SoCs in advanced CMOS technology nodes. Participate in the design, and implementation of IO and high‑speed interface solutions for SanDisk ASIC controllers. Evaluate design approaches, implement blocks at the circuit and RTL levels as applicable, perform detailed analysis, and drive design closure with focus on quality and schedule. Collaborate with layout ### CAD/IP/Infrastructure Engineer - Cisco - Location: Armenia (unspecified) - Salary: Not disclosed - Posted: 2026-05-15 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Engineer_2005399 - Excerpt: CAD/IP/Infrastructure Engineer Armenia Meet the Team The Common Hardware Group (CHG) delivers silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One (#CiscoSiliconOne) is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches all the way through web scale data centers and across service provider, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed in the industry. Your Impact We are seeking a highly motivated engineer to join CAD & Methodology Team. The candidate will play a critical role in ensuring that ASIC projects are fully enabled with vendor IPs, standard cells, and Process Design Kits (PDKs), working closely with both internal teams and external vendors to drive enablement and management of essential components. Key Responsibilities: Develop the platform for IP/PDK installations Develop a platform for IP quality assurance Execute custom cells characterization and model generation with quality validation. Establish and maintain efficient IP management methodologies, including version control, qualification, and distribution. Collaborate with IP vendors and foundries to facilitate IP and PDK enablement for ASIC projects. Benchmarking of different vendor/technology IPs Manage the integration, validation, and release of vendor IPs ### ​​Senior MLOps Engineer​ - Leidos - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://leidos.wd5.myworkdayjobs.com/External/job/Alexandria-VA/XMLNAME---Senior-MLOps-Engineer-_R-00177219 - Excerpt: ​​Senior MLOps Engineer​ 2 Locations posted: Posted 30+ Days Ago ### Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) - SanDisk - Location: Bengaluru, KA, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.smartrecruiters.com/Sandisk/744000126659825-principal-engineer-asic-development-engineering-mixed-signal-ip-layout- - Excerpt: Principal Engineer, ASIC Development Engineering (Mixed-Signal IP Layout) Bengaluru, KA, India Company Description: Sandisk understands how people and businesses consume data and we relentlessly innovate to deliver solutions that enable today's needs and tomorrow's next big ideas. With a rich history of groundbreaking innovations in Flash and advanced memory technologies, our solutions have become the beating heart of the digital world we're living in and that we have the power to shape. Sandisk meets people and businesses at the intersection of their aspirations and the moment, enabling them to keep moving and pushing possibility forward. We do this through the balance of our powerhouse manufacturing capabilities and our industry-leading portfolio of products that are recognized globally for innovation, performance and quality. Sandisk has two facilities recognized by the World Economic Forum as part of the Global Lighthouse Network for advanced 4IR innovations. These facilities were also recognized as Sustainability Lighthouses for breakthroughs in efficient operations. With our global reach, we ensure the global supply chain has access to the Flash memory it needs to keep our world moving forward. Job Description: We are looking for technically sound and highly skilled Analog/High Speed DDR IO Layout designer with 8-12 years of experience. The ideal candidate should have a strong background in analog/IO design principles, hands-on experience with layout tools, and a passion for solving challenging technical problems. Key Responsibilities: Develop and optimize MSIP IC layouts in TSMC 3nm, ensuring high performance and manufacturability. Collaborate with design engineers to understand design requirements ### DevOps Engineer (Rhode Island) - Torq - Location: Providence, Rhode Island, United States (unspecified) - Salary: Not disclosed - Posted: 2026-06-02 - Apply: https://job-boards.greenhouse.io/torq/jobs/6010965004 - Excerpt: DevOps Engineer (Rhode Island) Providence, Rhode Island, United States Skeletons, lasers, tattoo buses - the Torq brand grabs attention like nothing else in cybersecurity. And we're growing like crazy, backed by Series D funding, 200% employee growth, and 300% revenue growth. Fueling Torq's momentum is our game-changing AI SOC platform, backed by a team and culture that makes Torq one of Forbes' Best Startup Employers in America, and a Business Insider 'startup to bet your career on'. Life at Torq is all gas, no brakes. We're a team of relentless, collaborative go-getters pushing the boundaries of what's possible for security automation. Every role is an essential driver of Torq's success as the AI-native autonomous SecOps platform of choice for security teams across the Fortune 500. We're looking for a DevOps Engineer to join our fast-growing company at a breakthrough stage - building our dream team with the most passionate and professional people in the industry. This is a US-based position, joining a global DevOps team primarily based in Israel. We're looking for someone highly independent, adaptable, and proactive - a self-starter who thrives in a fast-moving environment and can collaborate effectively across time zones. Our team thinks differently and moves quickly, delivering high-quality, innovative solutions using the latest technologies and frameworks - all while enjoying the ride! What You'll Be Doing: - Champion a DevOps mindset: Identify friction points and implement scalable automation to improve reliability, delivery speed, and developer experience. - Operate and optimize production environments: Use infrastructure as ### ASIC Engineer Internship (Armenia) - Cisco - Location: Armenia (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Engineer-Internship--Armenia-_2009839 - Excerpt: ASIC Engineer Internship (Armenia) Armenia Please note this posting is to advertise potential job opportunities. This exact role may not be open today but could open in the near future. When you apply, a Cisco representative may contact you directly if a relevant position opens. Meet the Team Join our specialized ASIC implementation team where we bridge the gap between architectural design and physical silicon reality. Our team provides a structured, mentorship-driven environment focused on block-level and top-level physical implementation, timing closure, and physical verification. We work at the heart of Cisco's hardware innovation, ensuring that our next-generation semiconductor technologies are reliable, efficient, and high-performing. You will collaborate with experienced engineers who are passionate about teaching and pushing the boundaries of VLSI technology. This is an exciting opportunity to gain hands-on experience with industry-standard tools while contributing to the hardware that powers the global internet. Your Impact Support physical design tasks including floorplanning, placement, and routing to ensure efficient ASIC implementation. Participate in Static Timing Analysis (STA) and timing closure activities to meet critical design performance specifications. Assist in IR Drop and EMIR analysis to maintain power integrity and long-term reliability of the hardware. Perform physical verification checks such as DRC and LVS to guarantee manufacturing readiness and design rule compliance. Prepare technical documentation and reports to communicate progress and findings to the broader engineering team. Minimum Qualifications • Currently enrolled in a Bachelor's or Master's program in Microelectronics, VLSI, Electrical Engineering, or a related field. • Strong academic foundation ### Revenue Operations (RevOps) - Raspberry AI - Location: United States (unspecified) - Salary: Not disclosed - Posted: 2026-04-09 - Apply: https://jobs.ashbyhq.com/raspberry/b614e5cc-5f90-41ec-92aa-78d20814e04e - Excerpt: Revenue Operations (RevOps) United States Revenue Operations (RevOps) About Raspberry AI Raspberry AI is a generative AI design platform built for fashion brands and retailers. We help design, merchandising, and product development teams move faster - from concept to market-ready assets - using industry-leading AI. Some of the world's top fashion brands rely on Raspberry AI to streamline their workflows and accelerate product development. We are a Series A company backed by Andreessen Horowitz, Khosla Ventures, and Greycroft , with growing enterprise traction across leading global brands. As we scale, we're building the systems and infrastructure to support a high-performing, data-driven GTM engine. About the Role We're hiring a Revenue Operations professional to build and scale the operational backbone of Raspberry's go-to-market motion. This role will sit at the intersection of Sales, Marketing, Customer Success, and Finance , owning the systems, processes, and data that drive pipeline visibility, forecasting accuracy, and revenue performance. You'll be responsible for creating structure where it doesn't yet exist-owning CRM, reporting, pipeline hygiene, and core GTM processes-while partnering closely with Sales leadership to enable smarter, faster decision-making. This is a hands-on builder role for someone who thrives in early-stage environments and wants to shape how a modern AI company runs its revenue engine. Responsibilities CRM & Systems Ownership - Own and optimize Salesforce (or equivalent CRM) architecture, workflows, and data integrity - Build and maintain dashboards for pipeline, forecasting, and performance tracking - Manage integrations across GTM tools (CRM, marketing automation, billing, etc.) - Ensure ### Senior CloudOps Engineer - Tyler Technologies - Location: Location not specified (unspecified) - Salary: Not disclosed - Posted: 2026-06-10 - 401(k) match: listed (not source-backed) - Apply: https://jobs.jobvite.com/tylertech/job/ogtLzfwN - Excerpt: Senior CloudOps Engineer Senior CloudOps Engineer ### Technical Recruiter - Pave - Location: San Francisco, CA (unspecified) - Salary: $155K-$170K - Posted: 2026-04-16 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4685654005 - Excerpt: Technical Recruiter San Francisco, CA Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Recruiting Team @ Pave We're a small, high-leverage team - two recruiters and a dedicated coordinator - operating as trusted advisors to leadership on every major hiring decision. We own full-cycle recruiting across all levels and have real influence on how we attract and win top talent in a competitive market. Recruiting at Pave comes with a unique advantage: you'll have direct access to the same live compensation benchmarking data our customers use to make pay decisions. That means you can walk any candidate through exactly where our offers land in the market - with real data, full transparency, and genuine confidence. It's a closing tool most recruiters never get to use. We're also in the ### DFT Engineer, Google Cloud - Google - Location: Sunnyvale, CA, USA (unspecified) - Salary: $138K-$198K - Posted: 2026-06-05 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckbHGgLSiu4Qw0Ctr5P48kdwR9d8Dmv09N_AsBULxBn6uEjsACxwdTPRUsrC2OBEfu463es0I3b-BPXtac0lEf6QAbqcNIDKE9b4YdhOFujhyQ07I2s7PxuTRj3IRcA%3D%3D_V2&loc=US&title=DFT+Engineer - Excerpt: DFT Engineer, Google Cloud Sunnyvale, CA, USA In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. As a DFT Engineer, you will be responsible for defining, implementing and deploying advanced design-for-test (DFT) methodologies including Scan, MBIST, JTAG and iJTAG, for highly complex digital or mixed-signal chips or IPs. You will define DFT architecture, and create DFT flows for complex next generation SoCs in partnership with the Design and Physical Design teams. You will also be responsible for design verification of test logic, test pattern generation and debugging and test coverage issues. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From ### MLOps Manager - Aptiv - Location: Bangalore, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://aptiv.wd5.myworkdayjobs.com/APTIV_CAREERS/job/Bangalore-India/MLOps-Manager_J000697495 - Excerpt: MLOps Manager Bangalore, India posted: Posted 30+ Days Ago ### FinOps Manager - Bayer - Location: Warszawa,Mazowieckie,Poland (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://talent.bayer.com/careers/job/562949977256372 - Excerpt: FinOps Manager Warszawa,Mazowieckie,Poland ### ASIC Physical Design CAD Engineer - Cisco - Location: 2 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-07 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Caesarea-Israel/CAD-Engineer_2009617 - Excerpt: ASIC Physical Design CAD Engineer 2 Locations Job Description Silicon One is seeking a CAD Engineer to join the Cisco Silicon One Physical Design team. Meet the Team You'll be part of the Cisco Silicon One team, which is at the heart of Cisco's software and ASIC design efforts. As part of our team, you'll contribute to the development of our next-generation network devices-Cisco Silicon One™. Our team operates in a startup-like environment within a stable and leading corporation. Our design center is uniquely equipped, hosting all silicon hardware and software development fields under one roof. We are revolutionizing the industry by building a new internet for the 5G era, providing a unified, programmable silicon architecture that serves as the foundation for all of Cisco's future routing products. Our devices are designed to be universally adaptable across service providers and web-scale markets, catering to both fixed and modular platforms. They deliver high speed without compromising on programmability, buffering, power efficiency, scale, or feature flexibility. Cisco Silicon One is a ground-breaking, groundbreaking technology that will serve our customers and end users for decades to come. The Internet now has a new, faster, better, and safer engine! Your Impact You'll be joining our Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This is a critical part of the group leading the development of high-quality VLSI designs. Our Backend Engineers handle all aspects of chip design, including Definition, Physical ### Senior Software Engineer - Data Platform - Pave - Location: Krakow, Poland (unspecified) - Salary: Not disclosed - Posted: 2026-03-26 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4677919005 - Excerpt: Senior Software Engineer - Data Platform Krakow, Poland Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Data Platform Team @ Pave The Data Platform team owns the data infrastructure that makes Pave work - connecting Pave's platform to the HRIS, EMS, ATS, and partner systems that power our customers' compensation workflows. Without reliable, high-quality integrations, none of Pave's products can deliver their full value. This is a high-leverage role at the core of Pave's platform strategy. This is also a rare opportunity to join as a founding engineer on the team - meaning you won't just be executing on a defined roadmap, but actively shaping how the platform evolves, what gets prioritized, and what engineering culture looks like from day one. As a Senior Software Engineer on the Data ### Cloud DevOps Engineer Technical Mentor - Independent Contractor (US Canada, Europe, MENA, India & APAC Timezones) - Udacity - Location: Remote (remote) - Salary: Not disclosed - Posted: 2021-12-24 - Apply: https://job-boards.greenhouse.io/udacity/jobs/5791251002 - Excerpt: Cloud DevOps Engineer Technical Mentor - Independent Contractor (US Canada, Europe, MENA, India & APAC Timezones) Remote About Us Udacity is now an Accenture company, and exciting things are happening! 🚀 We are on a mission of forging futures in tech through radical talent transformation in digital technologies. We offer a unique and immersive online learning platform, powering corporate technical training in fields such as Artificial Intelligence, Machine Learning, Data Science, Autonomous Systems, Cloud Computing and more. Our rapidly growing global organization is revolutionizing how the enterprise market bridges the talent shortage and skills gaps during their digital transformation journey. Recognized for its innovative impact, Udacity part of Accenture continues to empower people with the skills they need to secure the jobs they want. we are committed to providing high-quality upskilling opportunities in this rapidly evolving field. We regularly launch new projects and are seeking experienced mentors to join us as external contractors to support our programs and learners. As new initiatives arise, we will reach out to qualified candidates within this talent pool to provide details on project scope, expected timelines, and compensation. If you are passionate about tackling meaningful challenges and making a difference we invite you to apply and explore this opportunity to collaborate with us. You'll be an excellent fit if you have: - Proven technical expertise with 5+ years of experience in the relevant field - A passion for mentoring and helping others succeed in their learning - Excellent interpersonal skills. You enjoy building relationships, ### Configuration Consultant - RTSM - Veeva Systems - Location: Croatia - Zagreb (unspecified) - Salary: EUR 36K-55K - Posted: 2023-04-19 - 401(k) match: listed (not source-backed) - Apply: https://jobs.lever.co/veeva/a3058d06-ade4-439b-a779-11651c40988c - Excerpt: Configuration Consultant - RTSM Croatia - Zagreb Veeva Systems is a mission-driven organization and pioneer in industry cloud, helping life sciences companies bring therapies to patients faster. As one of the fastest-growing SaaS companies in history, we surpassed $3B in revenue in our last fiscal year with extensive growth potential ahead. At the heart of Veeva are our values: Do the Right Thing, Customer Success, Employee Success, and Speed. We're not just any public company - we made history in 2021 by becoming a public benefit corporation (PBC), legally bound to balancing the interests of customers, employees, society, and investors. As a Work Anywhere company, we support your flexibility to work from home or in the office, so you can thrive in your ideal environment. Join us in transforming the life sciences industry, committed to making a positive impact on its customers, employees, and communities. The Role Veeva Systems, a leader in cloud-based solutions for the global life sciences industry, is looking for a Configuration Consultant to join our RTSM (Randomization and Trial Supply Management) team. The Configuration Consultant will configure RTSM projects based on the agreed-upon study requirements quickly and with the highest quality. This position requires great attention to detail. This is a full-time, exempt, position. Days and hours of work are generally Monday through Friday, 9:00 AM to 5:00 PM; however, hours are dependent on customer needs and deliverables. The Role Veeva Systems, a leader in cloud-based solutions for the global life sciences industry, is looking for ### Physical Design Engineer - Etched - Location: Austin (unspecified) - Salary: Not disclosed - Posted: 2026-04-16 - Mental health support: yes (not source-backed) - Apply: https://jobs.ashbyhq.com/etched/e194099a-b7c0-4aa7-9e6d-06a666de6275 - Excerpt: Physical Design Engineer Austin About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary Etched is looking for exceptional Physical Design engineers to join our team. In this role, you will own block-level implementation and verification, drive timing closure and PPA optimization, supervise 3rd party design work, and help improve our design flows and iteration speed. Key Responsibilities - Deeply understand what is involved in physical design - Running PD flows to close blocks, support ASIC infrastructure, automate PD flows, improve CAD infrastructure - Collaborate with RTL Designers and provide Physical Design feedback to improve PPA - Drive dashboards that show the convergence of projects related to PD - Optimize tool flows, working with EDA vendors to incorporate the latest features - Accountable for block level closure - Supervise the outsourcing of physical design to a 3rd party service You may be a good fit if you have - 5-10+ years of previous experience with PD - Tools, flow, and design methodology from RTL synthesis to GDSII sign-off - Experience with back-end design and timing closure on ### DevOps Engineer - Eurofins Scientific - Location: Nantes, Pays de la Loire, France (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://jobs.smartrecruiters.com/Eurofins/744000092964165-devops-engineer - Excerpt: DevOps Engineer Nantes, Pays de la Loire, France Company Description: Why are we here? Eurofins Scientific is an international life sciences company, providing a unique range of analytical testing services to clients across multiple industries, to make life and our environment safer, healthier and more sustainable. From the food you eat, to the water you drink, to the medicines you rely on, Eurofins laboratories work with the biggest companies in the world to ensure the products they supply are safe, their ingredients are authentic, and labelling is accurate. Eurofins is dedicated to delivering testing services that contribute to the health and safety of society and the planet, and to its corporate responsibility to protect the environment and ensure diversity, equity, and inclusion across the entire network of Eurofins companies. Job Description: In a nutshell As a DevOps Engineer, you will act as the liaison between cloud architects and regional and local IT teams as well as local business stakeholders. Based on the knowledge, you will help application teams modernize their applications to suit cloud-based deployment and modern authentication. Where will you be based and what business will you support? Based in Nantes, France; you will be part of a globally distributed team that supports and operate IT Infrastructure for two of our major programmes (Appolo & eClinical IT Applications). How can you help us? You will: • Design and implement cloud-based solutions on Azure, AWS & OpenStack; • Manage and optimize multiple Kubernetes clusters (AKS, EKS, Rancher); • Implement and ### Senior DFT Engineer, Architecture - TensTorrent - Location: Tokyo, Japan (unspecified) - Salary: Not disclosed - Posted: 2024-11-05 - Apply: https://job-boards.greenhouse.io/tenstorrent/jobs/4556198007 - Excerpt: Senior DFT Engineer, Architecture Tokyo, Japan Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Job title Senior DFT Engineer Job description We are looking for a person ready to take up the challenge of working in a high-profile project where we design and integrate multiple chiplets into a System-in-package, in collaboration with external stakeholders. You will work with Tenstorrent worldwide experts and leaders in the USA, Japan and other countries, and help us make our IP even better. In this role, you will be responsible for DFT implementation using industry standard tools for high-speed CPU core design. Your responsibilities Integrate and verify test features in digital designs for effective manufacturing testing and silicon debug. Key responsibilities include: - Building entire chip-level DFT strategies - Inserting DFTs, including scan chains, memory BIST, and JTAG - Collaborating with RTL, physical design, and verification teams for testability throughout the design flow - Scripting and automating DFT flows using industry-standard EDA tools (e.g., Cadence, Synopsys, Siemens) - Running and analyzing ### ASIC Design Hardware Engineer - SDC/STA (Hybrid) - Cisco - Location: San Jose, California, US (hybrid) - Salary: $165K-$241K - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineer---SDC_2011128 - Excerpt: ASIC Design Hardware Engineer - SDC/STA (Hybrid) San Jose, California, US The application window is expected to close on: 05/15/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you live within commuting distance of our San Jose, CA office and commute to the office 4-5 days per week. MEET THE TEAM Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. You will work with exceptional talent with vast ASIC design and development expertise. With Cisco being a systems company, you will also have an opportunity to work with other ASIC teams in the journey of taking it from concept to first customer shipments. YOUR IMPACT You are a diligent Design/SDC Engineer with strong analytical skills and a deep understanding of timing constraints, including clock groups, exceptions, and clock exclusivity. Proficient in industry-standard SDC/STA tools and scripting for automation, you excel at identifying and resolving timing issues across all design levels. You will develop timing constrains at both block level and full-chip and validate them using industry standard timing constraints ### DevOps Engineer - Leidos - Location: 2223 Chester House Farnborough Aerospace Centre Farnborough UK (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - Parental leave: 4 weeks (not source-backed) - Non-birth-parent leave: 4 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://leidos.wd5.myworkdayjobs.com/External/job/2223-Chester-House-Farnborough-Aerospace-Centre-Farnborough-UK/DevOps-Engineer_R-00182824 - Excerpt: DevOps Engineer 2223 Chester House Farnborough Aerospace Centre Farnborough UK posted: Posted 30+ Days Ago ### Senior Pyspark Data Engineer - Assistant Vice President - Citigroup Inc. - Location: MISSISSAUGA, Ontario, Canada (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://citi.eightfold.ai/careers/job/859034899255 - Excerpt: Senior Pyspark Data Engineer - Assistant Vice President MISSISSAUGA, Ontario, Canada ### Principal Analog EDA Design Automation Engineer - Maxlinear Inc - Location: Irvine, CA, US (unspecified) - Salary: $145K-$190K - Posted: 2026-06-10 - Apply: https://careersus-maxlinear.icims.com/jobs/2972/principal-analog-eda-design-automation-engineer/job - Excerpt: Principal Analog EDA Design Automation Engineer Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Analog EDA Design Automation Engineer to join our team. In this role, you will focus on the following: Develop, maintain, and support the MaxLinear Analog/RF Project Environment, including EDA tools, PDK, and custom scripts Working with design and layout teams to optimize workflows, automating tasks with scripting, installing and managing EDA tools (Cadence, Mentor, Synopsys), and supporting IC design engineers by maintaining tools, licenses, and servers Lead innovation and enablement of custom analog/rf design methodology and solutions to address critical design challenges in cutting-edge technologies Drive AI adoption in analog IC design to enhance efficiency by automating labor-intensive tasks like circuit sizing, layout, and technology migration, reducing turnaround times from weeks to days Create documentation and provide hands-on training for design and layout engineers Work with EDA vendors to track and resolve issues Mentor and train new employees on MaxLinear Design Flows Understand overall IC design flow and experience in developing tools and methods for cycle time reduction Develop software for automation in Skill, Perl, Unix Shell scripting Qualifications Experience with Cadence Virtuoso Studio Environment, front-end and back-end tools such as Virtuoso, Spectre, Maestro, Layout Environment(s) Experience with Siemens Calibre Physical Verification Tools, Solido Simulation Environment Proficient in Linux Environment, ### Sr. SE (Partner) - CloudBees - Location: United Kingdom / Ireland (unspecified) - Salary: Not disclosed - Posted: 2026-03-30 - 401(k) match: listed (not source-backed) - Apply: https://recruiting.paylocity.com/Recruiting/Jobs/Details/4042382 - Excerpt: Sr. SE (Partner) United Kingdom / Ireland Sr. SE (Partner) ### Enterprise Account Executive - Pave - Location: San Francisco, CA & New York, NY (unspecified) - Salary: Not disclosed - Posted: 2025-11-19 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4632306005 - Excerpt: Enterprise Account Executive San Francisco, CA & New York, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Sales Team @ Pave As an Enterprise Account Executive at Pave, you'll be at the forefront of revolutionizing how companies approach compensation. Working directly with HR and Finance executives, you'll help shape the future of compensation technology while playing a crucial role in our go-to-market strategy. As one of our Enterprise AEs, you'll have the unique opportunity to influence product direction and scale our enterprise motion while working alongside founders, investors, and industry leaders. What You'll Be Doing: - Drive complex, multi-threaded sales cycles with strategic prospects, focusing on six-figure deals that expand Pave's compensation network - Partner with prospects' HR and Finance leadership to understand their compensation challenges and demonstrate ### Consultant - LIMS - Veeva Systems - Location: North Carolina - Raleigh (unspecified) - Salary: $70K-$140K - Posted: 2025-10-03 - 401(k) match: listed (not source-backed) - Apply: https://jobs.lever.co/veeva/152408ea-8ab1-428a-9fe9-589c461d382d - Excerpt: Consultant - LIMS North Carolina - Raleigh Veeva Systems is a mission-driven organization and pioneer in industry cloud, helping life sciences companies bring therapies to patients faster. As one of the fastest-growing SaaS companies in history, we surpassed $3B in revenue in our last fiscal year with extensive growth potential ahead. At the heart of Veeva are our values: Do the Right Thing, Customer Success, Employee Success, and Speed. We're not just any public company - we made history in 2021 by becoming a public benefit corporation (PBC), legally bound to balancing the interests of customers, employees, society, and investors. As a Work Anywhere company, we support your flexibility to work from home or in the office, so you can thrive in your ideal environment. Join us in transforming the life sciences industry, committed to making a positive impact on its customers, employees, and communities. The Role Join Veeva as we modernize software for the life sciences industry. We are bringing to market a modern cloud solution designed to optimize laboratories with increased efficiency and productivity by streamlining processes. Join the team that will partner with our customers to implement one of Veeva's newest products - Veeva Vault LIMS. We are looking for hard-working individuals who are committed to helping our customers adopt the next generation of technology. We will bring new efficiencies to our customers with the most advanced GPM QC-focused LIMS by providing all functionality in a single platform. This role will allow you to be in the ### Commercial Account Executive - Pave - Location: San Francisco, CA & New York, NY (unspecified) - Salary: Not disclosed - Posted: 2025-11-19 - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4632215005 - Excerpt: Commercial Account Executive San Francisco, CA & New York, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Sales Team @ Pave Pave's sales team is looking for a driven Commercial Account Executive to help accelerate our growth and expand our compensation network. As an AE, you'll play a pivotal role in our go-to-market strategy, working directly with HR and Finance leaders to revolutionize how companies approach compensation. This role offers unique exposure to founders, investors, and industry leaders while helping shape the future of compensation technology. What You'll Do - Own the full sales cycle from discovery through close, building relationships with HR and Finance decision-makers - Drive consultative sales processes that help prospects understand and solve their compensation challenges - Collaborate with product and customer success teams ### DEVOPS / OPERATIONS ENGINEER - eSIM PLATFORM - VOIS - Vodafone Group - Location: Pune, Maharashtra, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://vodafone.eightfold.ai/careers/job/563018696822780 - Excerpt: DEVOPS / OPERATIONS ENGINEER - eSIM PLATFORM - VOIS Pune, Maharashtra, India ### AI Engineer - Pave - Location: San Francisco, CA & New York, NY (unspecified) - Salary: $167K-$225K - Posted: 2026-02-11 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4660955005 - Excerpt: AI Engineer San Francisco, CA & New York, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Eng Team @ Pave Pave's AI compensation analyst - an agentic system that sits on top of the world's largest proprietary compensation dataset and Pave's existing workflow engine. Think: autonomous agents that can reason over structured compensation data and execute multi-step workflows (market pricing, cycle planning, attrition analysis) across Pave's platform. In this role, you'll shape the technical vision and execution, working with a team of engineers and data scientists to build the product end-to-end and take it to market. This role requires deep AI expertise, strong product intuition, and a founder mentality. What You'll Bring - 3+ years building production systems, with hands-on experience working with LLMs, agentic architectures, and retrieval ### Python and Pyspark Developer - Assistant Vice President - Citigroup Inc. - Location: IRVING, Texas, United States of America | TAMPA, Florida, United States of America (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://citi.eightfold.ai/careers/job/859032800006 - Excerpt: Python and Pyspark Developer - Assistant Vice President IRVING, Texas, United States of America | TAMPA, Florida, United States of America ### Transportation Specialist I, ROC - Amazon - Location: Bengaluru, Karnataka, IND (unspecified) - Salary: Not disclosed - Posted: 2026-03-25 - Parental leave: 6 weeks (not source-backed) - Non-birth-parent leave: 6 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.amazon.jobs/en/jobs/10375539/transportation-specialist-i-roc - Excerpt: Transportation Specialist I, ROC Bengaluru, Karnataka, IND About Amazon ROC (Relay Operation Centre): Join a team that offers best learning opportunities and work experience in transportation execution, supply chain and operations management. A place where you can start/restart/advance your career and progress to leadership roles at Amazon. ROC (Relay Operation Center) is the central command and control center for 'Transportation Execution' across the Amazon Supply Chain network supporting multiple geographies like NA and EU. It ensures hassle free, timely pick-up and delivery of freight from vendors to Amazon fulfillment centers (FC) and from Amazon FCs to carrier hubs. In case of any exceptions, ROC steps in to resolve the issue and keeps all the stakeholders informed on the proceedings. In addition to support provided for ATS organization This organization supports externalization of ROC capabilities to external shippers and vendors. Along with this tactical problem-solving ROC is also charged with understanding trends in network exceptions and then automating processes or proposing process changes to streamline operations. This second aspect involves network monitoring and significant analysis of network data. Overall, ROC plays a critical role in ensuring the smooth functioning of Amazon transportation network and thereby has a direct impact on Amazon's ability to serve its customers on time. Location: Bangalore, KA IND Hours of Operation/Shift Timings: Rotational shifts (Position involves rotational shifts to support 24/7 operations. Schedule accommodations will be considered based on individual needs Medium of support: Multi-mode (Voice and non-voice) A synopsis of a 'Transportation Specialist' role: A Transportation ### Senior Software Engineer, Mobile DevOps - Toast, Inc. - Location: Remote, US (remote) - Salary: $159K-$254K - Posted: 2026-04-09 - 401(k) match: listed (not source-backed) - Apply: https://careers.toasttab.com/jobs?gh_jid=7781930 - Excerpt: Senior Software Engineer, Mobile DevOps Remote, US Toast creates technology to help restaurants and local businesses succeed in a digital world, helping business owners operate, increase sales, engage customers, and keep employees happy. The Toast POS app is the central pillar of Toast's restaurant products. Every day, hundreds of thousands of servers, hosts, bartenders, and chefs use Toast's POS to serve millions of guests. Our POS product is constantly evolving, and the POS Productivity team builds the platform that makes this evolution possible. Our mission is to make it as easy as possible for 150+ Android engineers to develop new features and deliver them with high confidence and quality. We are customer-obsessed-our customers are our fellow developers, and luckily for us, they are just a Slack message away! We strive to make it easy for people to do the right thing by default. The team manages a broad technical domain, including CI/CD, the local developer experience, and release engineering for the POS app. Its projects cover Android app development, Java and Kotlin backend services in AWS, React UIs, and more. The team is an excellent fit for Android engineers with experience with mobile DevOps-CI/CD, and build and release processes. The team's current primary goals are boosting build speeds and significantly reducing our lead time to value by optimizing POS developers' build/test cycles, and making updates to the mobile app release platform to allow Toast to manage concurrent releases across multiple projects. A day in the life (Responsibilities) - Deliver rapid, ### Senior Software Engineer - Communicate - Pave - Location: Krakow, Poland (unspecified) - Salary: Not disclosed - Posted: 2026-03-26 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4677930005 - Excerpt: Senior Software Engineer - Communicate Krakow, Poland Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The Communicate Team @ Pave The Communicate team builds the products that help companies communicate compensation with clarity, transparency, and trust. As part of this team, you will own core experiences used every day by thousands of employees, managers, and candidates to understand pay, rewards, and compensation decisions. This is a rare chance to join as a founding engineer on a high-impact product team. You will help define not just what gets built, but how the team operates, shaping the roadmap, influencing technical direction, and helping establish the engineering culture from the ground up. As a Senior Software Engineer, you will play a key role in building elegant, enterprise-grade product experiences for some of the ### Customer Success Engineer - Pave - Location: New York City, NY (unspecified) - Salary: $86K-$107K - Posted: 2025-05-15 - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/paveakatroveinformationtechnologies/jobs/4565225005 - Excerpt: Customer Success Engineer New York City, NY Who We Are At Pave, we're building the industry's leading compensation platform, combining the world's largest real-time compensation dataset with deep expertise in AI and machine learning. Our platform is perfecting the art and science of pay to give 8,500+ companies unparalleled confidence in every compensation decision. Top tier companies like OpenAI, McDonald's, Instacart, Atlassian, Synopsys, Stripe, Databricks, and Waymo use Pave, transforming every pay decision into a competitive advantage. $190+ billion in total compensation spend is managed in our workflows, and 70% of Forbes AI 50 use Pave to benchmark compensation. The future of pay is real-time & predictive, and we're making it happen right now. We've raised $160M in funding from leading investors like Andreessen Horowitz, Index Ventures, Y Combinator, Bessemer Venture Partners, and Craft Ventures. The CSE Team @ Pave: You'll become a Pave product and compensation expert, and you'll use that expertise to onboard and manage 30-40 customers at a time. You'll make sure your customers implement and get value from our products quickly, and tee them up for a healthy, long-term relationship with Pave. You'll do this in partnership with the Account Management team, the Sales team, and the Product and Engineering teams to ensure our customers are successful. What You'll Be Doing: - Drive successful implementation projects for Pave's compensation software, partnering closely with HR and Finance leaders to transform their compensation strategies while ensuring strong adoption and meaningful business outcomes. - Own end-to-end project management of ### ML Ops / Dev Ops Engineer - Zensors - Location: San Francisco | OnSite (onsite) - Salary: Not disclosed - Posted: 2026-06-10 - Apply: https://jobs.ashbyhq.com/zensors/8ec79427-0fc9-4df6-9b0d-121abae98e97 - Excerpt: ML Ops / Dev Ops Engineer San Francisco | OnSite Zensors is the spatial intelligence platform for the physical world. Our AI platform provides real-time insights-from airport queue times to office utilization-helping organizations make smarter operational decisions. Zensors processes massive streams of video data 24/7 with human-level accuracy. To do this at scale, we rely on cutting-edge optimization to ensure our vision transformers and spatial models run efficiently on both cloud and edge compute resources. Learn more at www.zensors.com http://www.zensors.com. ABOUT THE ROLE As an ML / DevOps Engineer, you will play a pivotal role in advancing our infrastructure, scaling enterprise deployment workflows, and refining automation architectures to enable rapid iteration across the organization. You will sit at the critical intersection of machine learning and systems engineering. This role requires deep technical expertise not just in cloud-native tools, but also in the foundational Linux systems and networking required to process high-throughput video data reliably and securely across both cloud and edge environments. KEY RESPONSIBILITIES - Infrastructure & Automation Strategy: Drive the design and implementation of automated infrastructure deployment and validation workflows supporting our cutting-edge AI and computer vision initiatives. - Video Pipeline Operations: Design, optimize, and manage the infrastructure specifically tailored for ingesting, processing, and analyzing real-time video streams at scale. You will ensure high throughput, low latency, and rock-solid reliability for critical CV workloads. - Systems & Networking Core: Maintain a strong systems foundation by managing high-performance Linux environments. You will architect and troubleshoot complex networking configurations (both cloud ### Integration Engineer - Apple - Location: Santa Clara, United States of America (unspecified) - Salary: $127K-$191K - Posted: 2026-04-10 - 401(k) match: listed (not source-backed) - Apply: https://jobs.apple.com/en-us/details/200657280/integration-engineer?team=HRDWR - Excerpt: Integration Engineer Santa Clara, United States of America Imagine what you could do here. At Apple, new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Sophisticated, hard-working people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our dedication to leave the world better than we found it. Join us to help deliver the next excellent Apple product. Do you enjoy working on challenges that no one has solved yet? As a member of our complex group, you will get the outstanding and rewarding opportunity to craft upcoming products that will delight and encourage millions of Apple's customers every single day. Are you ready to join a team transforming hardware technology? We are searching for a dedicated engineer to join our exciting team of problem solvers. The ideal candidate will have experience in ASIC design with: • IP Integration: Integrate third-party or internal IP blocks (e.g., CPU, GPU, memory controllers, custom logic) into a SoC. • RTL Integration: Manage and merge RTL codebases, ensure connectivity and bus/interface protocols (e.g., AMBA, AXI, AHB) are correctly implemented. • Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects. • Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis to ### Intern - DevOps - Sysco - Location: Sysco LABS - Sri Lanka (unspecified) - Salary: Not disclosed - Posted: 2026-06-08 - 401(k) match: listed (not source-backed) - Apply: https://sysco.wd5.myworkdayjobs.com/syscocareers/job/Sysco-LABS-----Sri-Lanka/Intern---DevOps_R250014 - Excerpt: Intern - DevOps Sysco LABS - Sri Lanka posted: Posted 4 Days Ago ### Advanced Package Design Engineer - SK hynix - Location: San Jose, CA (onsite) - Salary: $110K-$155K - Posted: 2026-02-11 - 401(k) match: listed (not source-backed) - Learning budget: yes (not source-backed) - Apply: https://job-boards.greenhouse.io/skhynixamerica/jobs/5117958008 - Excerpt: Advanced Package Design Engineer San Jose, CA Job Title: Advanced Package Design Engineer Office Location: San Jose, CA Work Model: Onsite About SK hynix America At SK hynix America, we're at the forefront of semiconductor innovation, developing advanced memory solutions that power everything from smartphones to data centers. As a global leader in DRAM and NAND flash technologies, we drive the evolution of advancing mobile technology, empowering cloud computing, and pioneering future technologies. Our cutting-edge memory technologies are essential in today's most advanced electronic devices and IT infrastructure, enabling enhanced performance and user experiences across the digital landscape. We're looking for innovative minds to join our mission of shaping the future of technology. At SK hynix America, you'll be part of a team that's pioneering breakthrough memory solutions while maintaining a strong commitment to sustainability. We're not just adapting to technological change - we're driving it, with significant investments in artificial intelligence, machine learning, and eco-friendly solutions and operational practices. As we continue to expand our market presence and push the boundaries of what's possible in semiconductor technology, we invite you to be part of our journey to creating the next generation of memory solutions that will define the future of computing. Job Summary: We are seeking a skilled Advanced Package Design Engineer to join our Packaging Engineering team in SK Hynix America. You will be responsible for designing and optimizing high-performance, high-density Interposers for chiplet-based architectures and heterogeneous integration solutions. You'll collaborate closely with PCB, SI/PI, thermal, and manufacturing ### Associate DevOps Engineer - TD Synnex - Location: Chennai, Tamil Nadu, Tamil Nādu, India (unspecified) - Salary: Not disclosed - Posted: 2026-05-07 - 401(k) match: listed (not source-backed) - Apply: https://synnex.wd5.myworkdayjobs.com/tdsynnexcareers/job/Chennai-India/Associate-DevOps-Engineer_R50659/apply - Excerpt: Associate DevOps Engineer Chennai, Tamil Nadu, Tamil Nādu, India Embrace the role of an Associate DevOps Engineer and drive innovation in a global technology environment. Leverage automation, cloud, and CI/CD to support enterprise solutions, collaborate across teams, and ensure seamless deployments. Grow your skills in a dynamic setting with opportunities for learning and professional development. ### DevOps Engineer - IQVIA - Location: Warsaw, Poland (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://iqvia.wd1.myworkdayjobs.com/IQVIA/job/Warsaw-Poland/DevOps-Engineer_R1528007 - Excerpt: DevOps Engineer Warsaw, Poland posted: Posted 30+ Days Ago ### Senior Physical Design Engineer - Signoff Methodology - Cisco - Location: Armenia (hybrid) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960 - Excerpt: Senior Physical Design Engineer - Signoff Methodology Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you'll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You'll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what's possible in chip design. Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design. Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate with engineering teams to support and enhance implementation tool flows. Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. Strong understanding of STA flows. Familiarity with PnR, ### Mgr Product Engineering - Rambus INC - Location: Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP (unspecified) - Salary: Not disclosed - Posted: 2026-01-23 - 401(k) match: listed (not source-backed) - Apply: https://careers-rambus.icims.com/jobs/22489/mgr-product-engineering/job - Excerpt: Mgr Product Engineering Taipei, UNAVAILABLE, JP; Taipei, UNAVAILABLE, JP Overview Mgr Product Engineering (based in Korea or Taiwan) will join a dynamic and multi-disciplinary team which will ensure product reliability and gross margins meet expectations for products in our memory and interface division. This engineer will be responsible for day-to-day product engineering activities by collaborating within a cross-functional team including test engineers, OSATs and fabs. Candidates for this level position must be capable of working independently, defining technical direction, be self-motivated and a collaborative team player Responsibilities Bring-up and debug first silicon quickly to identify any potential design, process or testing issues. · Ramp up yield for new product introduction. · Perform yield analysis to ensure products yield to D0 projections. · Identify the low yield detractors and the root cause. · Work with Taiwan/Korean subcontractors to ensure smooth production, for both Wafer Sort and Final Test, on the day-to-day basis: tester correlation, hold lot disposition etc. · Generate real time SBL and SYL for all products to identify production outliers. · Generate customer reports per commitment. · Identify areas of improvement in current productions. · Drive test time reduction to product COG metric or below. · Help to manage WIP & cycle time and provide constructive feedback to improve. Qualifications BSEE required, MSEE preferred. · 15+ of experience with product/test engineering. · Programming skills preferred (C++, Java script or Python experience). · Wafer Sorting (WS) and FT NPI setup/production experience preferred. · Strong test data analysis capability. (Synopsis, Galaxy, ### MLOps Engineer I - Checkout.com - Location: Amsterdam, Netherlands (unspecified) - Salary: Not disclosed - Posted: 2026-04-17 - Apply: https://jobs.ashbyhq.com/checkout.com/bac04840-ae0e-414e-9115-46fc8ea296f1 - Excerpt: MLOps Engineer I Amsterdam, Netherlands Company Description We're Checkout.com . You might not know our name, but companies like eBay, Spotify, Klarna, Uber, and Sony do, because we're behind many of the digital experiences you use every day. We are where the world checks out, enabling over 10 billion transactions daily for more than one billion global shoppers. Whether you want to book a holiday, order food, renew a subscription, or check out online, there's a good chance our tech powers the payments behind the scenes. Our platform helps the most ambitious businesses deliver effortless digital experiences, at scale. If you want to do career-defining work, you've come to the right place. We move fast, think globally, and believe great teams are built by hiring exceptional people with conviction, curiosity, and the desire to make an impact. With 20 offices across six continents and London as our HQ, we're shaping the future of fintech - and we're just getting started. As a ML (Machine Learning) Ops Engineer at Checkout.com in the ML Platform team, you will contribute to the development of scalable systems that power real-time fraud detection and payment optimization. This is your opportunity to grow alongside top-tier engineers while making a tangible impact on millions of transactions globally. The solutions that you will be building will power our stack of value added services in the Payments Performance area. We're a growing team in an expanding area within the company and we're looking for individuals who have strong ownership, ### Integrated Cloud Consulting - Cloud FinOps Manager (Location Flexible) - RSM US LLP - Location: 7 Locations (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - 401(k) match: listed (not source-backed) - Apply: https://rsm.wd1.myworkdayjobs.com/RSMCareers/job/Chicago/Cloud-Security-Lead_JR117064 - Excerpt: Integrated Cloud Consulting - Cloud FinOps Manager (Location Flexible) 7 Locations posted: Posted Yesterday ### Senior Mixed-Signal Behavioral Modeling Engineer - K2 Space - Location: United States - Remote (remote) - Salary: $160K-$230K - Posted: 2026-03-27 - Apply: https://job-boards.greenhouse.io/k2spacecorporation/jobs/5165723008 - Excerpt: Senior Mixed-Signal Behavioral Modeling Engineer United States - Remote K2 is building the largest and highest-power satellites ever flown, unlocking performance levels previously out of reach across every orbit. Backed by $450M from leading investors including Altimeter Capital, Redpoint Ventures, T. Rowe Price, Lightspeed Venture Partners, Alpine Space Ventures, and others - with an additional $500M in signed contracts across commercial and US government customers - we're mass-producing the highest-power satellite platforms ever built for missions from LEO to deep space. The rise of heavy-lift launch vehicles is shifting the industry from an era of mass constraint to one of mass abundance, and we believe this new era demands a fundamentally different class of spacecraft. Engineered to survive the harshest radiation environments and to fully capitalize on today's and tomorrow's massive rockets, K2 satellites deliver unmatched capability at constellation scale and across multiple orbits. With multiple launches planned through 2026 and 2027, we're Building Bigger to develop the solar system and become a Kardashev Type II (K2) civilization. If you are a motivated individual who thrives in a fast-paced environment and you're excited about contributing to the success of a groundbreaking Series C space startup, we'd love for you to apply. The Role We are seeking a Senior Mixed-Signal Behavioral Modeling Engineer to own the creation of behavioral modeling and drive mixed-signal verification methodology from the ground up. You will be part of a collaborative design team developing state-of-the-art mixed-signal SoCs to be hosted on some of the largest, most ### Physical Design Engineer - Cerebras Systems - Location: Sunnyvale, CA (unspecified) - Salary: $230K-$280K - Posted: 2026-06-10 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/cerebrassystems/jobs/7764007003 - Excerpt: Physical Design Engineer Sunnyvale, CA Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. Our novel wafer-scale architecture provides the AI compute power of dozens of GPUs on a single chip, with the programming simplicity of a single device. This approach allows Cerebras to deliver industry-leading training and inference speeds and empowers machine learning users to effortlessly run large-scale ML applications, without the hassle of managing hundreds of GPUs or TPUs. Cerebras' current customers include top model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras , to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference. Thanks to the groundbreaking wafer-scale architecture, Cerebras Inference offers the fastest Generative AI inference solution in the world, over 10 times faster than GPU-based hyperscale cloud inference services. This order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation. About The Role As a member of our tight knit physical design team, you will be working on the design and analysis of 3D integrated products. This role involves a combination of traditional ASIC/SoC physical design skills, packaging, power, clock and cooling analysis. You will work closely with the architecture and RTL team to do R&D on novel concepts for 3D integration. Skills and Qualifications Required - 10+ years of physical design/verification experience. - Strong knowledge of block level and full-chip physical verification methodology. - Expert at ### Customer Collaboration Key User - The Procter & Gamble Company - Location: WARSAW PLANT & GO (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 8 weeks (not source-backed) - Non-birth-parent leave: 8 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://pg.wd5.myworkdayjobs.com/1000/job/WARSAW-PLANT--GO/Customer-Collaboration-Key-User_R000153015 - Excerpt: Customer Collaboration Key User WARSAW PLANT & GO posted: Posted Yesterday ### Silicon SoC DFT Technical Lead, Google Cloud - Google - Location: Bengaluru, Karnataka, India (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckeOLtcKsALKSvQaFNUeIZfSImIdoxh7iYdRWc-Ym1rOREjsACxwdTKTCMkSYGNObmfBxVrokX_S3iEEeeki7lYZYO1N0mME7Tx7gmV6F_vqWOmCAFNpmE-2WjiQ9XQ%3D%3D_V2&loc=IN&title=Silicon+SoC+DFT+Technical+Lead - Excerpt: Silicon SoC DFT Technical Lead, Google Cloud Bengaluru, Karnataka, India In this role, you'll work to shape the future of AI/ML hardware acceleration. You will have an opportunity to drive cutting-edge TPU (Tensor Processing Unit) technology that powers Google's most demanding AI/ML applications. You'll be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's TPU. You'll contribute to the innovation behind products loved by millions worldwide, and leverage your design and verification expertise to verify complex digital designs, with a specific focus on TPU architecture and its integration within AI/ML-driven systems. The AI and Infrastructure team is redefining what's possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide. We're the driving team behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more. Define and document the comprehensive DFT architecture for multi-core SoCs, including strategies for hierarchical scan compression, Memory BIST (MBIST) for huge memory instances, functional BISTs, Analog components, logic BIST, high-speed I/O loopback, and ### DevOps Engineer - Marsh McLennan - Location: Cluj-Napoca - Decembrie (unspecified) - Salary: Not disclosed - Posted: 2026-05-12 - 401(k) match: listed (not source-backed) - Apply: https://mmc.wd1.myworkdayjobs.com/MMC/job/Cluj-Napoca---Decembrie/DevOps-Engineer_R_339471 - Excerpt: DevOps Engineer Cluj-Napoca - Decembrie posted: Posted 30+ Days Ago ### Principal Engineer, ServerOps, EMEA and APAC - Google - Location: Dublin, Ireland (unspecified) - Salary: EUR 224K-230K - Posted: 2026-06-08 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckTKMW64I4BqQgIWWFlNKyjE5JB7smMbDoCDY9fvOc16ZEjoACxwdTEFjf4dY0qJO8F9_BElNniGmcklgCM9cEC1BUxxTQxJbyaPDh0w2NOh_qK4pqNb0MYHcmJIG_V2&loc=IE&title=Principal+Engineer - Excerpt: Principal Engineer, ServerOps, EMEA and APAC Dublin, Ireland The Server Operations team is responsible for keeping the servers, networks, and logistics processes in Google's global fleet of data centers running smoothly and efficiently. The team installs, commissions, operates and maintains some of the most sophisticated systems equipment in the world. We strive to be creative, team-oriented technicians and managers working on a daily basis to operate systems in Google's data centers that are changing computing. Google is seeking a Principal Engineer who will be responsible for setting the overall technical direction for ServerOps, driving innovation and ensuring the reliability and scalability of server operations. You will partner with Platform and Prod Ops leaders to ensure the product hardware roadmap and features are compatible and support product deployability, serviceability and fleet maintenance in all data center designs while balancing cost, efficiency, and technology innovation. As the overall ServerOps Technical Lead, you'll build collaborative bridges across Google, including Platform Engineering, Fleet Management, Tech Writing, and multiple engineering organizations. Google continuously innovates on the designs of the server, storage, and networking hardware. While performance of the hardware is key, our ability to quickly deploy the hardware at scale in Google's own and third-party data centers is key to our agility. Once deployed, the ability of our ServerOps teams is to repair, maintain, upgrade, move, and decommission the hardware that is critical to the efficiency of our deployed fleet, effectiveness of our data center technicians, and directly impacts our customer experience. Behind everything our ### Senior/Staff Physical Design Engineer - Astera Labs - Location: San Jose, CA (unspecified) - Salary: $135K-$195K - Posted: 2026-01-28 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4654857005 - Excerpt: Senior/Staff Physical Design Engineer San Jose, CA Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Senior/Staff Physical Design Engineer you will play a crucial role in overseeing the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. To accomplish that, you will work closely with designers, verification engineering, and engineering operations. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer is required, and a Master's degree is preferred. - ≥3 years' experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision. - Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in ### Physical Design Engineer - Cisco - Location: Armenia (unspecified) - Salary: Not disclosed - Posted: 2026-05-14 - 401(k) match: listed (not source-backed) - Apply: https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-engineer_2011241 - Excerpt: Physical Design Engineer Armenia Meet the Team Step into Cisco's ASIC Physical Design Team, where innovation meets collaboration. As a group of highly skilled engineers, we're redefining what's possible in silicon technology. Our mission is to drive the future of chip design, managing full chip physical implementation from RTL to GDSII and beyond. Working hand-in-hand with Front-End teams, we transform cutting-edge designs into industry-leading silicon solutions. Here, you'll have the opportunity to shape tomorrow's technology, driving advancements in power, performance, and reliability with every project. Together, we're building the foundation for the future of connectivity. Your Impact In this role, you'll drive Cisco's silicon innovation by creating breakthrough solutions that blend hardware and software. You'll solve complex challenges, accelerate design processes, and deliver impactful technology. Beyond your technical work, you'll be part of a culture that values mentorship, celebrates success, and supports your growth. This is your opportunity to shape technology that connects and empowers people worldwide. You will be responsible for macro level RTL to GDS implementation and signoff. Work with Front-End teams to understand the design architecture to ensure optimal physical implementation. Execute physical design tasks, including gate-level netlist synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize designs to achieve industry-leading power, performance, and area (PPA) metrics while maintaining design integrity through formal verification. Conduct Static Timing Analysis (STA), physical verification, formal verification and signoff closure to ensure high-quality results. Analyze and resolve Electromigration (EM) and IR-drop (IR) issues, meeting stringent signoff requirements for reliability and ### DevOps Engineer - Astranis - Location: San Francisco (unspecified) - Salary: $120K-$170K - Posted: 2025-08-22 - Apply: https://job-boards.greenhouse.io/astranis/jobs/4595910006 - Excerpt: DevOps Engineer San Francisco Astranis builds advanced satellites for high orbits, expanding humanity's reach into the solar system. Today, Astranis satellites provide dedicated, secure networks to highly-sophisticated customers across the globe- large enterprises, sovereign governments, and the US military. With five satellites on orbit and many more set to launch soon, the company is servicing a backlog of more than $1 billion of commercial contracts. Astranis is the preferred satellite communications partner for buyers with stringent requirements for uptime, data security, network visibility, and customization. Astranis has raised over $750 million from some of the world's best investors, from Andreessen Horowitz to Blackrock and Fidelity, and employs a team of 450 engineers and entrepreneurs. Astranis designs, builds, and operates its satellites out of its 153,000 sq. ft. headquarters in Northern California, USA. DevOps Engineer As a DevOps engineer, you will be an early contributor to the growing infrastructure team to support a rapidly expanding fleet of satellites. Speed and reliability aren't luxuries here; they're lifelines. When a satellite is orbiting thousands of miles above Earth, minutes matter. Our developers need to iterate and deploy rapidly to fix mission-critical issues and push improvements that keep spacecraft healthy and missions on track. You'll be the one making sure our CI pipelines aren't just efficient, but blazing fast, so our engineers can respond to the unexpected in real time. You'll own every aspect of the development workflow including AI assistant tools, language upgrades, build systems, pre-commit checks, and emerging projects to help unlock ### Senior CPU Design Verification Engineer, Emulation - Google - Location: Austin, TX, USA; +3 more (unspecified) - Salary: $163K-$237K - Posted: 2026-06-09 - Parental leave: 18 weeks (not source-backed) - Non-birth-parent leave: 18 weeks (not source-backed) - 401(k) match: listed (not source-backed) - Apply: https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckV-Qg_cjRw75nG8ayY7-bHln_TIUxekLKzww-r2Gn5GVEjsACxwdTOQfWdeWXGJDaS9JMTt5mXniXJngpDM8BaO958zwudw6S4B5NtGBB24FK6Ej_573U700r_k1FQ%3D%3D_V2&loc=US&title=Senior+CPU+Design+Verification+Engineer - Excerpt: Senior CPU Design Verification Engineer, Emulation Austin, TX, USA; +3 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Google's mission is to organize the world's information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people's lives better through technology. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $163000 - $237000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Act as the critical bridge between Emulation, Design Verification (DV), and Register-Transfer Level (RTL) teams to accelerate root-cause analysis. Correlate DV simulation failures with emulation results by analyzing SystemVerilog/UVM testbenches. Lead post-silicon debug by analyzing lab artifacts (scan dumps, software logs) to reproduce silicon bugs in emulation. Create tools and scripts to automate debug pipelines and bridge software workloads with hardware triggers. Utilize deep micro-architecture knowledge to rapidly isolate complex hardware issues. Minimum qualifications: Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience. 8 years of experience in both Design ### Strategy & Consulting - Global Network - SONG - Service - Cloud Contact Center Consultant GENESYS - Accenture plc - Location: Location not specified (unspecified) - Salary: Not disclosed - Posted: 2026-06-11 - 401(k) match: listed (not source-backed) - Apply: https://accenture.wd103.myworkdayjobs.com/accenturecareers/job/Belen/Strategy---Consulting---Global-Network---SONG---Service---Cloud-Contact-Center-Consultant-GENESYS_R00334524-1 - Excerpt: Strategy & Consulting - Global Network - SONG - Service - Cloud Contact Center Consultant GENESYS Location not specified posted: Posted Yesterday ### Physical Design Engineer (Place & Route) - Astera Labs - Location: San Jose, California, United States (unspecified) - Salary: $135K-$165K - Posted: 2026-05-07 - 401(k) match: listed (not source-backed) - Apply: https://job-boards.greenhouse.io/asteralabs/jobs/4691424005 - Excerpt: Physical Design Engineer (Place & Route) San Jose, California, United States Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . As an Astera Labs Physical Design Engineer (Place & Route) to play a crucial role in the planning, coordination, and execution supporting the design of Astera Labs' portfolio of connectivity ASICs used in the world's leading cloud service providers, server and network OEMs. This is a generalist physical design role requiring broad expertise across floorplanning, place-and-route, timing closure, and physical sign-off. You will work closely with designers, verification engineering, and engineering operations to drive blocks from RTL to GDSII. This role is fully on-site and in-person. Basic Qualifications: - Strong academic and technical background in electrical engineering. A Bachelor's degree in EE / Computer Engineering is required, and a Master's degree is preferred. - 3+ years of experience supporting or developing complex SoC/silicon products for Server, Storage, and/or Networking applications. - Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and ### Sr. ERP Support Engineer - Vodafone Group - Location: Athens, Attiki, Greece (unspecified) - Salary: Not disclosed - Posted: 2026-06-12 - 401(k) match: listed (not source-backed) - Apply: https://vodafone.eightfold.ai/careers/job/563018696527481 - Excerpt: Sr. ERP Support Engineer Athens, Attiki, Greece ### CAD Engineer – Design Verification Methodology - Apple - Location: Austin Metro Area, United States of America (unspecified) - Salary: $162K-$286K - Posted: 2026-04-15 - 401(k) match: listed (not source-backed) - Apply: https://jobs.apple.com/en-us/details/200658106/cad-engineer-design-verification-methodology?team=HRDWR - Excerpt: CAD Engineer – Design Verification Methodology Austin Metro Area, United States of America Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! As a member of our CAD team, you will develop, maintain, and enhance existing sophisticated software systems for regression-testing Apple's silicon designs in software simulation, to find and report defects in our chip designs, and thus ensure that Apple tapes-out world-class silicon. Your experience and innovative ideas will inform the design of the next generation of these regression systems. Your experience and insight, your skill at diagnosing the root cause of complex problems, and your ability to guide engineers who come to you with problems will be important contributions to an extended CAD team that comprehensively supports Apple's DV and chip design engineering efforts. You will work closely with EDA vendors to incorporate new capabilities of their commercial tools, and to resolve problems. Minimum Qualifications: Minimum of BS degree + 10 years of relevant experience Experience developing, maintaining, and enhancing an existing system for regressing RTL Experience debugging vendor tool problems Python programming --- Source-backed benefit claims include source links; other benefit values are labeled separately.