{ "results": [ { "id": "d168458ff5aa34fbf7ff497a638d1b35", "title": "ASIC Design Technical Lead", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "San Jose, California, US", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 183800, "salary_max": 263600, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 183800, "base_salary_max": 263600, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-23T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "ASIC Design Technical Lead San Jose, California, US The application window is expected to close on: 06/01/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the Team Join the Cisco Silicon One team in developing a unified silicon architecture for web scale and service provider networks. Cisco's silicon team provides a unique experience for ASIC engineers by combining the resources offered by a large multi-geography silicon organization and a large campus (with onsite gym, healthcare, and café, social interest groups, and philanthropy), with the startup culture and breadth of growth opportunities that working in a smaller ASIC team can provide. Your Impact Participate in and contribute to chip architecture definition and discussions. Author design specifications and participate in micro-architecture specification reviews. Implement Verilog RTL to meet timing and performance requirements. Help define, evolve, and support our design methodology. Mentor junior engineers on performing project tasks and problem solving. Collaborate with the verification team to address design bugs and close code coverage. Work closely with physical design team to close design timing and place-and-route issues. Triage, debug, and root cause simulation, software bring-up, and customer failures. Perform diagnostic and post silicon validation tests in the lab. Minimum Qualifications Bachelor's degree in Electrical or Computer engineering and 10+ years of ASIC Design experience or Master's degree in Electrical or Computer engineering and 8+ years of ASIC Design experience. Verilog/System Verilog programming experience. Interactive and waveform debug experience. Experience", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "application_deadline": { "field": "application_deadline", "source": "llm:greenfield:inv_371_postfix", "db_column": "application_deadline" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 50, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.072158c63ca5632514", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d168458ff5aa34fbf7ff497a638d1b35", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "ASIC Design Technical Lead", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.d5626957a90a9ad333", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d168458ff5aa34fbf7ff497a638d1b35", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:d168458ff5aa34fbf7ff497a638d1b35:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.4d9ab0c454243a2045", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d168458ff5aa34fbf7ff497a638d1b35", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/ASIC-Engineering-Technical-Leader_2007180", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c5c92b4c4a293354df1db5f522d37f44", "title": "Digital IC Design Engineer", "employer_name": "Indie Semiconductor Inc", "employer_slug": "indie-semiconductor", "location_text": "Aliso Viejo, CA; Toronto, Canada", "country": "CA", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-03-05T01:36:14.000Z", "apply_url": "https://www.indie.inc/careers/job-opportunities/?gh_jid=5062242007", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Digital IC Design Engineer Aliso Viejo, CA; Toronto, Canada Imagine being part of a team that's redefining the future of mobility-where your ideas don't just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what's possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Digital IC Design Engineer you will be responsible for managing and executing activities associated with the design, integration, verification, and maintenance of digital IP integrated into ICs used in embedded microcontroller-based system solutions. In this role, you will help bring cutting-edge System-on-Chip solutions to the ADAS market. You will work closely with the development team to produce an MCU and Security IP strategy driven by the product roadmap, ensuring the development or acquisition of reusable IP blocks. Job Responsibilities - Support system architecture definition related to security and functional safety, including core logic, memory subsystems, hardware security systems, peripheral interfaces, and power management. - Drive and/or support the implementation of innovative security features for large, complex designs across multiple platforms, with reuse and long-term scalability in mind. - Support the definition of security lifecycle management and assess potential vulnerabilities in ASIC design and the supply chain", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1841925/000119312526082535/indi-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1841925/000119312526082535/indi-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.652668d436d4bd406d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Digital IC Design Engineer Aliso Viejo, CA; Toronto, Canada Imagine being part of a team that's redefining the future of mobility-where your ideas don't just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what's possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Digital IC Design Engineer you will be responsible for managing and executing activities associated with the design, integration, verification, and maintenance of digital IP integrated into ICs used in embedded microcontroller-based system solutions. In this role, you will help bring cutting-edge System-on-Chip solutions to the ADAS market. You will work closely with the development team to produce an MCU and Security IP strategy driven by the product roadmap, ensuring the development or acquisition of reusable IP blocks. Job Responsibilities - Support system architecture definition related to security and functional safety, including core logic, memory subsystems, hardware security systems, peripheral interfaces, and power management. - Drive and/or support the implementation of innovative security features for large, complex designs across multiple platforms, with reuse and long-term scalability in mind. - Support the definition of security lifecycle management and assess potential vulnerabilities in ASIC design and the supply chain", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c5c92b4c4a293354df1db5f522d37f44:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ddd34532014f6773b1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Digital IC Design Engineer Aliso Viejo, CA; Toronto, Canada Imagine being part of a team that's redefining the future of mobility-where your ideas don't just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what's possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Digital IC Design Engineer you will be responsible for managing and executing activities associated with the design, integration, verification, and maintenance of digital IP integrated into ICs used in embedded microcontroller-based system solutions. In this role, you will help bring cutting-edge System-on-Chip solutions to the ADAS market. You will work closely with the development team to produce an MCU and Security IP strategy driven by the product roadmap, ensuring the development or acquisition of reusable IP blocks. Job Responsibilities - Support system architecture definition related to security and functional safety, including core logic, memory subsystems, hardware security systems, peripheral interfaces, and power management. - Drive and/or support the implementation of innovative security features for large, complex designs across multiple platforms, with reuse and long-term scalability in mind. - Support the definition of security lifecycle management and assess potential vulnerabilities in ASIC design and the supply chain", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c5c92b4c4a293354df1db5f522d37f44:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f94c97e2fb54c91a45", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Digital IC Design Engineer Aliso Viejo, CA; Toronto, Canada Imagine being part of a team that's redefining the future of mobility-where your ideas don't just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what's possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Digital IC Design Engineer you will be responsible for managing and executing activities associated with the design, integration, verification, and maintenance of digital IP integrated into ICs used in embedded microcontroller-based system solutions. In this role, you will help bring cutting-edge System-on-Chip solutions to the ADAS market. You will work closely with the development team to produce an MCU and Security IP strategy driven by the product roadmap, ensuring the development or acquisition of reusable IP blocks. Job Responsibilities - Support system architecture definition related to security and functional safety, including core logic, memory subsystems, hardware security systems, peripheral interfaces, and power management. - Drive and/or support the implementation of innovative security features for large, complex designs across multiple platforms, with reuse and long-term scalability in mind. - Support the definition of security lifecycle management and assess potential vulnerabilities in ASIC design and the supply chain", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c5c92b4c4a293354df1db5f522d37f44:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.f11157625645163fd9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "Indie Semiconductor Inc", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c5c92b4c4a293354df1db5f522d37f44:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.33db57156381f13330", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Digital IC Design Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c5c92b4c4a293354df1db5f522d37f44:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8037dd54f6b12668d8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Digital IC Design Engineer Aliso Viejo, CA; Toronto, Canada Imagine being part of a team that's redefining the future of mobility-where your ideas don't just sit in a lab but power next-generation technology. At indie, we are developing cutting-edge semiconductors, photonics, and radar sensors and systems for automotive, industrial, and adjacent markets. Our innovations are at the heart of advanced intelligent sensing and user experience applications, pushing the boundaries of what's possible. If you're passionate about groundbreaking technology and want to make a real impact alongside a fast-paced team that thrives on creativity and collaboration, we'd love to have you on board! As a Digital IC Design Engineer you will be responsible for managing and executing activities associated with the design, integration, verification, and maintenance of digital IP integrated into ICs used in embedded microcontroller-based system solutions. In this role, you will help bring cutting-edge System-on-Chip solutions to the ADAS market. You will work closely with the development team to produce an MCU and Security IP strategy driven by the product roadmap, ensuring the development or acquisition of reusable IP blocks. Job Responsibilities - Support system architecture definition related to security and functional safety, including core logic, memory subsystems, hardware security systems, peripheral interfaces, and power management. - Drive and/or support the implementation of innovative security features for large, complex designs across multiple platforms, with reuse and long-term scalability in mind. - Support the definition of security lifecycle management and assess potential vulnerabilities in ASIC design and the supply chain", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.91ea28b3cb9dc7b07c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Indie Semiconductor Inc", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c965983378b689bc53", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c5c92b4c4a293354df1db5f522d37f44", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Digital IC Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1841925/000119312526082535/indi-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1841925/000119312526082535/indi-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.indie.inc/careers/job-opportunities/?gh_jid=5062242007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.indie.inc/careers/job-opportunities/?gh_jid=5062242007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.indie.inc/careers/job-opportunities/?gh_jid=5062242007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "563ff30110f8dfcfa201700a7201889f", "title": "MBIST Design Engineer", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Armenia", "country": "unknown", "employment_type": "unknown", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "MBIST Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join Cisco's ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you'll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry. Your Impact In this role, you will be central to Cisco's silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed-signal domains, collaborating with multi-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies. Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits. Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs. Collaborate Across Teams:", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 2, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7d9a941f286b0e62da", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "563ff30110f8dfcfa201700a7201889f", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "MBIST Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Join Cisco's ASIC Design for Test (DFT) Team, where innovation, collaboration, and technical excellence drive everything we do. As a group of passionate engineers, we are committed to pushing the boundaries of testability and reliability in complex silicon systems. Our mission is to enable robust, high-quality silicon by architecting and implementing advanced DFT solutions. Working in close partnership with design, verification, and physical implementation teams, we ensure that every Cisco chip is not only powerful, but also rigorously tested and dependable. Here, you'll play a pivotal role in shaping the future of test engineering while growing alongside some of the best minds in the industry. Your Impact In this role, you will be central to Cisco's silicon quality and innovation by developing advanced DFT strategies that ensure every chip meets the highest standards for testability and reliability. You will address challenges across digital and mixed-signal domains, collaborating with multi-functional teams to design, implement, and optimize sophisticated test solutions. Your work will enhance product robustness, accelerate silicon validation, and drive progress in automated test methodologies. Architect and Implement DFT Solutions: Design and integrate advanced Test Access Mechanisms (TAM), scan chains, Built-In Self-Test (BIST), and Memory BIST (MBIST) infrastructures for complex integrated circuits. Test Planning and Coverage Analysis: Lead test planning, test pattern generation, and fault coverage analysis to improve test coverage for both digital and mixed-signal designs. Collaborate Across Teams:", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.050d75a39b6aa0d484", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "563ff30110f8dfcfa201700a7201889f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "MBIST Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.e9c387d9bce7ef7012", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "563ff30110f8dfcfa201700a7201889f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:563ff30110f8dfcfa201700a7201889f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.f9ff31eea95547dbf6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "563ff30110f8dfcfa201700a7201889f", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/MBIST-Design-Engineer_1451723", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "b4abcbf45dbe47dd9f0ff595639e42f9", "title": "Analog Design Engineer, Staff", "employer_name": "d-Matrix", "employer_slug": "d-matrix", "location_text": "Santa Clara, Santa Clara, Ca, Ca, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2025-05-20T17:31:17.516Z", "apply_url": "https://jobs.ashbyhq.com/d-matrix/baf4903f-0fff-4ad2-aa2b-8a56b104db5c", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 7, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2a3a0502c233c5a914", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b4abcbf45dbe47dd9f0ff595639e42f9:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.592f703b9ae3a17352", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b4abcbf45dbe47dd9f0ff595639e42f9:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.73d8fbff8d786ffc27", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b4abcbf45dbe47dd9f0ff595639e42f9:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.f6e3ffdbc4ae753f83", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Analog Design Engineer, Staff", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b4abcbf45dbe47dd9f0ff595639e42f9:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1eaf26a3fcef937f21", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.dd68197d747af7076c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Design Engineer, Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week. The role: Staff Analog Design Engineer What you will do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsis. Design state of the art in-memory-compute engine for artificial intelligence accelerator and Die-Die serial interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 7nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. - Independent minor layout tweaks when necessary. - Work with backend engineers on integration of design/layout. - Provide model of circuit for backend verification. - Participate in testboard design for silicon bring up", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.0cbb32b604cfa2e1de", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Analog Design Engineer, Staff", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/d-matrix/baf4903f-0fff-4ad2-aa2b-8a56b104db5c", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/d-matrix/baf4903f-0fff-4ad2-aa2b-8a56b104db5c", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "ac7833fe5b4966c777aeb72fa13ec4f4", "title": "ECAD Application Engineer", "employer_name": "Arista Networks", "employer_slug": "arista-networks", "location_text": "Santa Clara, CA, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 127000, "salary_max": 167000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 127000, "base_salary_max": 167000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "ECAD Application Engineer Santa Clara, CA, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: What You'll Do We are looking for a multi-disciplined individual responsible for building engineering tools and processes in the area of Computer Aided Design (CAD), Product Data Management (PDM). We are looking for candidates with expertise in electrical CAD (ECAD) to help develop expert knowledge on ECAD tools and their applications. As part of Arista Hardware, you will stay current with industry trends and development in general and ECAD tools in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.346b13792b271e878d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac7833fe5b4966c777aeb72fa13ec4f4", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "ECAD Application Engineer Santa Clara, CA, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: What You'll Do We are looking for a multi-disciplined individual responsible for building engineering tools and processes in the area of Computer Aided Design (CAD), Product Data Management (PDM). We are looking for candidates with expertise in electrical CAD (ECAD) to help develop expert knowledge on ECAD tools and their applications. As part of Arista Hardware, you will stay current with industry trends and development in general and ECAD tools in", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ac7833fe5b4966c777aeb72fa13ec4f4:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8d827441c697f72be1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac7833fe5b4966c777aeb72fa13ec4f4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "ECAD Application Engineer Santa Clara, CA, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: What You'll Do We are looking for a multi-disciplined individual responsible for building engineering tools and processes in the area of Computer Aided Design (CAD), Product Data Management (PDM). We are looking for candidates with expertise in electrical CAD (ECAD) to help develop expert knowledge on ECAD tools and their applications. As part of Arista Hardware, you will stay current with industry trends and development in general and ECAD tools in", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ac7833fe5b4966c777aeb72fa13ec4f4:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.788c1eab1e04e0a8b9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac7833fe5b4966c777aeb72fa13ec4f4", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "ECAD Application Engineer Santa Clara, CA, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: What You'll Do We are looking for a multi-disciplined individual responsible for building engineering tools and processes in the area of Computer Aided Design (CAD), Product Data Management (PDM). We are looking for candidates with expertise in electrical CAD (ECAD) to help develop expert knowledge on ECAD tools and their applications. As part of Arista Hardware, you will stay current with industry trends and development in general and ECAD tools in", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.793b24d86ced2ca1ba", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac7833fe5b4966c777aeb72fa13ec4f4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "ECAD Application Engineer Santa Clara, CA, United States Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: What You'll Do We are looking for a multi-disciplined individual responsible for building engineering tools and processes in the area of Computer Aided Design (CAD), Product Data Management (PDM). We are looking for candidates with expertise in electrical CAD (ECAD) to help develop expert knowledge on ECAD tools and their applications. As part of Arista Hardware, you will stay current with industry trends and development in general and ECAD tools in", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000126581495-ecad-application-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "54221bec3abf57734b510639725bc3df", "title": "SoC Physical Design Engineer, Top Level", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Jose, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 126800, "salary_max": 190900, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 126800, "base_salary_max": 190900, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-05T22:16:44.850Z", "apply_url": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SoC Physical Design Engineer, Top Level San Jose, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. Dynamic, hardworking people and inspiring, innovative technologies are the norm here. The people who work here have reinvented entire industries with all Apple Hardware products. The same passion for innovation that goes into our products also applies to our practices strengthening our commitment to leave the world better than we found it. Join us to help deliver the next groundbreaking Apple product! In this highly visible role, you will be responsible for implementing complete chip design from netlist to tapeout. • Work with the FE team to understand chip architecture and drive physical aspects early in the design cycle. • Work with the physical design team to drive methodologies and “best known methods” to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress. • Be a focal point for place and route, drive the work among place and route engineers, set goals and milestones, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. • Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. Minimum Qualifications: Minimum BS with 0+ years experience. Preferred Qualifications: Knowledgeable in partition or top level P&R", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 0, "years_experience_max": 4, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.4eb116a71395b0d393", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "54221bec3abf57734b510639725bc3df", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "SoC Physical Design Engineer, Top Level", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.cf3a1ac76a9df6f7e5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "54221bec3abf57734b510639725bc3df", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:54221bec3abf57734b510639725bc3df:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200645433/soc-physical-design-engineer-top-level?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c883e76f487d7b9479723b14b8b5dfef", "title": "Circuit Design Engineer - Library/Process Monitor", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Beaverton, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 134800, "salary_max": 245800, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 134800, "base_salary_max": 245800, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-10T00:23:17.905Z", "apply_url": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Circuit Design Engineer - Library/Process Monitor Beaverton, United States of America Do you have a passion for crafting entirely new solutions? As part of our Digital Design Engineering group, you'll take imaginative and revolutionary ideas and determine how to turn them into reality! You and your team will apply engineering fundamentals and start from scratch if needed, bringing forward-thinking ideas to the real world. Join us, and you'll help design the tools that allow us to bring customers experiences they've never envisioned! We have an extraordinary opportunity for Standard Cell Designers. In this highly visible role, you will be at the heart of a processor design effort, working with the custom digital circuits team and library development, making a critical impact in delivering products to market quickly. Imagine yourself at the center of our cutting-edge processor design in deep submicron technologies, and on standard cell library designs. You will drive concepts of transistor level circuit design, modeling and performance analysis, collaborating with all fields, playing a strategic role of getting functional products to millions of customers quickly. You will have the opportunity to integrate and come up with new ideas, as well as work with a team of hardworking engineers. As a Circuit Design Engineer for the custom circuits team, you will perform the following: • Work on library architecture discussion & optimization effort to improve overall Library PPA. • Drive layout optimization effort by identifying & reducing parasitics to push circuit PPA. • Work on Library PPA for different", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.255ef2c4526e3596a1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c883e76f487d7b9479723b14b8b5dfef", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Circuit Design Engineer - Library/Process Monitor", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.f992efdc1ac957c2ba", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c883e76f487d7b9479723b14b8b5dfef", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c883e76f487d7b9479723b14b8b5dfef:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657022/circuit-design-engineer-library-process-monitor?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "dd5de0249310b4162aea8924bb9fb377", "title": "System Hardware Engineer (Switch/NAS)", "employer_name": "Ubiquiti", "employer_slug": "ubiquiti", "location_text": "Taipei", "country": "TW", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-28T10:01:40.000Z", "apply_url": "https://job-boards.greenhouse.io/ubiquiti/jobs/4234000009", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "System Hardware Engineer (Switch/NAS) Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Lead hardware circuit design, schematic development, and PCB layout review to ensure robust system performance and manufacturability - Drive design verification, system bring-up, debugging, and root cause analysis, including RMA failure resolution - Own BOM management and support production to ensure smooth transition from NPI to mass production - Evaluate and integrate new technologies, components, and platforms to enhance product competitiveness - Participate across the full product lifecycle from NPI, MP to EOL - Collaborate with cross-functional teams including layout, component engineering, firmware, mechanical, power, thermal, QA, software, PM, ID, and compliance Qualifications - Bachelor's degree or above in Electrical Engineering or a related field - 5+ years of hands-on experience in system-level hardware design - Experience with networking products such as Ethernet gateway, switch, or NAS platforms - Solid understanding of Ethernet technologies including 802.3 PoE (PSE/PD), 1G/10G PHY, and switching or routing fundamentals", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4776ad31c1006873e3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "dd5de0249310b4162aea8924bb9fb377", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "System Hardware Engineer (Switch/NAS) Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Lead hardware circuit design, schematic development, and PCB layout review to ensure robust system performance and manufacturability - Drive design verification, system bring-up, debugging, and root cause analysis, including RMA failure resolution - Own BOM management and support production to ensure smooth transition from NPI to mass production - Evaluate and integrate new technologies, components, and platforms to enhance product competitiveness - Participate across the full product lifecycle from NPI, MP to EOL - Collaborate with cross-functional teams including layout, component engineering, firmware, mechanical, power, thermal, QA, software, PM, ID, and compliance Qualifications - Bachelor's degree or above in Electrical Engineering or a related field - 5+ years of hands-on experience in system-level hardware design - Experience with networking products such as Ethernet gateway, switch, or NAS platforms - Solid understanding of Ethernet technologies including 802.3 PoE (PSE/PD), 1G/10G PHY, and switching or routing fundamentals", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:dd5de0249310b4162aea8924bb9fb377:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f401d668a9a4df9b2c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "dd5de0249310b4162aea8924bb9fb377", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "System Hardware Engineer (Switch/NAS) Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Lead hardware circuit design, schematic development, and PCB layout review to ensure robust system performance and manufacturability - Drive design verification, system bring-up, debugging, and root cause analysis, including RMA failure resolution - Own BOM management and support production to ensure smooth transition from NPI to mass production - Evaluate and integrate new technologies, components, and platforms to enhance product competitiveness - Participate across the full product lifecycle from NPI, MP to EOL - Collaborate with cross-functional teams including layout, component engineering, firmware, mechanical, power, thermal, QA, software, PM, ID, and compliance Qualifications - Bachelor's degree or above in Electrical Engineering or a related field - 5+ years of hands-on experience in system-level hardware design - Experience with networking products such as Ethernet gateway, switch, or NAS platforms - Solid understanding of Ethernet technologies including 802.3 PoE (PSE/PD), 1G/10G PHY, and switching or routing fundamentals", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:dd5de0249310b4162aea8924bb9fb377:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.48d6e952b82cd69c95", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "dd5de0249310b4162aea8924bb9fb377", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "System Hardware Engineer (Switch/NAS) Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Lead hardware circuit design, schematic development, and PCB layout review to ensure robust system performance and manufacturability - Drive design verification, system bring-up, debugging, and root cause analysis, including RMA failure resolution - Own BOM management and support production to ensure smooth transition from NPI to mass production - Evaluate and integrate new technologies, components, and platforms to enhance product competitiveness - Participate across the full product lifecycle from NPI, MP to EOL - Collaborate with cross-functional teams including layout, component engineering, firmware, mechanical, power, thermal, QA, software, PM, ID, and compliance Qualifications - Bachelor's degree or above in Electrical Engineering or a related field - 5+ years of hands-on experience in system-level hardware design - Experience with networking products such as Ethernet gateway, switch, or NAS platforms - Solid understanding of Ethernet technologies including 802.3 PoE (PSE/PD), 1G/10G PHY, and switching or routing fundamentals", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.eea83a6322e6edbdc3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "dd5de0249310b4162aea8924bb9fb377", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "System Hardware Engineer (Switch/NAS) Taipei About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Responsibilities - Lead hardware circuit design, schematic development, and PCB layout review to ensure robust system performance and manufacturability - Drive design verification, system bring-up, debugging, and root cause analysis, including RMA failure resolution - Own BOM management and support production to ensure smooth transition from NPI to mass production - Evaluate and integrate new technologies, components, and platforms to enhance product competitiveness - Participate across the full product lifecycle from NPI, MP to EOL - Collaborate with cross-functional teams including layout, component engineering, firmware, mechanical, power, thermal, QA, software, PM, ID, and compliance Qualifications - Bachelor's degree or above in Electrical Engineering or a related field - 5+ years of hands-on experience in system-level hardware design - Experience with networking products such as Ethernet gateway, switch, or NAS platforms - Solid understanding of Ethernet technologies including 802.3 PoE (PSE/PD), 1G/10G PHY, and switching or routing fundamentals", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4234000009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4234000009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c0ef1f8d705f20dc98eaf7cc4060855f", "title": "Automotive and Robotics SOC Architect", "employer_name": "TensTorrent", "employer_slug": "tenstorrent", "location_text": "United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2025-12-12T22:12:49.000Z", "apply_url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5004262007", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Automotive and Robotics SOC Architect United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is accelerating the future of AI and high-performance compute by building industry-leading CPU and AI architectures. As an Automotive and Robotics SoC Architect, you will define scalable, top-down system architectures that unify our CPU and AI technologies for next-generation automotive applications. This senior technical role shapes the architectural direction of our automotive and robotics portfolio, ensuring our products meet the industry's highest expectations for performance, safety, reliability, and security. This position is central to how Tenstorrent delivers world-class automotive solutions and requires strong technical leadership, systems thinking, and cross-functional collaboration. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - A systems thinker who can architect complex SoCs from", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "bootstrapped", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": 25, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c962dfdd8f1a5c6a15", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c0ef1f8d705f20dc98eaf7cc4060855f", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Automotive and Robotics SOC Architect United States Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. Tenstorrent is accelerating the future of AI and high-performance compute by building industry-leading CPU and AI architectures. As an Automotive and Robotics SoC Architect, you will define scalable, top-down system architectures that unify our CPU and AI technologies for next-generation automotive applications. This senior technical role shapes the architectural direction of our automotive and robotics portfolio, ensuring our products meet the industry's highest expectations for performance, safety, reliability, and security. This position is central to how Tenstorrent delivers world-class automotive solutions and requires strong technical leadership, systems thinking, and cross-functional collaboration. This role is remote, based out of North America. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - A systems thinker who can architect complex SoCs from", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.a1a455950509f2f825", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c0ef1f8d705f20dc98eaf7cc4060855f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c0ef1f8d705f20dc98eaf7cc4060855f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5004262007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5004262007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5004262007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5004262007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "78666d4d186f7ce1040ceff1dff2837f", "title": "ASIC Physical Design Engineer", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Armenia", "country": "unknown", "employment_type": "unknown", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-07T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "ASIC Physical Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Our team specializes in macro-level RTL-to-GDSII physical implementation and signoff, collaborating closely with Front-End teams to ensure optimal results. We are dedicated to delivering complex SoC and block-level projects through technical excellence and teamwork. The team is composed of highly experienced professionals who value collaboration and high standards in physical design. Your Impact Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize power, performance, and area (PPA) while maintaining design correctness through formal verification. Execute static timing analysis (STA), physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration (EM) and IR-drop issues to meet reliability and performance signoff targets. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects. Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure. Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence). Preferred Qualifications Broad understanding of physical design methodologies, integration, and implementation flows. Experience in physical verification (LVS, DRC) and signoff processes. Familiarity with physical design EDA toolchains and end-to-end workflows. Advanced expertise in STA, timing closure, and constraint management. Proficiency", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b256c4b4a31c2aac43", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78666d4d186f7ce1040ceff1dff2837f", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "ASIC Physical Design Engineer Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team Our team specializes in macro-level RTL-to-GDSII physical implementation and signoff, collaborating closely with Front-End teams to ensure optimal results. We are dedicated to delivering complex SoC and block-level projects through technical excellence and teamwork. The team is composed of highly experienced professionals who value collaboration and high standards in physical design. Your Impact Lead macro-level RTL-to-GDSII physical implementation and signoff. Collaborate with Front-End teams to translate architecture into optimal physical design. Perform synthesis, floorplanning, placement, Clock Tree Synthesis (CTS), and routing. Optimize power, performance, and area (PPA) while maintaining design correctness through formal verification. Execute static timing analysis (STA), physical verification, formal checks, and signoff closure to ensure reliable, high-quality silicon. Analyze and resolve Electromigration (EM) and IR-drop issues to meet reliability and performance signoff targets. Minimum Qualifications Bachelor's or Master's degree in Electrical Engineering, Computer Science, or a related field. 5+ years of hands-on experience in ASIC design and physical implementation. Proven track record in ASIC physical design and verification preferably in complex SoC or block-level projects. Deep knowledge of block-level synthesis, place-and-route (PnR), and timing closure. Experience with industry-standard PnR and signoff tools (e.g., Synopsys, Cadence). Preferred Qualifications Broad understanding of physical design methodologies, integration, and implementation flows. Experience in physical verification (LVS, DRC) and signoff processes. Familiarity with physical design EDA toolchains and end-to-end workflows. Advanced expertise in STA, timing closure, and constraint management. Proficiency", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.96ef9d7a4b065e1c76", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78666d4d186f7ce1040ceff1dff2837f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "ASIC Physical Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.2776d05ddec2bae39a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78666d4d186f7ce1040ceff1dff2837f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:78666d4d186f7ce1040ceff1dff2837f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.99260f5bf17edb7deb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78666d4d186f7ce1040ceff1dff2837f", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/ASIC-Physical-Design-Engineer_2008509", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "0367b1b872a7b991ea529bb2a2584fdb", "title": "Senior Staff Signal & Power Integrity Engineer", "employer_name": "Maxlinear Inc", "employer_slug": "maxlinear", "location_text": "Carlsbad, CA, US; Irvine, CA, US", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 135000, "salary_max": 183000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 135000, "base_salary_max": 183000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "apply_url_verified": false, "ats": "icims", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4d9b15766a507a8932", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0367b1b872a7b991ea529bb2a2584fdb:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.cc3464c2abd0276655", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0367b1b872a7b991ea529bb2a2584fdb:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f688e4fa214e7c9e1c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0367b1b872a7b991ea529bb2a2584fdb:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.ea1a4b0c3c36ae0e13", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "Maxlinear Inc", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0367b1b872a7b991ea529bb2a2584fdb:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.56474922416bb43909", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8ee23c2dbcb9b745b9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Staff Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Senior Staff Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.9cc2e0ef907447b92a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0367b1b872a7b991ea529bb2a2584fdb", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Maxlinear Inc", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3039/senior-staff-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "f4f09d26ed43309b193eeb3ed5091fa4", "title": "Principal Signal & Power Integrity Engineer", "employer_name": "Maxlinear Inc", "employer_slug": "maxlinear", "location_text": "Carlsbad, CA, US; Irvine, CA, US", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 158000, "salary_max": 193000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 158000, "base_salary_max": 193000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "apply_url_verified": false, "ats": "icims", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "principal", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 8, "years_experience_max": 12, "role_function": "teaching_education", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3ff5f9f1b6b2d28224", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f4f09d26ed43309b193eeb3ed5091fa4:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.70305d362ff0c4952d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f4f09d26ed43309b193eeb3ed5091fa4:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e0d3c35c6f4ef10c49", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f4f09d26ed43309b193eeb3ed5091fa4:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.688d3c23a2e00c668f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "Maxlinear Inc", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f4f09d26ed43309b193eeb3ed5091fa4:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.0627278631d3654fee", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Title: \"inc\"", "tooltip": "Title matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Principal Signal & Power Integrity Engineer", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f4f09d26ed43309b193eeb3ed5091fa4:title:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.af4270b463c869fbac", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f78de27e9fea29da1d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Principal Signal & Power Integrity Engineer Carlsbad, CA, US; Irvine, CA, US Responsibilities MaxLinear is seeking a Principal Signal & Power Integrity (SI/PI) Engineer to join our team. In this role, you will focus on the following: Development of state-of-the-art packages and printed circuit boards (PCBs) for MaxLinear's next generation products Perform SI/PI simulations and optimization to ensure critical signals meet their required specifications Design and simulate high-speed signal interfaces and power distribution networks (PDN) for advanced communications SoC packages and PCBs Work on a diverse set of products and applications including RF/mm-wave modems and transceivers, 5G communication, wireless connectivity, and optical communications (PAM4 1.6T/3.2T DSPs and TIAs) for data center connectivity and storage for AI applications Qualifications Deep understanding of Electromagnetic fundamentals, transmission lines, and microwave theory Experience designing and simulating signal and power integrity solutions for high-speed system components (packages, PCB, connectors) Experience with high-speed channel simulations for SerDes and transient simulations for SI and PI Understanding of S-parameters, Smith Chart, and frequency domain analysis Proficiency in use of 2.5D and 3D simulation tools such as ANSYS HFSS, SIwave, Cadence Sigrity tools, or similar field solvers Expertise in time and frequency domain analysis using simulation tools like ADS, SPECTRE, etc. Hands-on experience with lab measurement equipment like Spectrum Analyzer, Vector Network An", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.0bef139e38fbf97e05", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f4f09d26ed43309b193eeb3ed5091fa4", "signal_type": "query_match", "display_text": "Title: \"inc\"", "tooltip": "Title contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Principal Signal & Power Integrity Engineer", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1288469/000128846926000011/mxl-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careersus-maxlinear.icims.com/jobs/3035/principal-signal-&-power-integrity-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "455cde8db36a923ddd68f1be6ccdcc86", "title": "Staff Product Design Engineer", "employer_name": "Oura", "employer_slug": "oura", "location_text": "Hybrid - San Francisco, California", "country": "US", "employment_type": "unknown", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 6, "salary_min": 198000, "salary_max": 233000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 198000, "base_salary_max": 233000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-01-09T11:16:29.000Z", "apply_url": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Staff Product Design Engineer Hybrid - San Francisco, California Our mission at Oura is to empower every person to own their inner potential. Our award-winning products help our global community gain a deeper knowledge of their readiness, activity, and sleep quality by using their Oura Ring and its connected app. We've helped millions of people understand and improve their health by providing daily insights and practical steps to inspire healthy lifestyles. Empowering the world starts with living our values and empowering our team. As a quickly growing company focused on helping people live healthier and happier lives, we ensure that our team members have what they need to do their best work - both in and out of the office. We are looking for a Staff Mechanical Design Engineer to join our hardware team working on future wearables. This opportunity will be hybrid to either San Diego or San Francisco. What you will do: - Mechanical design and development of cutting-edge wearable and other consumer devices, with a keen focus to detail, precision, and design - Drive product development with our manufacturing partners in Asia, North America, and Europe - Build a lot of prototypes, break them, and iterate quickly. - Work with leadership to help define and drive product roadmap and timelines. We would love to consider you for this role, if you have: - Project Experience : 10+ years of experience as a consumer product design engineer who loves working on highly creative, fast-paced, and collaborative teams alongside", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": 20, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "pto_days": { "field": "pto_days", "source": "llm:greenfield:inv_371_postfix", "db_column": "pto_days" }, "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.265cefe6fdf63c543f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "455cde8db36a923ddd68f1be6ccdcc86", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Staff Product Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.44e1fc33e32c881b01", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "455cde8db36a923ddd68f1be6ccdcc86", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:455cde8db36a923ddd68f1be6ccdcc86:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "pto_days": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/oura/jobs/4093697009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "0ac4c9d6ffeae41504193872246dbf32", "title": "Sr. Product Designer, Connected Fitness", "employer_name": "Peloton Interactive Inc", "employer_slug": "peloton-interactive", "location_text": "New York, New York", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 155350, "salary_max": 190850, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base_plus_commission", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 155350, "base_salary_max": 190850, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-09T17:14:08.000Z", "apply_url": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sr. Product Designer, Connected Fitness New York, New York ABOUT THE ROLE The Workouts Design Team at Peloton is focused on designing new software experiences that enable people to live both healthier and longer lives. The team works collaboratively with designers across the organization to create new workout experiences, novel software interactions for new hardware products, and intuitive ways of getting the best workout at-home, outdoors, or even in the gym. Our Senior Product Designers create complex and functionality-dense interfaces across various ecosystems. They design in non-linear terms: capturing interactions, edge-cases, and the various states of these experiences through deliverables such as user flows, product maps, wireframes, storyboards, and prototypes. They approach problems with an agile mentality and rapidly iterate on both the UI and UX of the projects. As a Senior Product Designer, you'll partner closely with content designers, product managers, user researchers, engineers, project managers, and other cross-functional teams to bring features to life across our platforms. Successful candidates are self-motivated, strategic, highly collaborative, proactive project owners, readily open to feedback and critique. They value the success of the team over their individual progress, and are often taking leadership over delivering outcomes. YOUR DAILY IMPACT AT PELOTON - Partner with peers in design, product and engineering to help deliver cohesive experiences across all member touchpoints (hardware products, web, mobile, watch, TV, etc.) - Partner with design leads across software and hardware teams to drive new R&D opportunities and set direction for future experiences - Drive complex design initiatives", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1639825/000163982525000138/pton-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1639825/000163982525000138/pton-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "design", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.61b514ba96f13d5540", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0ac4c9d6ffeae41504193872246dbf32", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Product Designer, Connected Fitness New York, New York ABOUT THE ROLE The Workouts Design Team at Peloton is focused on designing new software experiences that enable people to live both healthier and longer lives. The team works collaboratively with designers across the organization to create new workout experiences, novel software interactions for new hardware products, and intuitive ways of getting the best workout at-home, outdoors, or even in the gym. Our Senior Product Designers create complex and functionality-dense interfaces across various ecosystems. They design in non-linear terms: capturing interactions, edge-cases, and the various states of these experiences through deliverables such as user flows, product maps, wireframes, storyboards, and prototypes. They approach problems with an agile mentality and rapidly iterate on both the UI and UX of the projects. As a Senior Product Designer, you'll partner closely with content designers, product managers, user researchers, engineers, project managers, and other cross-functional teams to bring features to life across our platforms. Successful candidates are self-motivated, strategic, highly collaborative, proactive project owners, readily open to feedback and critique. They value the success of the team over their individual progress, and are often taking leadership over delivering outcomes. YOUR DAILY IMPACT AT PELOTON - Partner with peers in design, product and engineering to help deliver cohesive experiences across all member touchpoints (hardware products, web, mobile, watch, TV, etc.) - Partner with design leads across software and hardware teams to drive new R&D opportunities and set direction for future experiences - Drive complex design initiatives", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.3b753bc1e477b14426", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0ac4c9d6ffeae41504193872246dbf32", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Peloton Interactive Inc", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.cf60b9c3f7c03bb1b0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0ac4c9d6ffeae41504193872246dbf32", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Sr. Product Designer, Connected Fitness", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.6e6188f449092864fe", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0ac4c9d6ffeae41504193872246dbf32", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0ac4c9d6ffeae41504193872246dbf32:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1639825/000163982525000138/pton-20250630.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1639825/000163982525000138/pton-20250630.htm" ], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.onepeloton.com/en/all-jobs/?gh_jid=7976905", "source_values": [ "rule" ], "checked_at": null } } }, { "id": "2f2362ada29748499707c97e58b29c4b", "title": "Memory Design Engineer - SRAM / TCAM", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Zhubei, Taiwan", "country": "TW", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.04fa82c4523ebad939", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2f2362ada29748499707c97e58b29c4b:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.22ecd5bcef65bb3ddd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2f2362ada29748499707c97e58b29c4b:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.39ce90973e165496f8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2f2362ada29748499707c97e58b29c4b:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5bc833bf40da6f99e8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2f2362ada29748499707c97e58b29c4b:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.bd3c2e45a89f4ee15d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Memory Design Engineer - SRAM / TCAM", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2f2362ada29748499707c97e58b29c4b:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.aa0e67604ec4928139", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e802f5e967e2f2d96c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in cross-functional", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.0b359fbd5e79a39a28", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Memory Design Engineer - SRAM / TCAM", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.c81ec5b29e437f7b77", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2f2362ada29748499707c97e58b29c4b", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Design-Engineer---1_2009410", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "513fa84462597ce5546de071f4ef061b", "title": "SOC Architect", "employer_name": "Vodafone Group", "employer_slug": "vodafone-group", "location_text": "Praha, Czech Republic", "country": "CZ", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-12T10:25:24.000Z", "apply_url": "https://vodafone.eightfold.ai/careers/job/563018696023545", "apply_url_verified": false, "ats": "eightfold", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SOC Architect Praha, Czech Republic", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 35, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.5c49e9d351ce19cd3f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "513fa84462597ce5546de071f4ef061b", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:513fa84462597ce5546de071f4ef061b:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://vodafone.eightfold.ai/careers/job/563018696023545", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://vodafone.eightfold.ai/careers/job/563018696023545", "source_values": [ "rule" ], "checked_at": null } } }, { "id": "6ab336b3e87370b96bd785af6a7c4d92", "title": "Memory Circuit Design Engineer - SRAM / TCAM", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Zhubei, Taiwan", "country": "TW", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2049a1fa56a0d2e4b6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6ab336b3e87370b96bd785af6a7c4d92:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6cdb68d47f9af7956b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6ab336b3e87370b96bd785af6a7c4d92:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7ced2e0c09875ea2f7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6ab336b3e87370b96bd785af6a7c4d92:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d0c9fd71856fc46c26", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6ab336b3e87370b96bd785af6a7c4d92:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.6d8efcad18ba3cf6e2", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6ab336b3e87370b96bd785af6a7c4d92:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.87ec83f31d817f72c4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f642d1f583971e6d90", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 5+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. TCAM/SRAM/2P/DP architectures and advanced custom circuit implementation on advanced technology nodes Full embedded memory design flow: Architecture, circuit design, physical implementation, compiler automation, characterization, model generation Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Ability to work collaboratively in", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.4f07c7fd9fdc9c64fc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Memory Circuit Design Engineer - SRAM / TCAM", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.3dbb157e1304658a80", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6ab336b3e87370b96bd785af6a7c4d92", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-Circuit-Design-Engineer---2_2009411-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "e604fd6cffcec03ab464b0e5b3e876d2", "title": "Technical Brand Designer", "employer_name": "Constellation Software Inc.", "employer_slug": "constellation-software", "location_text": "New York, New York", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 90000, "salary_max": 100000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 90000, "base_salary_max": 100000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-09T00:38:43.000Z", "apply_url": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Technical Brand Designer New York, New York About Constellation: Constellation is a cutting-edge AI solution that empowers highly regulated and complex industries with the insights and content they need to fuel their business. Specializing in industries such as healthcare, automotive, insurance, and finance, our powerful data/AI insights tools inform the creation of compliant content at scale. We enable our customers to harness their data and streamline the creation of localized, personalized content. A global, NYC-based company, Constellation has been revolutionizing marketing technology and data intelligence in order to drive exponential growth since its founding in 2016. Constellation was named the 65th Fastest-Growing Private Company in America, the 10th Fastest-Growing Women-Owned Private Company, and the 7th Fastest-Growing Marketing & Advertising Company by Inc 500. In 2022, our platform won the Digiday Technology Award for Best Marketing Automation Platform. div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-2 [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-2 [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8\"> _*]:min-w-0 gap-3 standard-markdown\"> About the Role We're looking for a strategic Technical Brand Designer to join our growing Creative Team-someone who not only understands exceptional design, but also has a genuine curiosity for how AI can be utilized within design practices. You'll craft multi-channel creative across legacy automotive brands such as BMW, Land Rover, Hyundai, and Volkswagen, while working closely with our Product and Tech teams to continue building on products leveraging proprietary technology. This is not your typical design role. It sits at the intersection of AI optimization and a high-volume systems approach. This is a full-time, hybrid role based out of our headquarters", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "portfolio_required": { "field": "portfolio_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "portfolio_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "growth-stage", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d43ab6da30c8071617", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e604fd6cffcec03ab464b0e5b3e876d2", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Technical Brand Designer New York, New York About Constellation: Constellation is a cutting-edge AI solution that empowers highly regulated and complex industries with the insights and content they need to fuel their business. Specializing in industries such as healthcare, automotive, insurance, and finance, our powerful data/AI insights tools inform the creation of compliant content at scale. We enable our customers to harness their data and streamline the creation of localized, personalized content. A global, NYC-based company, Constellation has been revolutionizing marketing technology and data intelligence in order to drive exponential growth since its founding in 2016. Constellation was named the 65th Fastest-Growing Private Company in America, the 10th Fastest-Growing Women-Owned Private Company, and the 7th Fastest-Growing Marketing & Advertising Company by Inc 500. In 2022, our platform won the Digiday Technology Award for Best Marketing Automation Platform. div]:bg-bg-000/50 [&_pre>div]:border-0.5 [&_pre>div]:border-border-400 [&_.ignore-pre-bg>div]:bg-transparent [&_.standard-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-2 [&_.standard-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8 [&_.progressive-markdown_:is(p,blockquote,h1,h2,h3,h4,h5,h6)]:pl-2 [&_.progressive-markdown_:is(p,blockquote,ul,ol,h1,h2,h3,h4,h5,h6)]:pr-8\"> _*]:min-w-0 gap-3 standard-markdown\"> About the Role We're looking for a strategic Technical Brand Designer to join our growing Creative Team-someone who not only understands exceptional design, but also has a genuine curiosity for how AI can be utilized within design practices. You'll craft multi-channel creative across legacy automotive brands such as BMW, Land Rover, Hyundai, and Volkswagen, while working closely with our Product and Tech teams to continue building on products leveraging proprietary technology. This is not your typical design role. It sits at the intersection of AI optimization and a high-volume systems approach. This is a full-time, hybrid role based out of our headquarters", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.3c8531ba26750dd901", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e604fd6cffcec03ab464b0e5b3e876d2", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Constellation Software Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.13ef30c8f527014d3c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e604fd6cffcec03ab464b0e5b3e876d2", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Technical Brand Designer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.38f3f5487b2fa23c4b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e604fd6cffcec03ab464b0e5b3e876d2", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e604fd6cffcec03ab464b0e5b3e876d2:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/constellationsoftwareinc/jobs/4687910006", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "8759d18332bcb5169a708fc984d3d7e4", "title": "Experienced PCB Design Engineer", "employer_name": "Renesas Electronics", "employer_slug": "renesas-electronics", "location_text": "Ho Chi Minh, , Vietnam", "country": "VN", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000130992933--experienced-pcb-design-engineer", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Experienced PCB Design Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: - Extract S-parameters (Touchstone format) and RLC ladder models from design data using electromagnetic analysis tools (Ansys HFSS and SIwave) - Perform simulations with a sim tool (Synopsys HSPICE) - Design board (.brd) and package (.mcm) data using a design tool (Cadense Allegro)- Create schematics using Cadense OrCAD (optional) Qualifications: - Hands-on expertise with Ansys HFSS, Ansys SIwave, and Synopsys HSPICE - Strong understanding of: Signal Integrity (SI); and Power Integrity (PI) - High-speed interconnect modeling - Ability to interpret design data and convert it into meaningful electrical models - Experience with Cadence Allegro for board and package design - Familiarity with .brd and .mcm file formats - Experience with Cadence OrCAD schematic capture -Strong problem solving mindset and ability to work in fast-paced environment. -Good communication skills, ability to cooperate with other teams. - Ability to communicate in Japanese is a plus. Additional Information: We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5a0d68e223be3894c8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8759d18332bcb5169a708fc984d3d7e4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Experienced PCB Design Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: - Extract S-parameters (Touchstone format) and RLC ladder models from design data using electromagnetic analysis tools (Ansys HFSS and SIwave) - Perform simulations with a sim tool (Synopsys HSPICE) - Design board (.brd) and package (.mcm) data using a design tool (Cadense Allegro)- Create schematics using Cadense OrCAD (optional) Qualifications: - Hands-on expertise with Ansys HFSS, Ansys SIwave, and Synopsys HSPICE - Strong understanding of: Signal Integrity (SI); and Power Integrity (PI) - High-speed interconnect modeling - Ability to interpret design data and convert it into meaningful electrical models - Experience with Cadence Allegro for board and package design - Familiarity with .brd and .mcm file formats - Experience with Cadence OrCAD schematic capture -Strong problem solving mindset and ability to work in fast-paced environment. -Good communication skills, ability to cooperate with other teams. - Ability to communicate in Japanese is a plus. Additional Information: We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8759d18332bcb5169a708fc984d3d7e4:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6abe49f10dcfbafb96", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8759d18332bcb5169a708fc984d3d7e4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Experienced PCB Design Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: - Extract S-parameters (Touchstone format) and RLC ladder models from design data using electromagnetic analysis tools (Ansys HFSS and SIwave) - Perform simulations with a sim tool (Synopsys HSPICE) - Design board (.brd) and package (.mcm) data using a design tool (Cadense Allegro)- Create schematics using Cadense OrCAD (optional) Qualifications: - Hands-on expertise with Ansys HFSS, Ansys SIwave, and Synopsys HSPICE - Strong understanding of: Signal Integrity (SI); and Power Integrity (PI) - High-speed interconnect modeling - Ability to interpret design data and convert it into meaningful electrical models - Experience with Cadence Allegro for board and package design - Familiarity with .brd and .mcm file formats - Experience with Cadence OrCAD schematic capture -Strong problem solving mindset and ability to work in fast-paced environment. -Good communication skills, ability to cooperate with other teams. - Ability to communicate in Japanese is a plus. Additional Information: We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8759d18332bcb5169a708fc984d3d7e4:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c4d7bdc9552976ddea", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8759d18332bcb5169a708fc984d3d7e4", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Experienced PCB Design Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8759d18332bcb5169a708fc984d3d7e4:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a3cca899e1bef7f8cc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8759d18332bcb5169a708fc984d3d7e4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Experienced PCB Design Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: - Extract S-parameters (Touchstone format) and RLC ladder models from design data using electromagnetic analysis tools (Ansys HFSS and SIwave) - Perform simulations with a sim tool (Synopsys HSPICE) - Design board (.brd) and package (.mcm) data using a design tool (Cadense Allegro)- Create schematics using Cadense OrCAD (optional) Qualifications: - Hands-on expertise with Ansys HFSS, Ansys SIwave, and Synopsys HSPICE - Strong understanding of: Signal Integrity (SI); and Power Integrity (PI) - High-speed interconnect modeling - Ability to interpret design data and convert it into meaningful electrical models - Experience with Cadence Allegro for board and package design - Familiarity with .brd and .mcm file formats - Experience with Cadence OrCAD schematic capture -Strong problem solving mindset and ability to work in fast-paced environment. -Good communication skills, ability to cooperate with other teams. - Ability to communicate in Japanese is a plus. Additional Information: We have adopted a hybrid model that gives employees the ability to work remotely two days a week while ensuring that we come together as a team in the office the rest of the time. The designated in-office days are Tuesday through Thursday for innovation, collaboration and continuous learning. Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.4f0629b6ca5483ce2f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8759d18332bcb5169a708fc984d3d7e4", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Experienced PCB Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000130992933--experienced-pcb-design-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000130992933--experienced-pcb-design-engineer", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "a3f11edc0a1843409a7d10f554016141", "title": "Sr. Hardware Development Engineer, Devices", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Shenzhen, CHN", "country": "CN", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-04T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 52, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 7, "years_experience_max": 8, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a96e7a737fe6f2f29d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a3f11edc0a1843409a7d10f554016141:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b2000863e6051ec5f6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a3f11edc0a1843409a7d10f554016141:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d514dc8b7eb7246212", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a3f11edc0a1843409a7d10f554016141:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.33488ed0bdcdbd4652", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3e06f3836ff7615534", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ceba41898c81529588", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a3f11edc0a1843409a7d10f554016141", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: * Lead multiple electrical design and validation on multiple products across Amazon device portfolio * Research test/validation technologies and methodologies across factory and lab environment", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3173588/sr-hardware-development-engineer-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "c655354d3134d053c93413b59a062b4c", "title": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Shenzhen, CHN", "country": "CN", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-26T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 52, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 7, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6f46e340bf26c7e91c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c655354d3134d053c93413b59a062b4c:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.950378ec36a577d3de", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c655354d3134d053c93413b59a062b4c:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e548d4be4dc2e1e60b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c655354d3134d053c93413b59a062b4c:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.29d6fde67b9a31d767", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.39192bd9f1fd3dd9ea", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c4a4193e6e32ee7846", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c655354d3134d053c93413b59a062b4c", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Hardware Development Engineer, Centralized Electrical Engineer (CEE) - Devices Shenzhen, CHN Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced groundbreaking devices like Kindle, Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Sr. Hardware Development Engineer in our team, you will be responsible for supporting product development functions across design, validation and manufacturing. We are looking for candidates who thrive in a fast-paced start-up like environment and want to invent the future. In this role, you will wear many hats working on system design down to quick turn prototypes, manufacturing production processes, design validation and debug. You will work at the integrated circuit and product systems level and drive the quality bar to ensure the products we ship are bug free. To be successful you need to be highly motivated, understand how to solve problems and dive deep while delivering to the highest standards. You will demonstrate a strong working knowledge of product electrical design with expertise in systems integration, the desire to learn from new challenges, and the problem-solving and communication skills to work within a highly interactive and experienced team. Key job responsibilities In this role, you will: - Lead multiple electrical design and validation on multiple products across Amazon device portfolio - Research test/validation technologies and methodologies", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10430478/sr-hardware-development-engineer-centralized-electrical-engineer-cee-devices", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "3b061c5d927b2d8b327233813b3b48d1", "title": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid)", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Kanata, Ontario, Canada", "country": "CA", "employment_type": "full_time", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 6, "salary_min": 142000, "salary_max": 181600, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 142000, "base_salary_max": 181600, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 12, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 50, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0de35339b04f5511f2", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b061c5d927b2d8b327233813b3b48d1:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1d09fe05168187a6af", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b061c5d927b2d8b327233813b3b48d1:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b88e8d8751e0600325", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b061c5d927b2d8b327233813b3b48d1:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.58391162ba96155370", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b061c5d927b2d8b327233813b3b48d1:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6021003b1f6baae2fb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fe89c5dccbcaef3a0b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid) Kanata, Ontario, Canada The application window is expected to close on 2/17/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This role can be performed Hybrid with three days per week onsite at our Ottawa office. Acacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. Meet the Team We are Mixed-signal IC design group that develops high speed (>25Gb/s), and high accuracy, analog designs for optical communications products. We optimize design that will integrate into the ASIC. Our team interacts with other Acacia groups including digital/DSP design, system design, package design, and module design. Your Impact * You will use your knowledge of circuit designs including device theory and signal integrity to support issues found in the lab or by customer * You will analyze data from lab, identify the probable circuits, run post-layout simulations of the circuit in cadence, and correlate the observed issue to find root cause * You have hand-on experience in using the lab equipment such as DCA, spectrum analyzer, etc, and as well as familiar with python script * In addition to your sustaining role, you will also design, layout, measure and productize ultra-deep sub-micron-based CMOS products and participate in peer review of complex IC designs and provide solid design", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.723e3418c7199ff386", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Analog/Mixed-signal Sustaining IC Design Developer - Acacia (Hybrid)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.b70f6462aee94624aa", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b061c5d927b2d8b327233813b3b48d1", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Kanata-Ontario-Canada/Analog-Mixed-signal-Sustaining-IC-Design-Developer---Acacia--Hybrid-_2001523", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "af18b14c4cef11a0d60aac8cb6da8326", "title": "Technical Program Manager - Hardware Product Engineering", "employer_name": "Aurora Innovation, Inc.", "employer_slug": "aurora-innovation", "location_text": "Mountain View, California", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 181000, "salary_max": 262500, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 181000, "base_salary_max": 262500, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-12-19T20:14:07.000Z", "apply_url": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Technical Program Manager - Hardware Product Engineering Mountain View, California Who we are Aurora's mission is to deliver the benefits of self-driving technology safely, quickly, and broadly. The Aurora Driver will create a new era in mobility and logistics, one that will bring a safer, more efficient, and more accessible future to everyone. At Aurora, you will tackle massively complex problems alongside other passionate, intelligent individuals, growing as an expert while expanding your knowledge. For the latest news from Aurora, visit aurora.tech or follow us on LinkedIn . Aurora hires talented people with diverse backgrounds who are ready to help build a transportation ecosystem that will make our roads safer, get crucial goods where they need to go, and make mobility more efficient and accessible for all. We're searching for a Staff Technical Program Manager - Vehicle Hardware V&V. The TPM drives the detailed, bottoms-up engineering for key modules and developments that integrate into top-level, vehicle program objectives. TPMs are responsible for developing and publishing consolidated schedules that balance engineering development risk with program requirements. TPMs work with internal and external stakeholders to identify requirements, track risks, set appropriate check-points, and drive technical alignment. In the tactical day-to-day development throughout the product life cycle, the TPM manages and communicates status, issues, and risks to, cross-functional partners and leadership across the company. The TPM also supports the development strategies for multi-generational hardware developments. In this role you will: - Be responsible for planning, coordinating, and managing execution of vehicle hardware verification", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1828108/000182810826000016/aur-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1828108/000182810826000016/aur-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "operations", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": 35, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.5f6d5fc863977da528", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "af18b14c4cef11a0d60aac8cb6da8326", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Aurora Innovation, Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.15cefea537a7ff3c5d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "af18b14c4cef11a0d60aac8cb6da8326", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "operations", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:af18b14c4cef11a0d60aac8cb6da8326:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1828108/000182810826000016/aur-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1828108/000182810826000016/aur-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://aurora.tech/jobs/8343467002?gh_jid=8343467002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "7ae089708c568d3ea745cc9a53b8329f", "title": "Memory circuit design engineer - 3.", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Zhubei, Taiwan", "country": "TW", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.04f720c3f1fd7b1470", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7ae089708c568d3ea745cc9a53b8329f:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7f75a7c6e18c23e41f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7ae089708c568d3ea745cc9a53b8329f:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.85e220106cc833f539", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7ae089708c568d3ea745cc9a53b8329f:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ec64bb3b3ec2103d86", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7ae089708c568d3ea745cc9a53b8329f:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.b104c0dad1a34c9a52", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Memory circuit design engineer - 3.", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7ae089708c568d3ea745cc9a53b8329f:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.15b6ec88a8d9d61c8b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.66a4baf2cb8421b1af", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Memory circuit design engineer - 3. Zhubei, Taiwan The Memory Circuit Design Engineer is responsible for designing, developing, and testing memory circuits used in electronic systems. This role involves collaborating with cross-functional teams to oversee the entire lifecycle of memory circuit projects from conceptualization through prototyping, testing, and production. The engineer ensures designs meet performance, reliability, and safety standards while maintaining detailed documentation of design processes and project progress. Key Responsibilities: Design and develop memory circuits including SRAM, and other memory technologies. Create detailed circuit schematics, and simulations to validate design functionality. Collaborate with manufacturing, testing, and senior engineering teams to ensure successful product development and integration. Conduct prototype development, testing, and debugging to optimize circuit performance and reliability. Maintain comprehensive documentation of design processes, test results, and project schedules. Ensure compliance with industry standards, safety regulations, and company policies. Stay updated with the latest technological advancements and trends in memory circuit design. Participate in design reviews and provide technical guidance to junior engineers. Support troubleshooting and resolution of memory-related issues in hardware products. Required Skills and Qualifications: Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or related field. 3+ years' relevant experience and strong knowledge of semiconductor memory technologies and circuit design principles. Experience with CAD tools for circuit design and simulation (e.g., Cadence, Synopsys). Excellent problem-solving skills and attention to details. Ability to work collaboratively in cross-functional teams. Strong documentation and communication skills. Preferred Qualifications: Experience with low-power memory circuit design. Knowledge of signal integrity and timing", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.907c30951544a966c6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Memory circuit design engineer - 3.", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.fbc3f82ac61aafdb7b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7ae089708c568d3ea745cc9a53b8329f", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Zhubei-Taiwan/Memory-circuit-design-engineer---3_2009413", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "82594b95317916562dc5ec7572270a2e", "title": "Front-End CAD Methodology Engineer – Design/DV Interface", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Francisco Bay Area, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 212000, "salary_max": 386300, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 212000, "base_salary_max": 386300, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-28T01:52:07.157Z", "apply_url": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Front-End CAD Methodology Engineer – Design/DV Interface San Francisco Bay Area, United States of America Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! The Front-End CAD Methodology Engineer plays a key role in promoting and driving robust, scalable methodology solutions across RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced automations and GenAI-driven capabilities to enhance engineering productivity, improve methodology quality, and enable intelligent workflow optimization across static verification, formal verification, simulation and emulation domains. This position requires a combination of deep technical expertise, architectural vision, and technical leadership to identify high-impact opportunities, design and architect innovative solutions, including GenAI-enabled tooling, and drive adoption across a large globally distributed engineering organization. You will work closely with the different design organizations and CAD teams to translate complex engineering challenges into scalable, reusable, and forward-looking methodology solutions that accelerate silicon development and verification while maintaining the highest standards of quality and efficiency. In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 15, "years_experience_max": 15, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fddd8635b6e93c8b62", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "82594b95317916562dc5ec7572270a2e", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Front-End CAD Methodology Engineer – Design/DV Interface San Francisco Bay Area, United States of America Do you love building elegant solutions to highly complex challenges? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and efficiently handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! The Front-End CAD Methodology Engineer plays a key role in promoting and driving robust, scalable methodology solutions across RTL Design and DV teams within Apple's HWTech organization. This role leverages advanced automations and GenAI-driven capabilities to enhance engineering productivity, improve methodology quality, and enable intelligent workflow optimization across static verification, formal verification, simulation and emulation domains. This position requires a combination of deep technical expertise, architectural vision, and technical leadership to identify high-impact opportunities, design and architect innovative solutions, including GenAI-enabled tooling, and drive adoption across a large globally distributed engineering organization. You will work closely with the different design organizations and CAD teams to translate complex engineering challenges into scalable, reusable, and forward-looking methodology solutions that accelerate silicon development and verification while maintaining the highest standards of quality and efficiency. In short, this position focuses in fostering our North Star and making sure that our vision statement extends across the", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.9b7c31089aae70459c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "82594b95317916562dc5ec7572270a2e", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Front-End CAD Methodology Engineer – Design/DV Interface", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.82502780578acf2434", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "82594b95317916562dc5ec7572270a2e", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:82594b95317916562dc5ec7572270a2e:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649228/front-end-cad-methodology-engineer-design-dv-interface?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "948c1b428a6e03db8bfc708f45aac4f7", "title": "Hardware System Architect, Pixel Watch", "employer_name": "Google", "employer_slug": "google", "location_text": "Mountain View, CA, USA; +1 more", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 188000, "salary_max": 275000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 188000, "base_salary_max": 275000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-05T20:09:39.000Z", "apply_url": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "apply_url_verified": false, "ats": "google_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Hardware System Architect, Pixel Watch Mountain View, CA, USA; +1 more The Watch Hardware Engineering team is looking for a System Architect responsible for defining and implementing the hardware architecture for wearable products to enable ambient and edge computing applications. In this role, you will provide thought leadership in architecting the system design and platform architecture for next generation wearable products. The architect will ensure all subsystems work together to meet performance, power, and cost goals for all critical user journeys. This role involves an understanding and analysis of the data processing paths and associated hardware, silicon, and software solutions. You will collaborate cross-functionally both internally and externally with silicon vendors and technology partners. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Architect the data processing paths and hardware-software interfaces for ambient and edge computing applications on wearable hardware. Define system and component-level specifications for performance, power, and thermals. Support critical user journeys, including on-device AI", "parental_leave_weeks": 18, "non_birth_parent_leave_weeks": 18, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 94, "benefit_verified": true, "benefit_last_verified": "2026-05-07", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "parental_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "non_birth_parent_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 6, "years_experience_max": 10, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.270aa4e877a1a0c088", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "948c1b428a6e03db8bfc708f45aac4f7", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware System Architect, Pixel Watch Mountain View, CA, USA; +1 more The Watch Hardware Engineering team is looking for a System Architect responsible for defining and implementing the hardware architecture for wearable products to enable ambient and edge computing applications. In this role, you will provide thought leadership in architecting the system design and platform architecture for next generation wearable products. The architect will ensure all subsystems work together to meet performance, power, and cost goals for all critical user journeys. This role involves an understanding and analysis of the data processing paths and associated hardware, silicon, and software solutions. You will collaborate cross-functionally both internally and externally with silicon vendors and technology partners. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Architect the data processing paths and hardware-software interfaces for ambient and edge computing applications on wearable hardware. Define system and component-level specifications for performance, power, and thermals. Support critical user journeys, including on-device AI", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bed1afb86bbe2a873b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "948c1b428a6e03db8bfc708f45aac4f7", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware System Architect, Pixel Watch Mountain View, CA, USA; +1 more The Watch Hardware Engineering team is looking for a System Architect responsible for defining and implementing the hardware architecture for wearable products to enable ambient and edge computing applications. In this role, you will provide thought leadership in architecting the system design and platform architecture for next generation wearable products. The architect will ensure all subsystems work together to meet performance, power, and cost goals for all critical user journeys. This role involves an understanding and analysis of the data processing paths and associated hardware, silicon, and software solutions. You will collaborate cross-functionally both internally and externally with silicon vendors and technology partners. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Architect the data processing paths and hardware-software interfaces for ambient and edge computing applications on wearable hardware. Define system and component-level specifications for performance, power, and thermals. Support critical user journeys, including on-device AI", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ec1bcc0711dc4db124", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "948c1b428a6e03db8bfc708f45aac4f7", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware System Architect, Pixel Watch Mountain View, CA, USA; +1 more The Watch Hardware Engineering team is looking for a System Architect responsible for defining and implementing the hardware architecture for wearable products to enable ambient and edge computing applications. In this role, you will provide thought leadership in architecting the system design and platform architecture for next generation wearable products. The architect will ensure all subsystems work together to meet performance, power, and cost goals for all critical user journeys. This role involves an understanding and analysis of the data processing paths and associated hardware, silicon, and software solutions. You will collaborate cross-functionally both internally and externally with silicon vendors and technology partners. The Platforms and Devices team encompasses Google's various computing software platforms across environments (desktop, mobile, applications), as well as our first party devices and services that combine the best of Google AI, software, and hardware. Teams across this area research, design, and develop new technologies to make our user's interaction with computing faster and more seamless, building innovative experiences for our users around the world. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $188000 - $275000 (USD) + 20% bonus target + bonus + equity + benefits Learn more about benefits at Google . Architect the data processing paths and hardware-software interfaces for ambient and edge computing applications on wearable hardware. Define system and component-level specifications for performance, power, and thermals. Support critical user journeys, including on-device AI", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.3427f67daf813455a1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "948c1b428a6e03db8bfc708f45aac4f7", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:948c1b428a6e03db8bfc708f45aac4f7:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-05-07" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckZK3EGJd7ALuHA3Wtaylw1slZabHmkGEUilrYP51nWMaEjoACxwdTHOxmQ1h9dF-Rndz_3xDW3oeTO5OuK5MRaoS84FwNvkjCGdAuFEL-zLdIvZcdfeOF4WhyfV2_V2&loc=US&title=Hardware+System+Architect", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "3b22083ac89d716f4ee7a159ad7bccbd", "title": "PCB Layout Engineer, Amazon Leo", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Redmond, Washington, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 117300, "salary_max": 160000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 117300, "base_salary_max": 160000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": true, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-11-21T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "us_citizenship_required": { "field": "us_citizenship_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "us_citizenship_required" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "surrogacy_assistance_offered": { "field": "surrogacy_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "surrogacy_assistance_offered" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 4, "years_experience_max": 8, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": true, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1b7375b36447bdddad", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b22083ac89d716f4ee7a159ad7bccbd:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.214e74263387266245", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b22083ac89d716f4ee7a159ad7bccbd:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bf860ff2066c369ff4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3b22083ac89d716f4ee7a159ad7bccbd:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0c4fbd589cc9aeaf53", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4cddd625857a1d4c3e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7b94b22212c5a9ab81", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3b22083ac89d716f4ee7a159ad7bccbd", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "PCB Layout Engineer, Amazon Leo Redmond, Washington, USA Amazon Leo is Amazon's low Earth orbit satellite network. Our mission is to deliver fast, reliable internet connectivity to customers beyond the reach of existing networks. From individual households to schools, hospitals, businesses, and government agencies, Amazon Leo will serve people and organizations operating in locations without reliable connectivity. As a PCB Layout Engineer, you will participate in the definition and implementation of multiple spacecraft subsystems. This individual will contribute in all phases of system design and production. You must bring a combination of PCB design, assembly, test and fabrication knowledge, cross team functional interdependence, and demonstrable design process experience to the position. You will have the opportunity to work with multiple technical teams at Amazon in different locations. You should be comfortable with a high degree of ambiguity and relish the idea of solving problems that haven't been solved at scale before. Along the way, we guarantee that you will learn a lot, have fun and make a positive impact on millions of people. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Key job responsibilities Create the physical layout of a PCB from concept to fabrication using Cadence Allegro or Mentor Xpedition in a highly collaborative design environment. Basic Qualifications: - Bachelor's degree in Computer Science, Computer Engineering, Electrical Engineering,", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "surrogacy_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3130982/pcb-layout-engineer-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "6673af001de5fa108be007dd2ef71dd4", "title": "Analog Design Engineer Sr Staff", "employer_name": "d-Matrix", "employer_slug": "d-matrix", "location_text": "Santa Clara, Santa Clara, Ca, Ca, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-03-19T20:11:26.139Z", "apply_url": "https://jobs.ashbyhq.com/d-matrix/8cd5868b-fe7e-429d-bf5a-63b551036878", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9f98141c794e6f7f89", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6673af001de5fa108be007dd2ef71dd4:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ce26f7da3704fc4adb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6673af001de5fa108be007dd2ef71dd4:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.da6406fa360ae73982", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6673af001de5fa108be007dd2ef71dd4:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.5df76979ab58e9fc5c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Analog Design Engineer Sr Staff", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6673af001de5fa108be007dd2ef71dd4:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ca1c944afac5b32b50", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fda2976477ea3cc9d0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Design Engineer Sr Staff Santa Clara, Santa Clara, Ca, Ca, United States At d-Matrix , we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration. We value humility and believe in direct communication. Our team is inclusive , and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together , we can help shape the endless possibilities of AI. Location: Hybrid, working onsite at our Santa Clara, Ca headquarters 3-5 days per week. The role: Analog Design Engineer, Senior / Staff /Sr. Staff What You Will Do: Analog-mixed signal integrated circuit design using (but not limited to) common circuit design tools from Cadence and Synopsys. Design state of the art In-Memory-Compute engine for Artificial Intelligence Inference Accelerator and High-Speed Die-2-Die Interface for scale-out. Job scope includes schematic circuit design, system level performance analysis, design test benches for simulations and verifications, guide layout engineers on layout in deep sub-micron process nodes from 4nm and below, and to optimize design and layout to achieve low power design performance over process-voltage-temperature corners and six-sigma Monte-Carlo yield analysis. • Independent minor layout tweaks when necessary. • Work with backend engineers on integration of design/layout. • Provide model of circuit for backend verification. • Participate in", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.cec254ad1d7973cb80", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6673af001de5fa108be007dd2ef71dd4", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Analog Design Engineer Sr Staff", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/d-matrix/8cd5868b-fe7e-429d-bf5a-63b551036878", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/d-matrix/8cd5868b-fe7e-429d-bf5a-63b551036878", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "46a8e8346409c975908198bb140566d0", "title": "Media-IP SoC Performance Engineer, Platform Architecture", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Cupertino, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 126800, "salary_max": 190900, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 126800, "base_salary_max": 190900, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-11-13T20:21:43.846Z", "apply_url": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Media-IP SoC Performance Engineer, Platform Architecture Cupertino, United States of America Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture forward-thinking who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to design how all our technologies work in unison! We are looking for a Media-IP SoC Performance Engineer to join our small, dynamic team at Apple. We own the performance models of several complex multi-media IPs that power Apple's SoCs-technology that's central to the customer experience across nearly every Apple product, from Apple Watch and iPhone to iPad, Mac, Vision Pro (AR/VR), and next-generation product lines. In this highly visible role, you will collaborate closely with cross-functional teams to help define the architecture of new features and optimize trade-offs between performance, power, and area for these Media-IPs using a variety of sources ranging from performance models to released devices. The end goal is to provide data-driven performance architectural insights that provide the best customer experience. Collaborate with functional architects, design, and software teams to plan, implement, validate, and correlate high-level C++ performance models Develop custom tools and approaches for analyzing and visualizing performance data, applying data science and machine learning techniques to provide architectural insights Present performance study results to cross-functional teams to inform and drive architectural decisions Validate the performance models against the specification and correlating the", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c484a669411a748cc4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "46a8e8346409c975908198bb140566d0", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Media-IP SoC Performance Engineer, Platform Architecture Cupertino, United States of America Do you love crafting elegant solutions to highly complex challenges? Are you a big-picture forward-thinking who understands how each element affects all the others? At Apple, our Architecture group is responsible for connecting our hardware and software into one unified system. Join this team, and you'll collaborate with engineers across Apple to design how all our technologies work in unison! We are looking for a Media-IP SoC Performance Engineer to join our small, dynamic team at Apple. We own the performance models of several complex multi-media IPs that power Apple's SoCs-technology that's central to the customer experience across nearly every Apple product, from Apple Watch and iPhone to iPad, Mac, Vision Pro (AR/VR), and next-generation product lines. In this highly visible role, you will collaborate closely with cross-functional teams to help define the architecture of new features and optimize trade-offs between performance, power, and area for these Media-IPs using a variety of sources ranging from performance models to released devices. The end goal is to provide data-driven performance architectural insights that provide the best customer experience. Collaborate with functional architects, design, and software teams to plan, implement, validate, and correlate high-level C++ performance models Develop custom tools and approaches for analyzing and visualizing performance data, applying data science and machine learning techniques to provide architectural insights Present performance study results to cross-functional teams to inform and drive architectural decisions Validate the performance models against the specification and correlating the", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.e32bf221f4828612f6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "46a8e8346409c975908198bb140566d0", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:46a8e8346409c975908198bb140566d0:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200632004/media-ip-soc-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "a259b004cbd6f721effd72cd05fc0030", "title": "Product Operations", "employer_name": "Plaid", "employer_slug": "plaid", "location_text": "San Francisco HQ, San Francisco, California, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn", "a16z" ], "posted_at": "2026-04-01T22:12:04.558Z", "apply_url": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": 16, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 8, "years_experience_max": 12, "role_function": "product", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "growth-stage", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.25cea8d7983692ebc0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a259b004cbd6f721effd72cd05fc0030:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4c590cbdac0f20f418", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a259b004cbd6f721effd72cd05fc0030:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.713ff13114f9924573", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a259b004cbd6f721effd72cd05fc0030:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bb73f6941e17461fa6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a259b004cbd6f721effd72cd05fc0030:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0381289eca8a6464e0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4b0f2ed62d4117a1b3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.81855dba0a0072d994", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a259b004cbd6f721effd72cd05fc0030", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Operations San Francisco HQ, San Francisco, California, United States We believe that the way people interact with their finances will drastically improve in the next few years. We're dedicated to empowering this transformation by building the tools and experiences that thousands of developers use to create their own products. Plaid powers the tools millions of people rely on to live a healthier financial life. We work with thousands of companies like Venmo, SoFi, several of the Fortune 500, and many of the largest banks to make it easy for people to connect their financial accounts to the apps and services they want to use. Plaid's network covers 12,000 financial institutions across the US, Canada, UK and Europe. Founded in 2013, the company is headquartered in San Francisco with offices in New York, Washington D.C., London and Amsterdam. As our founding Product Operations Lead, you will define and own the operational backbone of the Product organization. You will work closely with Product, Engineering, Design, and Product Marketing to build the systems, cadences, and standards that help teams execute consistently and at high quality . You are a hands-on builder who enjoys operating from first principles and defining long-term strategy for your domain . Responsibilities: - Own and evolve the operating system used by Product to plan, track, and communicate work, including roadmaps, planning artifacts, and execution tracking (in close partnership with Engineering Operations). - Design and run lightweight operating cadences (e.g., planning cycles, product reviews, execution check-ins) - Improve visibility", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/plaid/a7470e5b-2761-4251-9a59-a52c0f7c0e90", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "title": "Signal/Power Integrity Eng, Annapurna Labs", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Austin, Texas, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 136000, "salary_max": 184000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 136000, "base_salary_max": 184000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": true, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-09T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "surrogacy_assistance_offered": { "field": "surrogacy_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "surrogacy_assistance_offered" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.74cb03c6c2e337aaea", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ce39f7bf2e9b2a01877e8ed993ec1bae:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9a6b4f7fa97a5015dc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ce39f7bf2e9b2a01877e8ed993ec1bae:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a00086f7984b33b3e9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ce39f7bf2e9b2a01877e8ed993ec1bae:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.09bf5485b495a09c34", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0c7e48923b06648c24", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5d7c863f77c90ce4eb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Signal/Power Integrity Eng, Annapurna Labs Austin, Texas, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. We are seeking a SI/PI Engineer (Signal Integrity and Power Integrity) who will play a key role in the definition, design and validation of AWS next generation machine learning ASICs. As a member of our hardware team, you will have a meaningful opportunity to participate in the design and execution of all SI related topics, with the goal of creating and customized platforms that fit within AWS datacenter's world leading technology. Key job responsibilities Our engineers collaborate across diverse teams, projects, and environments to have a firsthand impact on our global customer base. You'll bring a passion for innovation, data, and hardware knowledge. You'll also solve challenging technical problems, often ones not solved before, at every layer of the design. This Signal Integrity Engineering role combines technical expertise with strategic design leadership. The ideal candidate will bring 3+ years of experience in signal and power integrity, with hands-on expertise in simulation tools like Hspice, Cadence, and HFSS. The role involves working with advanced packaging technologies, PCB design, and power delivery systems. Additional experience with die capacitors, SOC power, and 3D/2.5D EMIR simulation tools would be", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "surrogacy_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10387645/signal-power-integrity-eng-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "33b8e542f5c81757f3ad0315c0fbcd3d", "title": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Boise, Idaho, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 159200, "salary_max": 215300, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 159200, "base_salary_max": 215300, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-23T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.185f1a929e11833c66", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:33b8e542f5c81757f3ad0315c0fbcd3d:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7989ac3c78b36715d9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:33b8e542f5c81757f3ad0315c0fbcd3d:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a047e29b5e818e30de", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:33b8e542f5c81757f3ad0315c0fbcd3d:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.516c1f15c1aa01c6f7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:33b8e542f5c81757f3ad0315c0fbcd3d:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.58db814c3fd61ebad3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7c5a3ce9d7e9b6d2e6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design Boise, Idaho, USA Amazon Lab126 is an inventive research and development company that designs and engineers high-profile consumer electronics. Lab126 began in 2004 as a subsidiary of Amazon.com, Inc., originally creating the best-selling Kindle family of products. Since then, we have produced innovative devices like Fire tablets, Fire TV and Amazon Echo. What will you help us create? The Role: As a Senior Computer Aided Design (CAD) Engineer, you will be part of an advanced ASIC development team that is creating the semiconductor designs which will power millions of new Amazon devices. You will work closely with multi-disciplinary groups including Design, Verification, Physical Design, and Emulation teams to build and maintain a leading-edge ASIC development infrastructure that enables and accelerates their work. Key job responsibilities * Design and maintain ASIC development flows spanning RTL-to-GDSII, including RTL generation, simulation, synthesis, place & route, timing analysis, DRC/LVS, and sign-off * Deploy and configure EDA tools from vendors (Synopsys, Cadence, Mentor/Siemens, etc.) across compute infrastructure * Develop automation and CI/CD/regression to streamline design tasks, reduce manual effort, and improve consistency * Troubleshoot tool issues and work with vendors to resolve bugs, performance bottlenecks, or licensing problems * Work with IT teams to optimize compute and storage strategies to enhance engineering efficiency * Create and maintain documentation for tool usage, flow methodologies, and best practices * Utilization of AI tools to accelerate troubleshooting and monitoring of design flows A day in the life Your day starts", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.413c00972db4e57b64", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior CAD Engineer, ASIC Development Infrastructure, RTL Design", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3187150/senior-cad-engineer-asic-development-infrastructure-rtl-design", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "07d2a63b9adc8f26aa5dc500a362d548", "title": "High-Speed I/F Subsystem Design Engineer", "employer_name": "Renesas Electronics", "employer_slug": "renesas-electronics", "location_text": "Kodaira, , Japan", "country": "JP", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000118383975-high-speed-i-f-subsystem-design-engineer", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "High-Speed I/F Subsystem Design Engineer Kodaira, , Japan Company Description: Job Description: 【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability. As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important. In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint. By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs. 【Job Description】 Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable. Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness. Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bb0c9eaa666fa6df48", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "07d2a63b9adc8f26aa5dc500a362d548", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "High-Speed I/F Subsystem Design Engineer Kodaira, , Japan Company Description: Job Description: 【Background of the Recruitment】 As automotive electrification and intelligence continue to advance, automotive SoCs have become a core technology that directly supports vehicle performance and functionality. The R-Car series has evolved as a large-scale automotive SoC through the advanced integration of a wide range of IPs, including CPU, high‑speed interfaces, memory, AI/video, functional safety, and security. Among these technologies, high‑speed SerDes interfaces such as PCIe and CSI and DP and UCIe play a critical role in overall system performance and reliability. As interface speeds continue to increase and system complexity grows, ensuring quality through thorough silicon‑level evaluation and signal integrity verification has become increasingly important. In this context, we are seeking a technical leader who has hands‑on experience in high‑speed SerDes interface evaluation and can work closely with design teams and IP vendors to lead evaluation activities from a technical standpoint. By taking ownership of evaluation and contributing technical judgment to development, this role is expected to play a key part in improving the overall quality of our automotive SoCs. 【Job Description】 Lead the technical execution of high‑speed SerDes interface evaluation for automotive SoCs (R-Car series), covering interfaces such as PCIe, CSI, DP, UCIe, SerDes PHY, and other high‑speed I/F as applicable. Drive evaluation activities including silicon/board-level testing, signal integrity/quality assessment, stress testing, and standards/compliance confirmation, ensuring interface quality and robustness. Define and align evaluation strategy, organize test items, and consolidate evaluation results into actionable outputs for stakeholders.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.8b2271460e3fd87d0f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "07d2a63b9adc8f26aa5dc500a362d548", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "High-Speed I/F Subsystem Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.5a59c9163fa824a008", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "07d2a63b9adc8f26aa5dc500a362d548", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "data", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:07d2a63b9adc8f26aa5dc500a362d548:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000118383975-high-speed-i-f-subsystem-design-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000118383975-high-speed-i-f-subsystem-design-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000118383975-high-speed-i-f-subsystem-design-engineer", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "302fe92d31fb3ee214ed6c0848f80d03", "title": "FE Design and Timing Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Diego, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 120300, "salary_max": 210100, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 120300, "base_salary_max": 210100, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-16T22:06:55.197Z", "apply_url": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "FE Design and Timing Engineer San Diego, United States of America Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple's products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4795be20f632f2e5a6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "302fe92d31fb3ee214ed6c0848f80d03", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "FE Design and Timing Engineer San Diego, United States of America Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple's products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c8370c328b2a5a2bf7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "302fe92d31fb3ee214ed6c0848f80d03", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "FE Design and Timing Engineer San Diego, United States of America Come and join Apple's growing wireless silicon development team. Our wireless SoC organization is responsible for all aspects of wireless silicon development, emphasizing highly energy-efficient design and new technologies that transform the user experience at the product level. All of this is driven by a world-class vertically integrated engineering team spanning RF/Analog architecture and design, Systems/PHY/MAC architecture and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. If you enjoy a fast-paced and challenging environment, collaborate with people across different functional areas, and thrive during crisis times, we encourage you to apply. In this role you will work on a small team dedicated to implementing high performance, low power wireless SoCs from RTL to delivery of our final GDSII. There will be the opportunity to work closely with multi-disciplinary groups to meet power, performance, and area goals for Apple's products. You will interact with RTL designers to understand design intent and clock structure, with CAD to understand and develop flows, with UPF and DFT teams to insert power and test structures, and with Physical design team to close and sign-off timing. Collaboration will be needed to make sure designs are delivered on time and with the highest quality by incorporating targeted checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC creation effort, interfacing with all disciplines, with a critical impact in", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.dac2d55e27bc6ad0bf", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "302fe92d31fb3ee214ed6c0848f80d03", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "FE Design and Timing Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.dd35471f0103224123", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "302fe92d31fb3ee214ed6c0848f80d03", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:302fe92d31fb3ee214ed6c0848f80d03:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658465/fe-design-and-timing-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "b1c74eadba8cd0fe30b9aa664f60ac88", "title": "Sensor Electrical Engineer, Amazon Robotics", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "North Reading, Massachusetts, USA", "country": "US", "employment_type": "temporary", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 137300, "salary_max": 185700, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 137300, "base_salary_max": 185700, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-15T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "contractor", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.170742772cafd0d061", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b1c74eadba8cd0fe30b9aa664f60ac88:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6b6ff3e85778b00c4d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b1c74eadba8cd0fe30b9aa664f60ac88:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c823c995d5b758a43c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b1c74eadba8cd0fe30b9aa664f60ac88:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.247986fe9d1fa4c525", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.778f49aec536cbf611", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e04ebf25e9cbd062f0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sensor Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Amazon is seeking a talented and motivated Sensor Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, analog and digital circuit design, possess good communication skills, and have complete ownership of development and productization of a sensor system. The candidate will have strong technical expertise to deliver unsupervised, as well as great leadership skills to work with internal customers and external partners. Key job responsibilities - Oversee an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification. - Develop requirements, functional specifications, DVT plans and test procedures. - Build and facilitate concept prototype systems consisting of a mix of in house and OTS components. - Design, implement and debug embedded systems, analog, and digital circuits. - Facilitate product releases to manufacturing and customer deployments. - Research and advocate for new technologies and projects to help the business. - Oversee characterization of new internally developed or OTS sensors. - Write papers to drive strategic initiatives for Amazon Robotics. - Mentor junior engineers, provide advice and direction to outside projects/other groups. - Participate in program and design reviews. - Ensure program goals are met, working outside of your comfort zone. - Provide structure where there is ambiguity - Present work through papers and presentations at internal conferences. - Oversee development contracts with outside vendors. - Be comfortable communicating clearly and succinctly in", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10421823/sensor-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "f9d3267c5393c0125181c203ab0deb49", "title": "Power Design Hardware Engineer - Acacia (Hybrid)", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "2 Locations", "country": "unknown", "employment_type": "full_time", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 3, "salary_min": 168800, "salary_max": 241200, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 168800, "base_salary_max": 241200, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Power Design Hardware Engineer - Acacia (Hybrid) 2 Locations The application window is expected to close on: 02/12/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on: 3/31/26. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 50, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1afc2e4a24dd07bf51", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power Design Hardware Engineer - Acacia (Hybrid) 2 Locations The application window is expected to close on: 02/12/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on: 3/31/26. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f9d3267c5393c0125181c203ab0deb49:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2b6b5c62d2aebedc0a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power Design Hardware Engineer - Acacia (Hybrid) 2 Locations The application window is expected to close on: 02/12/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on: 3/31/26. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f9d3267c5393c0125181c203ab0deb49:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.adbba4290e4b3167a4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Power Design Hardware Engineer - Acacia (Hybrid)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f9d3267c5393c0125181c203ab0deb49:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e7a70b9467022da7be", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power Design Hardware Engineer - Acacia (Hybrid) 2 Locations The application window is expected to close on: 02/12/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . The application window is expected to close on: 3/31/26. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. This is a hybrid role with three day per week at our Maynard, MA or San Jose, CA office. Meet the Team You will work with a versatile and upbeat team of enthusiastic engineers in an environment where team members experience mutual enhancement and improvement. You will have the opportunity to collaborate cross-functionally with our Hardware, Mechanical Engineering, Optics, and manufacturing Process Engineering teams. Your Impact You will be key member of Acacia's Hardware Team. The Power Design Engineer will lead the design of DC-DC switch-mode power supplies and component selection. The successful candidate will work across disciplines to assure power supply designs meet the power, thermal, and safety requirements of the system specification. You will work closely with Acacia's multi-disciplinary engineering and manufacturing teams to understand the system requirements and contribute or lead the specification, design, and debug of complex power delivery systems for our products. * Architecture: Lead and contribute to power delivery system architecture and specifications. * Design: Design, analysis, and simulation of high current and low noise power delivery circuits. Debug: Contribute to system bring up, debug, and", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.5c555d817e4c01e87b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Power Design Hardware Engineer - Acacia (Hybrid)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.821b231c625e55771f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9d3267c5393c0125181c203ab0deb49", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Maynard-Massachusetts-US/Power-Design-Hardware-Engineer---Acacia_1450611", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "bdacc30d2605ce3d2d7e4739a5960bb6", "title": "Senior Motion Systems Engineer, Actuators", "employer_name": "Waymo", "employer_slug": "waymo", "location_text": "Mountain View, Ca, USA", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 196000, "salary_max": 248000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 196000, "base_salary_max": 248000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "a16z", "sequoia" ], "posted_at": "2025-12-26T20:47:03.000Z", "apply_url": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Motion Systems Engineer, Actuators Mountain View, Ca, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and you will report to a Vehicle Systems Architecture Lead. You will: - Translate product and safety goals into tangible technical requirements. You will drive architectural trade-off discussions regarding performance, fault tolerance, and reliability - Serve as the primary technical interface between internal software teams and external hardware suppliers (OEMs/Tier 1s) to resolve integration gaps and deviations early in the design phase - Review verification strategies for qualifying", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "contractor_type": { "field": "contractor_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "contractor_type" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": 20, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.10d8766fde9d1b2e08", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "bdacc30d2605ce3d2d7e4739a5960bb6", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Motion Systems Engineer, Actuators Mountain View, Ca, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and you will report to a Vehicle Systems Architecture Lead. You will: - Translate product and safety goals into tangible technical requirements. You will drive architectural trade-off discussions regarding performance, fault tolerance, and reliability - Serve as the primary technical interface between internal software teams and external hardware suppliers (OEMs/Tier 1s) to resolve integration gaps and deviations early in the design phase - Review verification strategies for qualifying", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7e461337743838d044", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "bdacc30d2605ce3d2d7e4739a5960bb6", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Motion Systems Engineer, Actuators Mountain View, Ca, USA Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and you will report to a Vehicle Systems Architecture Lead. You will: - Translate product and safety goals into tangible technical requirements. You will drive architectural trade-off discussions regarding performance, fault tolerance, and reliability - Serve as the primary technical interface between internal software teams and external hardware suppliers (OEMs/Tier 1s) to resolve integration gaps and deviations early in the design phase - Review verification strategies for qualifying", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.213930e596802ed571", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "bdacc30d2605ce3d2d7e4739a5960bb6", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Motion Systems Engineer, Actuators", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.a6c5b4e1ddeadd4a71", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "bdacc30d2605ce3d2d7e4739a5960bb6", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:bdacc30d2605ce3d2d7e4739a5960bb6:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7490150", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "title": "PE Physical Design", "employer_name": "Rambus INC", "employer_slug": "rambus", "location_text": "Bangalore, KA, IN", "country": "IN", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "base_plus_commission", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-03-27T04:00:00.000Z", "apply_url": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "apply_url_verified": true, "ats": "icims", "url_last_checked_alive": "2026-07-20T05:40:24.917Z", "removed_at": null, "description_excerpt": "PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/917273/000119312526057101/rmbs-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/917273/000119312526057101/rmbs-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.14b717bec78909a72e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8ec9eb4c637a41a4c0ce0fa951cf3789:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9cd78b3a7cc0db5fbc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8ec9eb4c637a41a4c0ce0fa951cf3789:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.36034312b8f9e1984d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "Rambus INC", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8ec9eb4c637a41a4c0ce0fa951cf3789:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.role_function.a096a618c0f1c91b1a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Role: \"design\"", "tooltip": "Role matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8ec9eb4c637a41a4c0ce0fa951cf3789:role-function:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.9f17e121cc7ae6567c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "PE Physical Design", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8ec9eb4c637a41a4c0ce0fa951cf3789:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.46227e64a79201442d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "PE Physical Design Bangalore, KA, IN Overview Rambus, a premier chip and silicon IP provider making data faster and safer, is seeking to hire an exceptional PE Physical Design Engineer to join our Silicon IP team in Bangalore. In this role, you will be working with some of the brightest inventors and engineers in the world developing products that make data faster and safer. Responsibilities Own end-to-end physical implementation for major IP blocks and/or full-chip designs. Develop and optimize floorplans (macro placement, IO ring planning, power grid design, congestion/area/timing analysis) Execute place-and-route, clock tree synthesis, and timing closure using industry-standard tools (Cadence Innovus). Perform detailed static timing analysis (STA) and drive sign-off across PVT corners and operating modes. Identify and resolve physical verification issues (DRC/LVS/ERC) in close partnership with process/CAD/foundry teams, ensuring robust manufacturability. Automate design flows (e.g., hierarchical PNR, IO ring automation, PG) to improve efficiency and quality; contribute to continuous flow enhancements. Collaborate with RTL, DFT, verification, package, and library teams to meet performance, power, and area (PPA) targets and project milestones. Mentor and coach junior engineers, sharing best practices in physical design and advancing team capability. Document methodologies and contribute to best practices, supporting a culture of learning and continuous improvement. Demonstrate Rambus values by being agile in adapting to changing business needs, leading by example, and striving for best-in-class results Qualifications Must have minimum Bachelors degree in EE/ECE (degree's related to electronics) from a reputed institute. Must have at least 10 years of experience, out of", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.b33da863b8b1b1d10b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Rambus INC", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.95cd7c870da2c017d4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "PE Physical Design", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.a8f5f97b3060c30977", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "source_label": "Apply link", "source_date": "2026-07-20T05:40:24.917Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-07-20T05:40:24.917Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-07-20T05:40:24.917Z", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/917273/000119312526057101/rmbs-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/917273/000119312526057101/rmbs-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-rambus.icims.com/jobs/22898/pe-physical-design/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "4bd195f65b04314533d6d13ac5d3994c", "title": "Staff Hardware Engineer, Charging Systems", "employer_name": "Waymo", "employer_slug": "waymo", "location_text": "Mountain View, CA, US", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 230000, "salary_max": 284000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 230000, "base_salary_max": 284000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "a16z", "sequoia" ], "posted_at": "2026-05-01T18:52:22.000Z", "apply_url": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Staff Hardware Engineer, Charging Systems Mountain View, CA, US Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and reports to a Hardware Engineering Lead. You will: - Architect, specify, and configure high power chargers for Waymo depots - Validate charger system requirements and specifications - Design and execute validation tests to confirm charger performance and reliability - Debug and triage charger failures from the field - Evaluate and select new charger hardware architectures and technologies You have: - BS or MS degree in Electrical Engineering,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "contractor_type": { "field": "contractor_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "contractor_type" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": 10, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8543d835ecf30e1e93", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4bd195f65b04314533d6d13ac5d3994c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Staff Hardware Engineer, Charging Systems Mountain View, CA, US Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and reports to a Hardware Engineering Lead. You will: - Architect, specify, and configure high power chargers for Waymo depots - Validate charger system requirements and specifications - Design and execute validation tests to confirm charger performance and reliability - Debug and triage charger failures from the field - Evaluate and select new charger hardware architectures and technologies You have: - BS or MS degree in Electrical Engineering,", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c267c64d87ac1d4cb2", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4bd195f65b04314533d6d13ac5d3994c", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Staff Hardware Engineer, Charging Systems Mountain View, CA, US Waymo is an autonomous driving technology company with the mission to be the world's most trusted driver. Since its start as the Google Self-Driving Car Project in 2009, Waymo has focused on building the Waymo Driver-The World's Most Experienced Driver™-to improve access to mobility while saving thousands of lives now lost to traffic crashes. The Waymo Driver powers Waymo's fully autonomous ride-hail service and can also be applied to a range of vehicle platforms and product use cases. The Waymo Driver has provided over ten million rider-only trips, enabled by its experience autonomously driving over 100 million miles on public roads and tens of billions in simulation across 15+ U.S. states. Hardware Engineering is an innovative and collaborative group of electrical, mechanical, reliability, software and vehicle engineers. We design, build, and perfect the products which are the eyes and ears of Waymo's autonomous driving technology, and integrate those products into vehicle platforms. We're seeking curious and talented teammates to keep us moving in the right direction. This role follows a hybrid work schedule and reports to a Hardware Engineering Lead. You will: - Architect, specify, and configure high power chargers for Waymo depots - Validate charger system requirements and specifications - Design and execute validation tests to confirm charger performance and reliability - Debug and triage charger failures from the field - Evaluate and select new charger hardware architectures and technologies You have: - BS or MS degree in Electrical Engineering,", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.ad8b3ac9c85af289ce", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4bd195f65b04314533d6d13ac5d3994c", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Staff Hardware Engineer, Charging Systems", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.ccf61ec7afdbf98ef0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4bd195f65b04314533d6d13ac5d3994c", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:4bd195f65b04314533d6d13ac5d3994c:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.withwaymo.com/jobs?gh_jid=7872767", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "0d028fae7bab8214e421c5996f506a36", "title": "SI/PI Engineer", "employer_name": "Etched", "employer_slug": "etched", "location_text": "San Jose, CA, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-04-30T23:08:16.449Z", "apply_url": "https://jobs.ashbyhq.com/etched/d02d77c6-5e99-4184-9e3b-a2180152f95d", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "security", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.13ea1c82fa9e5351ba", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0d028fae7bab8214e421c5996f506a36:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7e2362b7b5175ae2c8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0d028fae7bab8214e421c5996f506a36:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8c1135843cd7132320", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0d028fae7bab8214e421c5996f506a36:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.561a8d022a2e334189", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bf66c6dc67d93f4970", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d3fa9e8da7b347c125", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0d028fae7bab8214e421c5996f506a36", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SI/PI Engineer San Jose, CA, United States About Etched Etched is building the world's first AI inference system purpose-built for transformers - delivering over 10x higher performance and dramatically lower cost and latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents. Backed by hundreds of millions from top-tier investors and staffed by leading engineers, Etched is redefining the infrastructure layer for the fastest growing industry in history. Job Summary We are looking for a Signal Integrity and Power Integrity (SI/PI) Engineer to join our platform electrical engineering team. In this role, you will own the SI/PI methodology for high-speed PCB and system designs - from early architecture through final release - ensuring electrical margins are met across interfaces running at multi-gigabit data rates. Key Responsibilities - Perform pre- and post-layout SI simulations for high-speed serial interfaces including PCIe Gen5/Gen6, 112G/224G Ethernet. - Conduct channel analysis and link budget calculations; define topology constraints, trace geometry, stack-up requirements, and via optimization guidelines for PCB designers. - Develop and maintain COM, IBIS, S-parameter, and SPICE models; correlate simulation results against lab measurements. - Execute power delivery network (PDN) design and analysis: target impedance profiling, decoupling capacitor selection, AC/DC power analysis, and IR-drop simulation. - Drive DFI and design rule checks for SI/PI compliance; work with layout teams in Cadence Allegro / Sigrity or Ansys SIwave. - Collaborate with PCB design and layout", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/d02d77c6-5e99-4184-9e3b-a2180152f95d", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/d02d77c6-5e99-4184-9e3b-a2180152f95d", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/d02d77c6-5e99-4184-9e3b-a2180152f95d", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "a7b866cb0f84dbbf978e80e810407ccd", "title": "Associate Backend Engineer", "employer_name": "Renesas Electronics", "employer_slug": "renesas-electronics", "location_text": "Ho Chi Minh, , Vietnam", "country": "VN", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-12T10:25:24.000Z", "apply_url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000131372011-associate-backend-engineer", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.51a0e1c9206f9f73d5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a7b866cb0f84dbbf978e80e810407ccd:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7a6deca840b7d225a2", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a7b866cb0f84dbbf978e80e810407ccd:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f62c6f2225e6a89306", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a7b866cb0f84dbbf978e80e810407ccd:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3c72b4ce624e6d668f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.47d513bc0e6c64bacd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.70fd5140ec7f4a87d5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a7b866cb0f84dbbf978e80e810407ccd", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Associate Backend Engineer Ho Chi Minh, , Vietnam Company Description: Job Description: Embedded Processing Group (DFT): Do DFT tasks MPU/MCU product, including Implementation and improving test coverage, verification, DFT SDC (timing constraint) design, Tester pattern making, Tester pattern debugging, ... Work closely with the FE/BE teams to complete the chip design within the defined schedule. High-Performance Computing Group (Physical Design) Physical Design: physical synthesis, place & route, timing closure, and timing/physical verification for IP, CPU, and Chip design. Qualifications: Undergraduate/Fresh graduate (for fresh engineer positions) majoring in Electronics, Telecommunications, Mechatronics, Automation, Computer Science, Computer Engineering, Information Technology, Mathematics, and Physics. Good at English in writing and speaking skills, distinguished competence, consistent pursuit of excellence, professional behavior, and good relationships with others and society. Have experience for one of related fields: HW FE/BE design (Logic architecture, Clock architecture, TPI), solid knowledge in using EDA tools (Synopsys, Cadence, Tessent, ...) are advantage Have a strong passion in the technical field, especially in chip design. Have logical thinking and explanation; be serious and mature in working attitude Long-term working commitment Additional Information: Renesas is an embedded semiconductor solution provider driven by its Purpose ' To Make Our Lives Easier .' As the industry's leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power. With a diverse team of", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000131372011-associate-backend-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000131372011-associate-backend-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000131372011-associate-backend-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c3027fb964fbdf21aa1d20808addfe8d", "title": "Senior Hardware Design Engineer", "employer_name": "Arista Networks", "employer_slug": "arista-networks", "location_text": "Bengaluru, KA, India", "country": "IN", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs.smartrecruiters.com/AristaNetworks/744000130863489-senior-hardware-design-engineer", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Hardware Design Engineer Bengaluru, KA, India Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: Who You'll Work With Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.df49470aba660a2806", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c3027fb964fbdf21aa1d20808addfe8d", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Hardware Design Engineer Bengaluru, KA, India Company Description: Arista Networks is an industry leader in data-driven, client-to-cloud networking for large data center, campus and routing environments. What sets us apart is our relentless pursuit of innovation. We leverage the latest advancements in cloud computing, artificial intelligence, and software-defined networking to provide our clients with a competitive edge in an increasingly interconnected world. Our solutions are designed to not only meet the current demands of the digital landscape but to also anticipate and adapt to future challenges. At Arista we value the diversity of thought and perspectives that each employee brings to the table. We believe that fostering an inclusive environment, where individuals from various backgrounds and experiences feel welcome, is essential for driving creativity and innovation. Our commitment to excellence has earned us several prestigious awards, such as Best Engineering Team, Best Company for Diversity, Compensation, and Work-Life Balance. At Arista, we take pride in our track record of success and strive to maintain the highest standards of quality and performance in everything we do. Job Description: Who You'll Work With Working closely with cross-functional teams including software, product management, and manufacturing, our engineers innovate on system architectures, high-speed PCB designs, and signal integrity to deliver state-of-the-art products that drive network performance and reliability. What You'll Do Our Hardware Design Engineering team is at the forefront of developing high-speed networking and Ethernet products used in Enterprise campuses, hyperscale datacenters and bleeding edge AI clusters. The team is responsible for", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.fe96ef4b785d12615f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c3027fb964fbdf21aa1d20808addfe8d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Hardware Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.c9446f0a64a68c69d7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c3027fb964fbdf21aa1d20808addfe8d", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "data", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c3027fb964fbdf21aa1d20808addfe8d:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000130863489-senior-hardware-design-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1596532/000159653226000013/anet-20251231.htm" ], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000130863489-senior-hardware-design-engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/AristaNetworks/744000130863489-senior-hardware-design-engineer", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": null } } }, { "id": "71d303448fcdc1e0e00c3479d83c61b5", "title": "Executive Assistant to the Chief Marketing Officer", "employer_name": "Bentley Systems", "employer_slug": "bentley-systems", "location_text": "Job Location - Country United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-12T10:25:24.000Z", "apply_url": "https://jobs.bentley.com/job/Remote-Executive-Assistant-to-the-Chief-Marketing-Officer-CO/1372804100/", "apply_url_verified": false, "ats": "successfactors", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Executive Assistant to the Chief Marketing Officer Job Location - Country United States Bentley's marketing organization is undergoing a transformation to become an AI native, globally scaled function driving global adoption of our broad, industry leading product portfolio. This transformation requires clarity, precision, speed, and disciplined execution at every level. The Executive Assistant to the CMO serves as a force multiplier within a global marketing organization of 160 colleagues. This is not a traditional administrative role. It is a strategic executive partnership role designed to ensure the CMO's time, attention, preparation, and energy are aligned to the highest impact priorities for the business. This role reports directly to the Chief of Staff to the CMO and works in close partnership with her. Together, they operate as a coordinated executive team. The Chief of Staff focuses on strategic alignment, cross functional initiatives, and executive priorities. The Executive Assistant focuses on ensuring adherence to operational cadences, preparation, precision, and executive readiness. This position is designed for a career Executive Assistant who is committed to the executive support profession. It is not a pathway role into marketing. Success in this role requires mastery of executive leverage, anticipation, and operational excellence. Success means the CMO is always prepared, never surprised, and consistently focused on the highest value outcomes. It means the marketing organization functions with predictable cadences, efficient use of travel and mee", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1031308/000103130826000007/bsy-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1031308/000103130826000007/bsy-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 8, "years_experience_max": 12, "role_function": "finance", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2e92118805cfad3a90", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Executive Assistant to the Chief Marketing Officer Job Location - Country United States Bentley's marketing organization is undergoing a transformation to become an AI native, globally scaled function driving global adoption of our broad, industry leading product portfolio. This transformation requires clarity, precision, speed, and disciplined execution at every level. The Executive Assistant to the CMO serves as a force multiplier within a global marketing organization of 160 colleagues. This is not a traditional administrative role. It is a strategic executive partnership role designed to ensure the CMO's time, attention, preparation, and energy are aligned to the highest impact priorities for the business. This role reports directly to the Chief of Staff to the CMO and works in close partnership with her. Together, they operate as a coordinated executive team. The Chief of Staff focuses on strategic alignment, cross functional initiatives, and executive priorities. The Executive Assistant focuses on ensuring adherence to operational cadences, preparation, precision, and executive readiness. This position is designed for a career Executive Assistant who is committed to the executive support profession. It is not a pathway role into marketing. Success in this role requires mastery of executive leverage, anticipation, and operational excellence. Success means the CMO is always prepared, never surprised, and consistently focused on the highest value outcomes. It means the marketing organization functions with predictable cadences, efficient use of travel and mee", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:71d303448fcdc1e0e00c3479d83c61b5:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c1845adb60aeeed2e0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Executive Assistant to the Chief Marketing Officer Job Location - Country United States Bentley's marketing organization is undergoing a transformation to become an AI native, globally scaled function driving global adoption of our broad, industry leading product portfolio. This transformation requires clarity, precision, speed, and disciplined execution at every level. The Executive Assistant to the CMO serves as a force multiplier within a global marketing organization of 160 colleagues. This is not a traditional administrative role. It is a strategic executive partnership role designed to ensure the CMO's time, attention, preparation, and energy are aligned to the highest impact priorities for the business. This role reports directly to the Chief of Staff to the CMO and works in close partnership with her. Together, they operate as a coordinated executive team. The Chief of Staff focuses on strategic alignment, cross functional initiatives, and executive priorities. The Executive Assistant focuses on ensuring adherence to operational cadences, preparation, precision, and executive readiness. This position is designed for a career Executive Assistant who is committed to the executive support profession. It is not a pathway role into marketing. Success in this role requires mastery of executive leverage, anticipation, and operational excellence. Success means the CMO is always prepared, never surprised, and consistently focused on the highest value outcomes. It means the marketing organization functions with predictable cadences, efficient use of travel and mee", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:71d303448fcdc1e0e00c3479d83c61b5:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.65a07c857e4886cf20", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Employer: \"systems\"", "tooltip": "Employer matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "Bentley Systems", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:71d303448fcdc1e0e00c3479d83c61b5:employer:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3147bbd60b59ee630b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Executive Assistant to the Chief Marketing Officer Job Location - Country United States Bentley's marketing organization is undergoing a transformation to become an AI native, globally scaled function driving global adoption of our broad, industry leading product portfolio. This transformation requires clarity, precision, speed, and disciplined execution at every level. The Executive Assistant to the CMO serves as a force multiplier within a global marketing organization of 160 colleagues. This is not a traditional administrative role. It is a strategic executive partnership role designed to ensure the CMO's time, attention, preparation, and energy are aligned to the highest impact priorities for the business. This role reports directly to the Chief of Staff to the CMO and works in close partnership with her. Together, they operate as a coordinated executive team. The Chief of Staff focuses on strategic alignment, cross functional initiatives, and executive priorities. The Executive Assistant focuses on ensuring adherence to operational cadences, preparation, precision, and executive readiness. This position is designed for a career Executive Assistant who is committed to the executive support profession. It is not a pathway role into marketing. Success in this role requires mastery of executive leverage, anticipation, and operational excellence. Success means the CMO is always prepared, never surprised, and consistently focused on the highest value outcomes. It means the marketing organization functions with predictable cadences, efficient use of travel and mee", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.665dae9cf87aa84db9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Executive Assistant to the Chief Marketing Officer Job Location - Country United States Bentley's marketing organization is undergoing a transformation to become an AI native, globally scaled function driving global adoption of our broad, industry leading product portfolio. This transformation requires clarity, precision, speed, and disciplined execution at every level. The Executive Assistant to the CMO serves as a force multiplier within a global marketing organization of 160 colleagues. This is not a traditional administrative role. It is a strategic executive partnership role designed to ensure the CMO's time, attention, preparation, and energy are aligned to the highest impact priorities for the business. This role reports directly to the Chief of Staff to the CMO and works in close partnership with her. Together, they operate as a coordinated executive team. The Chief of Staff focuses on strategic alignment, cross functional initiatives, and executive priorities. The Executive Assistant focuses on ensuring adherence to operational cadences, preparation, precision, and executive readiness. This position is designed for a career Executive Assistant who is committed to the executive support profession. It is not a pathway role into marketing. Success in this role requires mastery of executive leverage, anticipation, and operational excellence. Success means the CMO is always prepared, never surprised, and consistently focused on the highest value outcomes. It means the marketing organization functions with predictable cadences, efficient use of travel and mee", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.9e0c6ba87a8fb344eb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "71d303448fcdc1e0e00c3479d83c61b5", "signal_type": "query_match", "display_text": "Employer: \"systems\"", "tooltip": "Employer contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Bentley Systems", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.bentley.com/job/Remote-Executive-Assistant-to-the-Chief-Marketing-Officer-CO/1372804100/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1031308/000103130826000007/bsy-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1031308/000103130826000007/bsy-20251231.htm" ], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.bentley.com/job/Remote-Executive-Assistant-to-the-Chief-Marketing-Officer-CO/1372804100/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.bentley.com/job/Remote-Executive-Assistant-to-the-Chief-Marketing-Officer-CO/1372804100/", "source_values": [ "rule" ], "checked_at": null } } }, { "id": "78bdd5261dc30ee66aad6da68fe239a9", "title": "Senior Director, Customer & Partner Operations", "employer_name": "MongoDB, Inc.", "employer_slug": "mongodb", "location_text": "San Francisco", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 132000, "salary_max": 259000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 132000, "base_salary_max": 259000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-19T17:17:37.000Z", "apply_url": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "parental_leave_weeks": 20, "non_birth_parent_leave_weeks": 20, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "parental_leave_weeks" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "director_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 12, "years_experience_max": null, "role_function": "operations", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "1001-5000", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8ea6914e8b306cf36a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:78bdd5261dc30ee66aad6da68fe239a9:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a5b75da65f83ad53c5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:78bdd5261dc30ee66aad6da68fe239a9:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.cb013f516754caffd5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:78bdd5261dc30ee66aad6da68fe239a9:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.9daa359006960232fd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "MongoDB, Inc.", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:78bdd5261dc30ee66aad6da68fe239a9:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3aaf828bbd443b6b70", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b466f4ef6cd294a252", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Director, Customer & Partner Operations San Francisco MongoDB is seeking a Senior Director of Customer & Partner Operations to serve as the operational backbone of our Customer organization. This leader will drive the systems, insights, processes, and rhythm-of-business that enable MongoDB's customer success, professional services, support, and partner functions to operate at scale and with precision. This is a high-visibility, cross-functional role at the intersection of data, process, and execution. This leader will: - Act as the Senior Director of Customers & Partner operations to the Chief Customer Officer (CCO), owning the planning, analytics, and operational cadence for the org - Play a critical role in evolving how we measure & track our Customer and Partner GTM model to drive higher retention, increased revenue realization, and more efficient use of our technical ecosystem - Lead a high‑impact CCO Strategy & Operations team, staying close to the work and building models to shape the business reviews that guide executive decisions We're looking to speak with candidates based in the San Francisco Bay Area for our hybrid working model. Key responsibilities Business Rhythm & Operational Cadence - Own the operating cadence for the Customer organization - QBRs, pipeline reviews, forecast calls, and board-level reporting - Drive annual planning, headcount modeling, and budget management across the customer organization - Serve as a key operational partner to the CCO, ensuring leadership has the information and structure needed to make high-quality decisions quickly Insights & Analytics - Build and maintain the reporting infrastructure that", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.64db87dbc3c16ad09e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "78bdd5261dc30ee66aad6da68fe239a9", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "MongoDB, Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7939522", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "3884b7fcc85ccb85c0366921667c76e7", "title": "GPU Top RTL Designer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-14T17:55:36.386Z", "apply_url": "https://jobs.apple.com/en-us/details/200657717/gpu-top-rtl-designer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "GPU Top RTL Designer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! At Apple, we push our designs to the limit in order to make amazing products. We want to delight our customers with hardware that performs great while delivering long battery life. As part of the mobile GPU design team, you will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications for GPU power management and SOC interface logic. In addition, you will be responsible for integrating applicable IP from other teams to enable complete security, debug, and power management solutions! - Deliver high quality design collateral, including RTL, to Physical Design teams - Create micro architecture specifications - Specify clock, power, and interface descriptions to ensure optimized design - Assess and integrate IP from other Apple teams - Close timing, power, area, and lint for design by optimizing RTL and constraints - Drive performance, power, area, and functional goals - Provide", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2a11041b3f87e2e695", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3884b7fcc85ccb85c0366921667c76e7", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "GPU Top RTL Designer Austin, United States of America Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient processor, system-on-chip (SoC). You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be responsible for crafting and building the technology that fuels Apple's devices. Together, you and your team will enable our customers to do all the things they love with their devices! At Apple, we push our designs to the limit in order to make amazing products. We want to delight our customers with hardware that performs great while delivering long battery life. As part of the mobile GPU design team, you will collaborate with Platform Architecture, Software, Design Verification, and Physical Design teams to deliver RTL and specifications for GPU power management and SOC interface logic. In addition, you will be responsible for integrating applicable IP from other teams to enable complete security, debug, and power management solutions! - Deliver high quality design collateral, including RTL, to Physical Design teams - Create micro architecture specifications - Specify clock, power, and interface descriptions to ensure optimized design - Assess and integrate IP from other Apple teams - Close timing, power, area, and lint for design by optimizing RTL and constraints - Drive performance, power, area, and functional goals - Provide", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.d6cd1fb8c64bce1d32", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3884b7fcc85ccb85c0366921667c76e7", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "GPU Top RTL Designer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.43b73050478e28db26", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3884b7fcc85ccb85c0366921667c76e7", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3884b7fcc85ccb85c0366921667c76e7:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657717/gpu-top-rtl-designer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657717/gpu-top-rtl-designer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200657717/gpu-top-rtl-designer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "2381d96ab5a63519067dc70ed02c7fd5", "title": "Senior Analog Mixed-Signal CAD Engineer", "employer_name": "Astera Labs", "employer_slug": "astera-labs", "location_text": "Vietnam", "country": "VN", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-01-27T22:24:40.000Z", "apply_url": "https://job-boards.greenhouse.io/asteralabs/jobs/4654351005", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1736297/000173629726000010/alab-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1736297/000173629726000010/alab-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0334a3110694802efb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2381d96ab5a63519067dc70ed02c7fd5:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.63fa53aea18232cff3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2381d96ab5a63519067dc70ed02c7fd5:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fa52c4894ccb834383", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2381d96ab5a63519067dc70ed02c7fd5:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.132c6895bf6fa0167c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.33edeb1c377693db9b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.be0d77fd6828caa0a5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2381d96ab5a63519067dc70ed02c7fd5", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Mixed-Signal CAD Engineer Vietnam Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs' Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company's COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company's custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com . Job Summary: We are seeking a highly motivated and detail-oriented Analog Mixed-Signal CAD Engineer to join our design automation team. In this role, you will develop, maintain, and support CAD tools and design flows for analog and mixed-signal IC design. You will work closely with circuit designers, layout engineers, and EDA vendors to ensure efficient and robust design environments. Key Responsibilities: - Develop and maintain analog/mixed-signal design flows using industry-standard EDA tools (Cadence Virtuoso, Spectre, etc.). - Automate design tasks using scripting languages (e.g., Python, SKILL, Tcl, Perl). - Support schematic, layout, simulation, and verification environments. - Collaborate with design teams to understand requirements and improve design productivity. - Integrate and validate PDKs (Process Design Kits) and technology files. - Provide documentation, training, and support for CAD tools and flows. - Interface with EDA vendors to evaluate and deploy new tools and features. - Monitor and resolve CAD tool issues, ensuring", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1736297/000173629726000010/alab-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1736297/000173629726000010/alab-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/asteralabs/jobs/4654351005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/asteralabs/jobs/4654351005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/asteralabs/jobs/4654351005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "991af5db2ccb724217120cf229a185b0", "title": "Senior Photonics PDK Design Automation Engineer", "employer_name": "Lightmatter", "employer_slug": "lightmatter", "location_text": "Boston, MA; Mountain View, CA; Toronto, ON", "country": "unknown", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": 165000, "salary_max": 200000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 165000, "base_salary_max": 200000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-06-09T13:38:25.000Z", "apply_url": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Photonics PDK Design Automation Engineer Boston, MA; Mountain View, CA; Toronto, ON Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! We are hiring a Photonics PDK Design Automation Engineer to join our team. In this role, you will develop our internal Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between photonics device design and system-level verification. You will develop robust flow ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, EDA tools, applying software engineering rigor to the challenges of photonic hardware design. Responsibilities - Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models. - Develop and maintain custom photonic Layout vs Schematic", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "series_d", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.49322a0e9f48008c90", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "991af5db2ccb724217120cf229a185b0", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Photonics PDK Design Automation Engineer Boston, MA; Mountain View, CA; Toronto, ON Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! We are hiring a Photonics PDK Design Automation Engineer to join our team. In this role, you will develop our internal Process Design Kit (PDK). You will act as the architect of our component library, bridging the gap between photonics device design and system-level verification. You will develop robust flow ensuring that our simulation environment accurately predicts the behavior of our physical layouts. You will work heavily in Python, EDA tools, applying software engineering rigor to the challenges of photonic hardware design. Responsibilities - Develop and maintain a library of pcells using Python-based layout frameworks. Ensure strict synchronization between physical layout, logical netlists, and behavioral models. - Develop and maintain custom photonic Layout vs Schematic", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:991af5db2ccb724217120cf229a185b0:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.aade4625c723434526", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "991af5db2ccb724217120cf229a185b0", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Senior Photonics PDK Design Automation Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:991af5db2ccb724217120cf229a185b0:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c9deede115c8a73efd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "991af5db2ccb724217120cf229a185b0", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Photonics PDK Design Automation Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5249470008?gh_jid=5249470008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "e14c17dba55cdf850028a4a0d0b756b3", "title": "SoC QoS/Fabric Performance Engineer, Platform Architecture", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 181100, "salary_max": 272100, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 181100, "base_salary_max": 272100, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-29T18:39:55.453Z", "apply_url": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SoC QoS/Fabric Performance Engineer, Platform Architecture Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! In this role, you will be a member of the Platform Architecture team, working with hardware and software engineering groups to shape the architecture of Apple's future System-on-Chips (SoC). We are seeking an energetic and highly motivated SoC performance engineer to drive development of our on-chip communication interconnect and memory Quality-of-Service features. You will help create a full-chip C++ simulator for iPhone/iPad/Mac/Watch SoCs. You will model new, emerging workloads such as Augmented Reality (AR) and Machine Learning (ML). You will use these models to study a range of performance and power trade-offs in our SoCs. Your work will be highly visible and critical for driving architecture improvements in Apple's future products. Learning about the state of the art in SoC IP and chip-level architecture including network-on-chip C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC models Running performance simulation of future applications Careful analysis and presentation of simulation results Tuning and validating future SoC HW/SW for the best user experience Collaboration with cross-functional modeling, hardware, and software teams Some international travel is required for this position Minimum Qualifications: BS degree C++ programming experience Coursework and/or experience in computer architecture and the HW/SW stack Coursework and/or experience", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.27fb5fa53cd6776b21", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e14c17dba55cdf850028a4a0d0b756b3", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SoC QoS/Fabric Performance Engineer, Platform Architecture Austin, United States of America Imagine what you could do here! At Apple, new ideas have a way of becoming extraordinary products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish! In this role, you will be a member of the Platform Architecture team, working with hardware and software engineering groups to shape the architecture of Apple's future System-on-Chips (SoC). We are seeking an energetic and highly motivated SoC performance engineer to drive development of our on-chip communication interconnect and memory Quality-of-Service features. You will help create a full-chip C++ simulator for iPhone/iPad/Mac/Watch SoCs. You will model new, emerging workloads such as Augmented Reality (AR) and Machine Learning (ML). You will use these models to study a range of performance and power trade-offs in our SoCs. Your work will be highly visible and critical for driving architecture improvements in Apple's future products. Learning about the state of the art in SoC IP and chip-level architecture including network-on-chip C++ modeling of graphics, camera, and ML dataflow, network-on-chip and integration with other SoC models Running performance simulation of future applications Careful analysis and presentation of simulation results Tuning and validating future SoC HW/SW for the best user experience Collaboration with cross-functional modeling, hardware, and software teams Some international travel is required for this position Minimum Qualifications: BS degree C++ programming experience Coursework and/or experience in computer architecture and the HW/SW stack Coursework and/or experience", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.ef7fc9c7613681c0ad", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e14c17dba55cdf850028a4a0d0b756b3", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e14c17dba55cdf850028a4a0d0b756b3:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665859/soc-qos-fabric-performance-engineer-platform-architecture?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "7d8de16c4d3c952750ab7a9db1c95536", "title": "Senior Golang Engineer (4866)", "employer_name": "Yum! Brands", "employer_slug": "yum-brands", "location_text": "Location not specified", "country": "unknown", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-04T16:41:40.000Z", "apply_url": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "apply_url_verified": true, "ats": "custom", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1041061/000104106126000084/yum-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1041061/000104106126000084/yum-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Retail", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.023a5697225e9a524f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7d8de16c4d3c952750ab7a9db1c95536:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.985c1a63e13c7bd8a5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7d8de16c4d3c952750ab7a9db1c95536:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d5ee8b04a460e403a8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7d8de16c4d3c952750ab7a9db1c95536:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.10c6ce328a75ca09c9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.459d56c41b1de18b53", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.dbe15e6949a6c8de2c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Golang Engineer (4866) Senior Golang Engineer As a Senior Software Engineer I, you will play a key role in building and evolving the Store, Menu Serving, and Menu Management platforms. You\\u2019ll contribute directly to system architecture and implementation while helping ensure high standards of code quality, consistency, and feature delivery across the team. You will work closely with front-end engineering teams integrating with your APIs and partner with Product and Design to plan, scope, and deliver new menu management capabilities. This role balances hands-on development with technical leadership through collaboration, review, and mentorship. Design, build, and maintain scalable GraphQL services in Go. Write and maintain high-quality unit and integration tests. Improve and refactor existing systems to enhance performance, readability, and maintainability. Collaborate with Product and Engineering partners during planning and backlog grooming to shape and take ownership of technical solutions. Provide thoughtful, timely code reviews and technical guidance to peers. Participate in team ceremonies (standups, sprint planning, retrospectives) to support delivery and remove blockers. \\n Bachelor's degree in Computer Science, Information Systems, or equivalent practical experience. 3-5 years of software engineering experience. GraphQL and\\/or REST API development Golang PostgreSQL (or similar relational databases) Containerized services using Docker Experience with distributed workflow orchestration tools (e.g., Temporal, Cadence). Additional Qualifications Familiarity with Node.js and modern front-end frameworks (e.g., React, Angular, Vue) or mobile platforms (iOS, Android) Experience with AWS S3 This role can be remote in the United States Salary Range: 117,800 - 147,600 Benefits : Employees (and their eligible family", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.3b9f3eb8b7acbdf034", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7d8de16c4d3c952750ab7a9db1c95536", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1041061/000104106126000084/yum-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1041061/000104106126000084/yum-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.yum.com/jobs/engineering/smith-county-ks-usa/senior-golang-engineer/4866", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "ec7980703903401dcbf8263ec3f3021c", "title": "Mechanical Design Engineer: Robotics Hardware Engineering", "employer_name": "Meta", "employer_slug": "meta", "location_text": "Redmond, WA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 173000, "salary_max": 245000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 173000, "base_salary_max": 245000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-07T17:58:24.000Z", "apply_url": "https://www.metacareers.com/jobs/1957808705109843/", "apply_url_verified": false, "ats": "meta_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Mechanical Design Engineer: Robotics Hardware Engineering Redmond, WA At Meta, we're building the future of human connection and the technology that enables it. This means continuously inventing and developing technologies for the next generation of experiences. To continue our efforts in the path to AGI, and as we move closer to a future with intelligent robots and advanced AI models, we're hiring talent across a broad range of disciplines from robotics hardware to system software, machine perception, and artificial intelligence. These crucial projects and initiatives taken on by this team have never been done before, so you have a rare opportunity to help us create new ways people connect around the world. The Meta Robotics Hardware team is seeking a Mechanical Design Engineer. This role is pivotal in tackling mechanical design problems we face including designing and developing complex robotics that balance ergonomics, performance, reliability, and usability while maintaining the highest safety and quality standards. This role will be part of a team responsible for initial concept development, analytical modeling, prototype design, construction, and testing. Candidates should be experienced working in a high ambiguity, fast-paced environment where full system requirements are seldom known. This team is dedicated to building hardware that enables learning through data collection and testing. Responsibilities: - Design and Development: Mechanical design and analysis problems for prototype robotics structures, mechanisms, power transmissions, and systems integration while balancing ergonomics, performance, reliability, weight, and maintainability - Supporting prototype fabrication and builds: Working with internal/external partners to support part fabrication", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1326801/000162828026003942/meta-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1326801/000162828026003942/meta-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.16deb03f510884c256", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ec7980703903401dcbf8263ec3f3021c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Mechanical Design Engineer: Robotics Hardware Engineering Redmond, WA At Meta, we're building the future of human connection and the technology that enables it. This means continuously inventing and developing technologies for the next generation of experiences. To continue our efforts in the path to AGI, and as we move closer to a future with intelligent robots and advanced AI models, we're hiring talent across a broad range of disciplines from robotics hardware to system software, machine perception, and artificial intelligence. These crucial projects and initiatives taken on by this team have never been done before, so you have a rare opportunity to help us create new ways people connect around the world. The Meta Robotics Hardware team is seeking a Mechanical Design Engineer. This role is pivotal in tackling mechanical design problems we face including designing and developing complex robotics that balance ergonomics, performance, reliability, and usability while maintaining the highest safety and quality standards. This role will be part of a team responsible for initial concept development, analytical modeling, prototype design, construction, and testing. Candidates should be experienced working in a high ambiguity, fast-paced environment where full system requirements are seldom known. This team is dedicated to building hardware that enables learning through data collection and testing. Responsibilities: - Design and Development: Mechanical design and analysis problems for prototype robotics structures, mechanisms, power transmissions, and systems integration while balancing ergonomics, performance, reliability, weight, and maintainability - Supporting prototype fabrication and builds: Working with internal/external partners to support part fabrication", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.71b909534ab8575d7c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ec7980703903401dcbf8263ec3f3021c", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Mechanical Design Engineer: Robotics Hardware Engineering Redmond, WA At Meta, we're building the future of human connection and the technology that enables it. This means continuously inventing and developing technologies for the next generation of experiences. To continue our efforts in the path to AGI, and as we move closer to a future with intelligent robots and advanced AI models, we're hiring talent across a broad range of disciplines from robotics hardware to system software, machine perception, and artificial intelligence. These crucial projects and initiatives taken on by this team have never been done before, so you have a rare opportunity to help us create new ways people connect around the world. The Meta Robotics Hardware team is seeking a Mechanical Design Engineer. This role is pivotal in tackling mechanical design problems we face including designing and developing complex robotics that balance ergonomics, performance, reliability, and usability while maintaining the highest safety and quality standards. This role will be part of a team responsible for initial concept development, analytical modeling, prototype design, construction, and testing. Candidates should be experienced working in a high ambiguity, fast-paced environment where full system requirements are seldom known. This team is dedicated to building hardware that enables learning through data collection and testing. Responsibilities: - Design and Development: Mechanical design and analysis problems for prototype robotics structures, mechanisms, power transmissions, and systems integration while balancing ergonomics, performance, reliability, weight, and maintainability - Supporting prototype fabrication and builds: Working with internal/external partners to support part fabrication", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.d0f0e0dc6bae223a95", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ec7980703903401dcbf8263ec3f3021c", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Mechanical Design Engineer: Robotics Hardware Engineering", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.e3572387c55e23f4d8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ec7980703903401dcbf8263ec3f3021c", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ec7980703903401dcbf8263ec3f3021c:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1326801/000162828026003942/meta-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1326801/000162828026003942/meta-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.metacareers.com/jobs/1957808705109843/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "cd7186948e2d85a070ef8331f5dd7d68", "title": "Electronics Engineer", "employer_name": "Department of Defense", "employer_slug": "department-of-defense", "location_text": "McClellan, California", "country": "US", "employment_type": "part_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 45155, "salary_max": 107620, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 45155, "base_salary_max": 107620, "salary_disclosed": true, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-08T07:40:18.000Z", "apply_url": "https://www.usajobs.gov:443/job/872056300", "apply_url_verified": false, "ats": "usajobs", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [ "CA" ], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "hire_states_allowed": { "field": "hire_states_allowed", "source": "rule:state_eligibility", "db_column": "hire_states_allowed" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Defense", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2c8d1174d293314fa6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:cd7186948e2d85a070ef8331f5dd7d68:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7d4e4442c2af68570c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:cd7186948e2d85a070ef8331f5dd7d68:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f3b0e5c3f2890e2415", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:cd7186948e2d85a070ef8331f5dd7d68:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fd01cdd07e8a75850b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:cd7186948e2d85a070ef8331f5dd7d68:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1346de7f980e3ef2f6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.afa7f8a95611351acb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d3b544615ca0833477", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "cd7186948e2d85a070ef8331f5dd7d68", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electronics Engineer McClellan, California Summary This position is part of the Defense Microelectronics Activity, Defense Microelectronics Activity. The incumbent serves as a Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Duties This position is being filled under the memorandum from the Under Secretary of Defense for Personnel and Readiness (USD(P&R)) \"Expansion of Direct Hire Authority for Certain Personnel of the Department of Defense,\" dated October 15, 2021. As an Electronics Engineer at the NH-0855-2 some of your typical work assignments may include: Serves as Device Engineer as a key member in the Modeling and Simulation team in support of the DMEA Foundry team. Responsible for the design and optimization of TCAD device simulations to accurately represent next generation SiC and/or Si power device behavior and performance. Responsible for executing device testing and characterization to ensure device operation. Performs measurements with semiconductor device parameter analyzers and semi-automated wafer probe systems, LCR meters, oscilloscopes, etc. Measures semiconductor devices at wafer-level or package-level to verify electrical behavior and extract key performance parameters. Assists the lead Process Control Monitoring (PCM) engineer to verify PCM test structure electrical behavior. Assists in the design of PCM test structures to validate process/device performance and monitor process stability using Cadence Virtuoso for design/layout activities. Identifies device requirements and key system performance parameters to analyze results from electrical/reliability testing and provides feedback to the Foundry team. Education You MUST provide transcripts or other documentation to support your educational", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "hire_states_allowed": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "rule:state_eligibility" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.usajobs.gov:443/job/872056300", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "b8990488ddb55fe225be596102addc44", "title": "Instrument Systems Design Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Diego, United States of America", "country": "US", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 134800, "salary_max": 245800, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 134800, "base_salary_max": 245800, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-09T00:28:28.174Z", "apply_url": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Instrument Systems Design Engineer San Diego, United States of America Apple designs consumer electronics that have touched millions and changed the way people interact with electronic devices around the world. The Product Integrity Group plays a key role in keeping up the standards. Through work with the team you will have the unique opportunity to impact products all across Apple, because here new ideas have a way of becoming great products, services, and customer experiences very quickly. We are looking for an engineer to design, develop and deploy calibration and test instrumentation systems for Apple's world class products. This engineer will work closely with cross-functional groups (Design, ME, EE, SW, Ops, etc.) throughout the New Product Introduction (NPI) phase to ensure the success of current and future Apple products. You will be responsible for the design specification, bring up, validation and deployment of automated instrumentation to calibrate and test Apple's products through NPI and mass production. Architect instrumentation systems (including HW specification) and maintain those systems through production. Work with our mechanical engineering team to specify and validate the required mechanical fixtures & automation systems. Develop, debug, and optimize automation software. Implement advanced signal processing and ML algorithms to evaluate performance of systems. Analyze large amounts of data generated from your instrument systems and adopt data-driven approaches to solving engineering challenges. Perform failure mode root cause analysis and resolution, debugging from the system level down to the component level. Work closely with Apple Acoustics/N&V, system EE, product design, firmware, operations,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 2, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 10, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.cabff06c4e5ac73875", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b8990488ddb55fe225be596102addc44", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Instrument Systems Design Engineer San Diego, United States of America Apple designs consumer electronics that have touched millions and changed the way people interact with electronic devices around the world. The Product Integrity Group plays a key role in keeping up the standards. Through work with the team you will have the unique opportunity to impact products all across Apple, because here new ideas have a way of becoming great products, services, and customer experiences very quickly. We are looking for an engineer to design, develop and deploy calibration and test instrumentation systems for Apple's world class products. This engineer will work closely with cross-functional groups (Design, ME, EE, SW, Ops, etc.) throughout the New Product Introduction (NPI) phase to ensure the success of current and future Apple products. You will be responsible for the design specification, bring up, validation and deployment of automated instrumentation to calibrate and test Apple's products through NPI and mass production. Architect instrumentation systems (including HW specification) and maintain those systems through production. Work with our mechanical engineering team to specify and validate the required mechanical fixtures & automation systems. Develop, debug, and optimize automation software. Implement advanced signal processing and ML algorithms to evaluate performance of systems. Analyze large amounts of data generated from your instrument systems and adopt data-driven approaches to solving engineering challenges. Perform failure mode root cause analysis and resolution, debugging from the system level down to the component level. Work closely with Apple Acoustics/N&V, system EE, product design, firmware, operations,", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.94f93e64d9582ece60", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b8990488ddb55fe225be596102addc44", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Instrument Systems Design Engineer", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.e2562368d477b8f595", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b8990488ddb55fe225be596102addc44", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Instrument Systems Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.e311b34699113487e5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b8990488ddb55fe225be596102addc44", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b8990488ddb55fe225be596102addc44:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200667269/instrument-systems-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c24709a748633087351902129c2423c2", "title": "Senior Electrical Engineer, Amazon Industrial Robotics", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "North Reading, Massachusetts, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 137300, "salary_max": 185700, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 137300, "base_salary_max": 185700, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-11-18T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.79bbc46ad6e35bd8f0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c24709a748633087351902129c2423c2:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9011e13983e22c92bb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c24709a748633087351902129c2423c2:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f8a525dd6e2cbe0707", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c24709a748633087351902129c2423c2:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.525aed3fb8ff0ffff0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9d3b1ee5fce3cb3f30", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.eae5c5d3ec4b53f2e5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c24709a748633087351902129c2423c2", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Industrial Robotics North Reading, Massachusetts, USA Amazon Industrial Robotics is seeking exceptional talent to help develop the next generation of advanced robotics systems that will transform automation at Amazon's scale. We're building revolutionary robotic systems that combine cutting-edge AI, sophisticated control systems, and advanced mechanical design to create adaptable automation solutions capable of working safely alongside humans in dynamic environments. This is a unique opportunity to shape the future of robotics and automation at an unprecedented scale, working with world-class teams pushing the boundaries of what's possible in robotic manipulation, locomotion, and human-robot interaction. Amazon is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation and release to manufacturing. The ideal candidate will have extensive experience in system design, complex analog and digital circuit design, power electronics, possess good communication skills, own a large component of a system, and lead a team of Electrical Engineers. This candidate must have the ability to work well both independently and in a team setting. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel - Coordinate all activities within the engineering discipline for the project. - Ensure coordination with other disciplines is effective for each project. - Thorough understanding of technical principles and concepts in Electrical Engineering - Writing and developing functional specifications, design verification plans and test", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3128218/senior-electrical-engineer-amazon-industrial-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "6652916bfca99a61ba43e3467014a90e", "title": "Strategy & Operations Lead", "employer_name": "Forter", "employer_slug": "forter", "location_text": "United States - New York", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 168000, "salary_max": 200000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 168000, "base_salary_max": 200000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-03-27T01:54:09.000Z", "apply_url": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "equity_type": { "field": "equity_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_type" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 2, "years_experience_max": 6, "role_function": "operations", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8c96404cac87edb93f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6652916bfca99a61ba43e3467014a90e:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c7aa60470f8197fbf7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6652916bfca99a61ba43e3467014a90e:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.cb7f37bd3337b1f3f5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6652916bfca99a61ba43e3467014a90e:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f051e0ce9f94eef98b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:6652916bfca99a61ba43e3467014a90e:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7de58a3de1f5aa35a7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.90cd5df9bb82198f36", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.95b670d3a1bc35f319", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "6652916bfca99a61ba43e3467014a90e", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Strategy & Operations Lead United States - New York About the role: Reporting to Forter's Chief of Staff, the Strategy & Operations Lead will serve as a force-multiplier for the Chief of Staff function - driving execution of high-priority cross-functional initiatives, maintaining the operational cadences that keep the leadership team aligned, and supporting the preparation of key moments such as board meetings and quarterly offsites. This is a high-visibility, high-impact role designed for someone who combines sharp analytical thinking with strong execution discipline. You'll work across the entire business, partner directly with senior leaders, and build the operational muscle to grow into roles of increasing strategic scope over time. What you'll be doing: Cross-Functional Project Management - Drive strategic projects: Support end-to-end execution of high-priority, ad hoc strategic projects on behalf of the Chief of Staff and President, managing scope, timelines, and stakeholder coordination from kickoff through completion. - Build execution infrastructure: Develop and maintain structured tracking systems (e.g., project plans, dashboards, status trackers) to provide the Chief of Staff and leadership team with clear visibility into initiative progress and blockers. - Coordinate across the business: Work across Sales, Product, Finance, Marketing, and other functions to surface dependencies, align on priorities, and unblock execution, serving as a connective layer between teams. - Identify and escalate blockers: Quickly diagnose obstacles slowing down key workstreams and surface proposed solutions to the Chief of Staff, with a bias toward action. Management Rhythm & Operating Cadence - Support leadership cadences: Support the Chief of", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/forter/jobs/8480473002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "db83c58d918450908df9a1a9285df234", "title": "Electrical Engineer, Hardware Systems", "employer_name": "Etched", "employer_slug": "etched", "location_text": "San Jose, CA, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 150000, "salary_max": 275000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 150000, "base_salary_max": 275000, "salary_disclosed": true, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-03-17T21:03:12.427Z", "apply_url": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Electrical Engineer, Hardware Systems San Jose, CA, United States About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. Etched is looking for exceptional hardware system engineers to join our team. The candidate will be responsible for schematic design for our accelerator module, and will help us pave the way for manufacturing scale. Key Responsibilities - Lead schematic design of the mezzanine card and base board for Etched's accelerator systems - Work with Signal Integrity, PCB, and Mechanical Engineering to solve system level design problems - Collaborate with ODMs/OEMs on system requirements, including bringup and validation plans - Understand datacenter customer requirements and ensure our servers meet them - Bring up of system base board and mezzanine card - Create and manage PCBA documentation including BOMs and special assembly processes - Define test plans and test equipment for bring-up and manufacturing You may be a good fit if you have (Must-have qualifications) - 5-10 years of experience in complex server/switch system design and development - Extensive experience on 100G Ethernet, PCIe Gen5, I2C, SPI, UART interfaces - Familiar with modern AI/datacenter system architecture - Proven track record of designing systems alongside silicon - Deep understanding of datacenter needs, especially with respect to", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 14, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ab53e47810beacd1dd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "db83c58d918450908df9a1a9285df234", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Hardware Systems San Jose, CA, United States About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. Etched is looking for exceptional hardware system engineers to join our team. The candidate will be responsible for schematic design for our accelerator module, and will help us pave the way for manufacturing scale. Key Responsibilities - Lead schematic design of the mezzanine card and base board for Etched's accelerator systems - Work with Signal Integrity, PCB, and Mechanical Engineering to solve system level design problems - Collaborate with ODMs/OEMs on system requirements, including bringup and validation plans - Understand datacenter customer requirements and ensure our servers meet them - Bring up of system base board and mezzanine card - Create and manage PCBA documentation including BOMs and special assembly processes - Define test plans and test equipment for bring-up and manufacturing You may be a good fit if you have (Must-have qualifications) - 5-10 years of experience in complex server/switch system design and development - Extensive experience on 100G Ethernet, PCIe Gen5, I2C, SPI, UART interfaces - Familiar with modern AI/datacenter system architecture - Proven track record of designing systems alongside silicon - Deep understanding of datacenter needs, especially with respect to", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bf33fe92f39df3e66c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "db83c58d918450908df9a1a9285df234", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Hardware Systems San Jose, CA, United States About Etched Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep chain-of-thought reasoning. Etched is looking for exceptional hardware system engineers to join our team. The candidate will be responsible for schematic design for our accelerator module, and will help us pave the way for manufacturing scale. Key Responsibilities - Lead schematic design of the mezzanine card and base board for Etched's accelerator systems - Work with Signal Integrity, PCB, and Mechanical Engineering to solve system level design problems - Collaborate with ODMs/OEMs on system requirements, including bringup and validation plans - Understand datacenter customer requirements and ensure our servers meet them - Bring up of system base board and mezzanine card - Create and manage PCBA documentation including BOMs and special assembly processes - Define test plans and test equipment for bring-up and manufacturing You may be a good fit if you have (Must-have qualifications) - 5-10 years of experience in complex server/switch system design and development - Extensive experience on 100G Ethernet, PCIe Gen5, I2C, SPI, UART interfaces - Familiar with modern AI/datacenter system architecture - Proven track record of designing systems alongside silicon - Deep understanding of datacenter needs, especially with respect to", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.f2aa0e6ee6abd47070", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "db83c58d918450908df9a1a9285df234", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Electrical Engineer, Hardware Systems", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.d8642465a2c8d36b97", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "db83c58d918450908df9a1a9285df234", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:db83c58d918450908df9a1a9285df234:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/etched/61860739-5aa9-4f64-920d-f4c1cca71af8", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "11e11377008b3cd6233af7b07ce3e454", "title": "Design Engineer 1", "employer_name": "Garmin", "employer_slug": "garmin", "location_text": "Cary, North Carolina", "country": "US", "employment_type": "internship", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-05T21:57:00.000Z", "apply_url": "https://careers-garmin.icims.com/jobs/18605/login", "apply_url_verified": true, "ats": "jibe_icims", "url_last_checked_alive": "2026-07-14T12:18:10.205Z", "removed_at": null, "description_excerpt": "Design Engineer 1 Cary, North Carolina Overview We are seeking a full-time Design Engineer 1 at our Cary, NC location. In this role, you will be responsible for designing and developing basic analog, digital and/or RF circuits, equipment, and/or systems. Essential Functions Perform basic schematic design and PCB layout Complete basic troubleshooting and debugging of electronic circuits and/or systems Design test boards and circuit modifications to test design improvements Test circuits designed by other engineers and document the test results Identify and resolve defects of basic scope using proper engineering tools and techniques Apply design standards and procedures using appropriate engineering tools to document and implement basic designs in an organized manner Basic Qualifications Bachelor's Degree in Electrical Engineering or Computer Engineering OR an equivalent combination of education and experience Excellent academics (cumulative GPA greater than or equal to 3.0 as a general rule) Must demonstrate the capability to apply design standards and procedures to develop basic analog, digital and/or RF designs/circuits including simulations, schematics, PCB layouts and evaluation Must demonstrate the ability to learn how to use and apply engineering tools specific to electrical engineering (e.g. multimeters, oscilloscopes, network analyzers, spectrum analyzers, schematic design and PCB layout programs, etc.) Must demonstrate the capability to perform basic troubleshooting & debugging Desired Qualifications Outstanding academics (cumulative GPA greater than or equal to 3.5) Previous work or internship experience with circuit design for consumer or aviation products Garmin International is an equal opportunity employer. Qualified applicants will receive consideration for employment without", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1121788/000119312526056028/grmn-20251227.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1121788/000119312526056028/grmn-20251227.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Retail", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7fdd6064a4b9cec1b5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "11e11377008b3cd6233af7b07ce3e454", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Design Engineer 1 Cary, North Carolina Overview We are seeking a full-time Design Engineer 1 at our Cary, NC location. In this role, you will be responsible for designing and developing basic analog, digital and/or RF circuits, equipment, and/or systems. Essential Functions Perform basic schematic design and PCB layout Complete basic troubleshooting and debugging of electronic circuits and/or systems Design test boards and circuit modifications to test design improvements Test circuits designed by other engineers and document the test results Identify and resolve defects of basic scope using proper engineering tools and techniques Apply design standards and procedures using appropriate engineering tools to document and implement basic designs in an organized manner Basic Qualifications Bachelor's Degree in Electrical Engineering or Computer Engineering OR an equivalent combination of education and experience Excellent academics (cumulative GPA greater than or equal to 3.0 as a general rule) Must demonstrate the capability to apply design standards and procedures to develop basic analog, digital and/or RF designs/circuits including simulations, schematics, PCB layouts and evaluation Must demonstrate the ability to learn how to use and apply engineering tools specific to electrical engineering (e.g. multimeters, oscilloscopes, network analyzers, spectrum analyzers, schematic design and PCB layout programs, etc.) Must demonstrate the capability to perform basic troubleshooting & debugging Desired Qualifications Outstanding academics (cumulative GPA greater than or equal to 3.5) Previous work or internship experience with circuit design for consumer or aviation products Garmin International is an equal opportunity employer. Qualified applicants will receive consideration for employment without", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.eaf5e578cb84ed9ffc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "11e11377008b3cd6233af7b07ce3e454", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Design Engineer 1 Cary, North Carolina Overview We are seeking a full-time Design Engineer 1 at our Cary, NC location. In this role, you will be responsible for designing and developing basic analog, digital and/or RF circuits, equipment, and/or systems. Essential Functions Perform basic schematic design and PCB layout Complete basic troubleshooting and debugging of electronic circuits and/or systems Design test boards and circuit modifications to test design improvements Test circuits designed by other engineers and document the test results Identify and resolve defects of basic scope using proper engineering tools and techniques Apply design standards and procedures using appropriate engineering tools to document and implement basic designs in an organized manner Basic Qualifications Bachelor's Degree in Electrical Engineering or Computer Engineering OR an equivalent combination of education and experience Excellent academics (cumulative GPA greater than or equal to 3.0 as a general rule) Must demonstrate the capability to apply design standards and procedures to develop basic analog, digital and/or RF designs/circuits including simulations, schematics, PCB layouts and evaluation Must demonstrate the ability to learn how to use and apply engineering tools specific to electrical engineering (e.g. multimeters, oscilloscopes, network analyzers, spectrum analyzers, schematic design and PCB layout programs, etc.) Must demonstrate the capability to perform basic troubleshooting & debugging Desired Qualifications Outstanding academics (cumulative GPA greater than or equal to 3.5) Previous work or internship experience with circuit design for consumer or aviation products Garmin International is an equal opportunity employer. Qualified applicants will receive consideration for employment without", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.28ea9c8680d9a70fde", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "11e11377008b3cd6233af7b07ce3e454", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design Engineer 1", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.80ef5db09ba3d5208c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "11e11377008b3cd6233af7b07ce3e454", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "data", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:11e11377008b3cd6233af7b07ce3e454:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.069fc175b3fec2a857", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "11e11377008b3cd6233af7b07ce3e454", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://careers-garmin.icims.com/jobs/18605/login", "source_label": "Apply link", "source_date": "2026-07-14T12:18:10.205Z" } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": "2026-07-14T12:18:10.205Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-07-14T12:18:10.205Z", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-garmin.icims.com/jobs/18605/login", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1121788/000119312526056028/grmn-20251227.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1121788/000119312526056028/grmn-20251227.htm" ], "checked_at": null }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-garmin.icims.com/jobs/18605/login", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers-garmin.icims.com/jobs/18605/login", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "2eba1d8e0f098555621d2111c6498814", "title": "Mechanical Designer, Automation & Controls (Starship Launch Pad)", "employer_name": "SpaceX", "employer_slug": "spacex", "location_text": "Starbase, TX", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn", "a16z", "sequoia", "foundersfund" ], "posted_at": "2025-12-26T20:04:44.000Z", "apply_url": "https://boards.greenhouse.io/spacex/jobs/8352050002?gh_jid=8352050002", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "weekend_work": { "field": "weekend_work", "source": "llm:greenfield:inv_371_postfix", "db_column": "weekend_work" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "us_citizenship_required": { "field": "us_citizenship_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "us_citizenship_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 2, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": true, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8f0988b2bec6392c06", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2eba1d8e0f098555621d2111c6498814:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d78797159b47b0e386", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2eba1d8e0f098555621d2111c6498814:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fe8316149f811fd63c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2eba1d8e0f098555621d2111c6498814:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.35855abb162710cb3e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2eba1d8e0f098555621d2111c6498814:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1b7dec6bd754e968b8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bf28396a7ef0fc11cb", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad) Starbase, TX SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. MECHANICAL DESIGNER, AUTOMATION & CONTROLS (STARSHIP LAUNCH PAD) The Starship Tower & Launch Mount team is looking for controls designers to help make the next generation of launch pads a reality. This role will be focused on bridging the gap between system architecture and build - that is, developing electrical schematics, sizing conveyances, interfacing with fluids and mechanical components, detailed design of conduits and bracketry, and design of control panels. These systems will be involved in interfacing with the next generation of Starship vehicles, catching both stages, and reaching a rapid and automated flight cadence requiring no manual actions between launches. RESPONSIBILITES: - Detail electrical schematics in collaboration with automation & controls engineers who architect the systems - Perform conduit fill calculations and initial sizing of conveyances - Create CAD models and drawings of conduits, control panels, bracketry, and related access provisions - Perform basic structural analysis and use best practices to ensure designs are sufficiently robust for the challenging environment of the launch pad - Translate designs into planning as the basis for install in the field - Documentation of designs as well as best practices BASIC QUALIFICATIONS: - Bachelor's degree in", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.8ed824d41f6d41a903", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2eba1d8e0f098555621d2111c6498814", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Mechanical Designer, Automation & Controls (Starship Launch Pad)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8352050002?gh_jid=8352050002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8352050002?gh_jid=8352050002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8352050002?gh_jid=8352050002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c322b1e39fe2746e13cd5105556fa2e6", "title": "Sr. Solutions Architect-Customer Systems", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-01T00:22:28.959Z", "apply_url": "https://jobs.apple.com/en-us/details/200663311/sr-solutions-architect-customer-systems?team=SFTWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sr. Solutions Architect-Customer Systems Austin, United States of America Do you have a passion for creating experiences that help people solve technology problems? At Apple, we're here to help our customers when they need support, and by joining our team, you'll help us evolve and expand the experiences we offer through our digital apps. We build carefully crafted apps and services which serve a critical need for our customers. The Digital team builds systems that power the cloud-based support apps and tools for Apple products used by millions of our world-wide customers everyday. As a Solutions Architect on this team, you will own system design across a highly distributed, customer-facing platform where availability, latency, and data privacy are key considerations. You will define architecture across cross-functional teams, drive alignment on technical strategy, and ensure that what we build is designed to scale globally, operate reliably under peak load, and delight customers at every touchpoint. We are looking for a highly motivated individual with strong technical skills to solve complex problems, who is passionate about quality, and has a keen eye for the details that surprise and delight our customers. You will champion your ideas with peers, management and other engineering groups. You will also enjoy the benefits of working in a fast growing business where you are encouraged to \"Think Different\" and where your efforts play a key role in the success of Apple's business. Our applications rely on a complex ecosystem supported by multiple engineering teams. You will be", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 7, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fa65e3b60309175e79", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c322b1e39fe2746e13cd5105556fa2e6", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. Solutions Architect-Customer Systems Austin, United States of America Do you have a passion for creating experiences that help people solve technology problems? At Apple, we're here to help our customers when they need support, and by joining our team, you'll help us evolve and expand the experiences we offer through our digital apps. We build carefully crafted apps and services which serve a critical need for our customers. The Digital team builds systems that power the cloud-based support apps and tools for Apple products used by millions of our world-wide customers everyday. As a Solutions Architect on this team, you will own system design across a highly distributed, customer-facing platform where availability, latency, and data privacy are key considerations. You will define architecture across cross-functional teams, drive alignment on technical strategy, and ensure that what we build is designed to scale globally, operate reliably under peak load, and delight customers at every touchpoint. We are looking for a highly motivated individual with strong technical skills to solve complex problems, who is passionate about quality, and has a keen eye for the details that surprise and delight our customers. You will champion your ideas with peers, management and other engineering groups. You will also enjoy the benefits of working in a fast growing business where you are encouraged to \"Think Different\" and where your efforts play a key role in the success of Apple's business. Our applications rely on a complex ecosystem supported by multiple engineering teams. You will be", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.85f86b5e01740a8f86", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c322b1e39fe2746e13cd5105556fa2e6", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Sr. Solutions Architect-Customer Systems", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.f47183572bef87733e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c322b1e39fe2746e13cd5105556fa2e6", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c322b1e39fe2746e13cd5105556fa2e6:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200663311/sr-solutions-architect-customer-systems?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200663311/sr-solutions-architect-customer-systems?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200663311/sr-solutions-architect-customer-systems?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "fc843570a00b1063d9f54eceadd6fd93", "title": "Analog Layout Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 154600, "salary_max": 274900, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 154600, "base_salary_max": 274900, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-02T20:54:32.022Z", "apply_url": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4a3c12600ca5f7fc67", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:fc843570a00b1063d9f54eceadd6fd93:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.815ad27132852768ae", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:fc843570a00b1063d9f54eceadd6fd93:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c95ecdffd45def40ad", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:fc843570a00b1063d9f54eceadd6fd93:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5245e228bd6aa930e6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.64bfa8e108a10c709b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d24ab91b98c90ca67d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "fc843570a00b1063d9f54eceadd6fd93", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Engineer Austin, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking highly skilled Analog Layout engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors. As an Analog Layout engineer, you'll play a crucial role in translating design concepts into silicon, collaborating closely with circuit designers, and leveraging advanced tools. Your work will involve creating custom analog designs to optimize the performance of Apple's world-class products. In this dynamic and innovative environment, you'll have endless learning opportunities while collaborating across dedicated multidisciplinary teams. This job is right for you if you are a self-motivated engineer passionate about working with cutting-edge technology. You want to accelerate career growth, thrive in a results-oriented environment, and contribute to the development of revolutionary Apple products. The roles include crafting upcoming products, challenging oneself, and broadening skillsets in a dynamic, innovative work culture! Analog Layout engineers are pivotal in delivering Analog Mixed-Signal IP in a SOC flow. You will collaborate with teams of highly skilled individuals to develop the next generation of world-leading SOCs. Your responsibilities include crafting sophisticated layouts for mixed-signal and analog circuits, reviewing floorplans, and analyzing intricate circuits with circuit designers. You'll run complete sets of design verification tools, plan/schedule work, and coordinate vital layout tradeoffs. Interpretation of LVS, DRC, and ERC", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200665253/analog-layout-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "title": "Hardware Development Engineer, Hardware Development, Amazon LEO", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Redmond, Washington, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 96600, "salary_max": 160000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 96600, "base_salary_max": 160000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-09-17T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Hardware Development Engineer, Hardware Development, Amazon LEO Redmond, Washington, USA Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Hardware Engineer, you will be a part of the team of experts working on the development of advanced antenna systems. You will own or contribute to the following: · Design and optimization of different blocks of antennas system · Design the proof of concept systems and prototypes for the next generation of the antennas · Design of RF circuitry in collaboration with RF team · Design of automated test systems, test fixtures and factory test · Bring-up and test campaigns of the active antennas · Lead and review PCB layout At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. As a hardware engineer, you will work alongside Senior Electrical Engineers supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - MS degree in electrical engineering or computer engineering, or equivalent experience Preferred Qualifications: - PhD in electrical engineering or computer engineering,", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "us_citizenship_required": { "field": "us_citizenship_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "us_citizenship_required" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 1, "years_experience_max": 5, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": true, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6b279ea58973363083", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Hardware Development Engineer, Hardware Development, Amazon LEO Redmond, Washington, USA Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Hardware Engineer, you will be a part of the team of experts working on the development of advanced antenna systems. You will own or contribute to the following: · Design and optimization of different blocks of antennas system · Design the proof of concept systems and prototypes for the next generation of the antennas · Design of RF circuitry in collaboration with RF team · Design of automated test systems, test fixtures and factory test · Bring-up and test campaigns of the active antennas · Lead and review PCB layout At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. As a hardware engineer, you will work alongside Senior Electrical Engineers supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - MS degree in electrical engineering or computer engineering, or equivalent experience Preferred Qualifications: - PhD in electrical engineering or computer engineering,", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2717b2b1b8ec99607f8ff1b2d5b80afa:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6e59f2e9ae657d6d0d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Hardware Development Engineer, Hardware Development, Amazon LEO Redmond, Washington, USA Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Hardware Engineer, you will be a part of the team of experts working on the development of advanced antenna systems. You will own or contribute to the following: · Design and optimization of different blocks of antennas system · Design the proof of concept systems and prototypes for the next generation of the antennas · Design of RF circuitry in collaboration with RF team · Design of automated test systems, test fixtures and factory test · Bring-up and test campaigns of the active antennas · Lead and review PCB layout At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. As a hardware engineer, you will work alongside Senior Electrical Engineers supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - MS degree in electrical engineering or computer engineering, or equivalent experience Preferred Qualifications: - PhD in electrical engineering or computer engineering,", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2717b2b1b8ec99607f8ff1b2d5b80afa:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.945013d97a022e0ebe", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Development Engineer, Hardware Development, Amazon LEO Redmond, Washington, USA Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Hardware Engineer, you will be a part of the team of experts working on the development of advanced antenna systems. You will own or contribute to the following: · Design and optimization of different blocks of antennas system · Design the proof of concept systems and prototypes for the next generation of the antennas · Design of RF circuitry in collaboration with RF team · Design of automated test systems, test fixtures and factory test · Bring-up and test campaigns of the active antennas · Lead and review PCB layout At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. As a hardware engineer, you will work alongside Senior Electrical Engineers supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - MS degree in electrical engineering or computer engineering, or equivalent experience Preferred Qualifications: - PhD in electrical engineering or computer engineering,", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e2edb655625e9dc5ae", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Development Engineer, Hardware Development, Amazon LEO Redmond, Washington, USA Amazon LEO is an initiative to launch a constellation of Low Earth Orbit satellites that will provide low-latency, high-speed broadband connectivity to unserved and underserved communities around the world. As a Hardware Engineer, you will be a part of the team of experts working on the development of advanced antenna systems. You will own or contribute to the following: · Design and optimization of different blocks of antennas system · Design the proof of concept systems and prototypes for the next generation of the antennas · Design of RF circuitry in collaboration with RF team · Design of automated test systems, test fixtures and factory test · Bring-up and test campaigns of the active antennas · Lead and review PCB layout At Amazon, we hire the best minds in technology to innovate and build on behalf of our customers. As a hardware engineer, you will work alongside Senior Electrical Engineers supporting the design, debug, validation and optimization of the products. You will be involved in projects from concept through production, gaining exposure to the complete design lifecycle. Export Control Requirement: Due to applicable export control laws and regulations, candidates must be a U.S. citizen or national, U.S. permanent resident (i.e., current Green Card holder), or lawfully admitted into the U.S. as a refugee or granted asylum. Basic Qualifications: - MS degree in electrical engineering or computer engineering, or equivalent experience Preferred Qualifications: - PhD in electrical engineering or computer engineering,", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3086616/hardware-development-engineer-hardware-development-amazon-leo", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "d85da07c3db5d1fa1099fe10562d85ac", "title": "Senior Physical Design Engineer - Signoff Methodology", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "Armenia", "country": "unknown", "employment_type": "unknown", "remote_status": "hybrid", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 2, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Senior Physical Design Engineer - Signoff Methodology Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you'll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You'll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what's possible in chip design. Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design. Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate with engineering teams to support and enhance implementation tool flows. Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. Strong understanding of STA flows. Familiarity with PnR,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.cd247b31964b908a3c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d85da07c3db5d1fa1099fe10562d85ac", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Physical Design Engineer - Signoff Methodology Armenia This is a hybrid role with four days per week at Cisco's Yerevan office. Meet the Team You'll be joining our CAD Physical Design team within Cisco Silicon One, which is responsible for the entire backend methodology and flow development from RTL to GDS. This team is a critical part of the group leading the development of high-quality VLSI designs and supports the creation of advanced silicon. Our design center brings together all silicon hardware and software development fields, encouraging collaboration and technical excellence. Your Impact As part of our team, you'll help develop and improve flows for all signoff disciplines and contribute to the evolution of implementation tool flows. You'll play a key role in enabling the delivery of high-performance, large-scale, and complex devices that push the boundaries of what's possible in chip design. Develop and refine backend methodologies and flows from RTL to GDS, supporting high-quality VLSI design. Contribute to the advancement of all signoff flows, including physical synthesis, place and route, power optimization, timing closure, and physical closure. Collaborate with engineering teams to support and enhance implementation tool flows. Work with advanced silicon technologies and processes to deliver complex and reliable devices. Minimum Requirements 5+ years of experience as a CAD Physical Design Engineer with PnR and STA or as a Design Engineer with strong backend design experience. B.Sc. or M.Sc. in Electrical Engineering or Computer Engineering, or a related field. Strong understanding of STA flows. Familiarity with PnR,", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.5511f107cdb993818f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d85da07c3db5d1fa1099fe10562d85ac", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Physical Design Engineer - Signoff Methodology", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.63e666db09f7b790a7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d85da07c3db5d1fa1099fe10562d85ac", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:d85da07c3db5d1fa1099fe10562d85ac:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.49bbd61498cd0f467d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "d85da07c3db5d1fa1099fe10562d85ac", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/Armenia/PD-Signoff-Methodology-Engineer_1451960", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "2833bbb49fa922ecf18ee35aaf9bc765", "title": "Systems Power Integrity Engineer - Apple Mac", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-03T23:21:15.377Z", "apply_url": "https://jobs.apple.com/en-us/details/200666410/systems-power-integrity-engineer-apple-mac?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 4, "years_experience_max": 8, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "masters", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.55153a9b1523cd1c27", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2833bbb49fa922ecf18ee35aaf9bc765:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a947826d79534453d9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2833bbb49fa922ecf18ee35aaf9bc765:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f08d0af6c52a5b9b91", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2833bbb49fa922ecf18ee35aaf9bc765:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.1ba53bd24474e76685", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Systems Power Integrity Engineer - Apple Mac", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2833bbb49fa922ecf18ee35aaf9bc765:title:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.18a01af4667139c3bd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.eefe6feaa891907b9d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Systems Power Integrity Engineer - Apple Mac Austin, United States of America The Mac organization is looking for an outstanding engineer to support the system-level Power Distribution Network (PDN) design, analysis and validation aspects of Mac and Accessory products development. You should have deep knowledge and familiarity with power delivery network design, analysis and validation methods. You will work with multi-functional teams design and implement a power supply network solution, develop and validate impedance and droop targets, and verify the quality of the power supply using lab and in-situ silicon measurements. The role involves pathfinding studies in silicon development phase where feedback is provided to silicon and packaging team on system integration tradeoffs. Ability to complete target impedance analysis, transient voltage droop and phase margin/stability analysis is required. The candidate is expected to guide and work closely with the system team on the component selections, for optimum power solutions with high and low load transient, at different performance state. The candidate is expected to work closely with System Design teams to provide detailed layout strategy and guidelines during design execution phase. The candidate is also expected to work with HW Validation teams to develop test-suites to perform system-level validation for evaluation of design margins on the power domains. The roll includes the PI support throughout the product design process which can include system pathfinding and verification stages, and characterization reviews with continuing guidance through production and ramp. Minimum Qualifications: M.S Degree with 4~7 years relevant work experience. You must have", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.161a91170560f8d355", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2833bbb49fa922ecf18ee35aaf9bc765", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Systems Power Integrity Engineer - Apple Mac", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200666410/systems-power-integrity-engineer-apple-mac?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200666410/systems-power-integrity-engineer-apple-mac?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200666410/systems-power-integrity-engineer-apple-mac?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "0236c06eb6b8d180d073d4c6eb82b521", "title": "AV Mechanical Design, Manager", "employer_name": "Nuro", "employer_slug": "nuro", "location_text": "Mountain View, California (HQ)", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 176400, "salary_max": 264600, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 176400, "base_salary_max": 264600, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2025-12-01T19:21:20.000Z", "apply_url": "https://nuro.ai/careersitem?gh_jid=7384555", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "AV Mechanical Design, Manager Mountain View, California (HQ) Who We Are Nuro is a self-driving technology company on a mission to make autonomy accessible to all. Founded in 2016, Nuro is building the world's most scalable driver, combining cutting-edge AI with automotive-grade hardware. Nuro licenses its core technology, the Nuro Driver™, to support a wide range of applications, from robotaxis and commercial fleets to personally owned vehicles. With technology proven over years of self-driving deployments, Nuro gives the automakers and mobility platforms a clear path to AVs at commercial scale, empowering a safer, richer, and more connected future. About the Role We are looking for an experienced leader to be our AV Mechanical Design Manager and lead our world class team of engineers. In this role you will be responsible for the research, design, and delivery of our autonomous hardware solutions that enable Nuro's autonomous driving systems. This work spans electronics packaging, sensor packaging, vehicle integrations, and sensor weather mitigation, and success requires the ability to manage the full product lifecycle, key partnerships with electrical and software engineering counterparts, and long term R&D efforts. Leading this team will also require strong organizational and communications skills. You will be responsible for managing a large engineering team working across multiple product lines, driving a culture of accountability and technical rigor, and developing the people and processes of the team. About the Work - Define and own the mechanical design efforts across Nuro covering prototype development, product development, and long term R&D. -", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "growth-stage", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0d696b2cd159119031", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0236c06eb6b8d180d073d4c6eb82b521", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "AV Mechanical Design, Manager Mountain View, California (HQ) Who We Are Nuro is a self-driving technology company on a mission to make autonomy accessible to all. Founded in 2016, Nuro is building the world's most scalable driver, combining cutting-edge AI with automotive-grade hardware. Nuro licenses its core technology, the Nuro Driver™, to support a wide range of applications, from robotaxis and commercial fleets to personally owned vehicles. With technology proven over years of self-driving deployments, Nuro gives the automakers and mobility platforms a clear path to AVs at commercial scale, empowering a safer, richer, and more connected future. About the Role We are looking for an experienced leader to be our AV Mechanical Design Manager and lead our world class team of engineers. In this role you will be responsible for the research, design, and delivery of our autonomous hardware solutions that enable Nuro's autonomous driving systems. This work spans electronics packaging, sensor packaging, vehicle integrations, and sensor weather mitigation, and success requires the ability to manage the full product lifecycle, key partnerships with electrical and software engineering counterparts, and long term R&D efforts. Leading this team will also require strong organizational and communications skills. You will be responsible for managing a large engineering team working across multiple product lines, driving a culture of accountability and technical rigor, and developing the people and processes of the team. About the Work - Define and own the mechanical design efforts across Nuro covering prototype development, product development, and long term R&D. -", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.aaab2b142eb6e5411c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0236c06eb6b8d180d073d4c6eb82b521", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "AV Mechanical Design, Manager", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.f57b24f634e149cb6d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0236c06eb6b8d180d073d4c6eb82b521", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0236c06eb6b8d180d073d4c6eb82b521:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://nuro.ai/careersitem?gh_jid=7384555", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "f7bb8584c3414fd14f80a228f2afc65f", "title": "Design Engineer, Mechanical", "employer_name": "Blue Bird Corp", "employer_slug": "blue-bird", "location_text": "Fort Valley, GA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T14:39:30.201Z", "apply_url": "https://recruiting.ultipro.com/BLU1004BBBC/JobBoard/1dfd3da7-cc1c-4f67-a1ca-2de669150f8c/OpportunityDetail?opportunityId=0a910b11-fc4c-4402-9f96-f3fc8e5b5b7b", "apply_url_verified": false, "ats": "ukg_pro", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Design Engineer, Mechanical Fort Valley, GA Reporting to the Director, Engineering, the Design Engineer, Mechanical will collaborate with experienced engineers and designers to develop and refine innovative design solutions. You will utilize CAD software to create detailed models and drawings, assist in prototype development, and contribute to design reviews. This position offers an excellent opportunity to develop your skills, work on exciting projects, and grow your career in a supportive and dynamic environment.", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1589526/000158952625000100/blbd-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1589526/000158952625000100/blbd-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.5979aebaa44e9d8508", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f7bb8584c3414fd14f80a228f2afc65f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design Engineer, Mechanical", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.01f14be982fee10590", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f7bb8584c3414fd14f80a228f2afc65f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f7bb8584c3414fd14f80a228f2afc65f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://recruiting.ultipro.com/BLU1004BBBC/JobBoard/1dfd3da7-cc1c-4f67-a1ca-2de669150f8c/OpportunityDetail?opportunityId=0a910b11-fc4c-4402-9f96-f3fc8e5b5b7b", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1589526/000158952625000100/blbd-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1589526/000158952625000100/blbd-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://recruiting.ultipro.com/BLU1004BBBC/JobBoard/1dfd3da7-cc1c-4f67-a1ca-2de669150f8c/OpportunityDetail?opportunityId=0a910b11-fc4c-4402-9f96-f3fc8e5b5b7b", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://recruiting.ultipro.com/BLU1004BBBC/JobBoard/1dfd3da7-cc1c-4f67-a1ca-2de669150f8c/OpportunityDetail?opportunityId=0a910b11-fc4c-4402-9f96-f3fc8e5b5b7b", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "f9de76671576f5e64f71bc0df81f409b", "title": "Electrical Engineer, Generalist", "employer_name": "Anduril", "employer_slug": "anduril", "location_text": "Costa Mesa, California, United States", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 129000, "salary_max": 171000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "total_comp", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 129000, "base_salary_max": 171000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cnbc_disruptor50", "cbinsights_unicorn", "a16z", "foundersfund", "generalcatalyst" ], "posted_at": "2026-06-10T18:15:51.000Z", "apply_url": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop & Execute", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "security_clearance": { "field": "security_clearance", "source": "llm:greenfield:inv_371_postfix", "db_column": "security_clearance" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "top_secret", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1a41bd6764ae50731f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9de76671576f5e64f71bc0df81f409b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop & Execute", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f9de76671576f5e64f71bc0df81f409b:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f2d2852c6c46eb664e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9de76671576f5e64f71bc0df81f409b", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop & Execute", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:f9de76671576f5e64f71bc0df81f409b:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6937f6fd4c9a9c29d3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9de76671576f5e64f71bc0df81f409b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop & Execute", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bef424dfd3a15b4dde", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "f9de76671576f5e64f71bc0df81f409b", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop & Execute", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/4959646007?gh_jid=4959646007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "1724fefa0c39fad29a3153587e114f79", "title": "Power and Signal Integrity Engineer, PhD Graduate", "employer_name": "Google", "employer_slug": "google", "location_text": "Tel Aviv, Israel; +1 more", "country": "IL", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-18T15:30:12.000Z", "apply_url": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "apply_url_verified": false, "ats": "google_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "parental_leave_weeks": 18, "non_birth_parent_leave_weeks": 18, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 90, "benefit_verified": true, "benefit_last_verified": "2026-05-07", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "parental_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "non_birth_parent_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.04422074168defd3b0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1724fefa0c39fad29a3153587e114f79:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3abbdf84fe60528310", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1724fefa0c39fad29a3153587e114f79:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.78090e182a8642cfbe", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1724fefa0c39fad29a3153587e114f79:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.15758ae5216bf6176e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.295a45c57b611f804a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e155249d2970e9b556", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1724fefa0c39fad29a3153587e114f79", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power and Signal Integrity Engineer, PhD Graduate Tel Aviv, Israel; +1 more Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. As a Power and Signal Integrity Engineer, you will be responsible for the design and characterization of signal and power integrity of our IC designs. You will design the external electrical interfaces of the device, from their Signal/Power-integrity and electrical usage perspectives and set up methodologies, perform simulations, silicon characterization and correlations to ensure our IC designs meet systems design budgets and achieve the highest performance. You will work with systems architects, ASIC design, systems engineers, and partner cross-functionally with teams and external vendors/partners. The ML, Systems, & Cloud AI (MSCA) organization at Google designs, implements, and manages the hardware, software, machine learning, and systems infrastructure for all Google services (Search, YouTube, etc.) and Google Cloud. Our end users are Googlers, Cloud customers and the billions of people who use Google services around the world. We prioritize security, efficiency, and reliability across everything we do - from developing our latest TPUs to running a global network, while driving towards shaping the future of hyperscale computing. Our global impact spans software and hardware, including Google Cloud's Vertex AI, the leading AI platform for bringing Gemini models to enterprise customers. Generate precise electrical", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-05-07" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckUPfNhCDd8AhWXHCQE7NDDjkcxy6z5GkNimhETmXc53sEjsAvkGZm19Aj0_Rd70Fgbz1VSkVgg3o1FhuvKlNcCI_bNwMoRrofvQ_cRPhYmUo3VONnd3u0tdbL5mbjA%3D%3D_V2&loc=IL&title=Power+and+Signal+Integrity+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "5d8865e9d533ce4e2e454a4f48fade1a", "title": "Hardware Engineer", "employer_name": "Legrand", "employer_slug": "legrand", "location_text": "Fremont, CA, US", "country": "US", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 100000, "salary_max": 115000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 100000, "base_salary_max": 115000, "salary_disclosed": true, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "apply_url_verified": false, "ats": "icims", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Hardware Engineer Fremont, CA, US Position Description Legrand has an exciting opportunity for a Hardware Engineer to join the ZPE Systems Team in Fremont, CA. Key Responsibilities: Design and Development: · Design and develop hardware devices for infrastructure management, including routers, serial consoles, and edge network components. · Review circuit designs, PCB layout, mechanical designs, and assist on component selection for high-performance, reliable, and energy-efficient hardware. · Collaborate with contract manufacturers and vendors to ensure designs are manufacturable and cost-effective. · Collaborate with product management to define and refine product requirements. · Coordinate with firmware and software teams to ensure seamless integration of hardware components. Firmware Development: · Maintain a cross-compiler environment for embedded systems. · Write and review code for boot loader, BIOS, device drivers, firmware installation, and hardware tests. · Maintain source control management with git. · Follow agile development strategies and practices. Prototyping and Testing: · Build and test hardware prototypes, refining designs based on test results. · Conduct measurements and analyses to verify design integrity and compliance with industry standards. · Collaborate with contract manufacturers to review prototype and production testing results. Manufacturing and Production Support: · Work closely with contract manufacturers to resolve technical issues during production, ensuring products meet quali", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.173f6b3f6cb688a05c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5d8865e9d533ce4e2e454a4f48fade1a", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Engineer Fremont, CA, US Position Description Legrand has an exciting opportunity for a Hardware Engineer to join the ZPE Systems Team in Fremont, CA. Key Responsibilities: Design and Development: · Design and develop hardware devices for infrastructure management, including routers, serial consoles, and edge network components. · Review circuit designs, PCB layout, mechanical designs, and assist on component selection for high-performance, reliable, and energy-efficient hardware. · Collaborate with contract manufacturers and vendors to ensure designs are manufacturable and cost-effective. · Collaborate with product management to define and refine product requirements. · Coordinate with firmware and software teams to ensure seamless integration of hardware components. Firmware Development: · Maintain a cross-compiler environment for embedded systems. · Write and review code for boot loader, BIOS, device drivers, firmware installation, and hardware tests. · Maintain source control management with git. · Follow agile development strategies and practices. Prototyping and Testing: · Build and test hardware prototypes, refining designs based on test results. · Conduct measurements and analyses to verify design integrity and compliance with industry standards. · Collaborate with contract manufacturers to review prototype and production testing results. Manufacturing and Production Support: · Work closely with contract manufacturers to resolve technical issues during production, ensuring products meet quali", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.23ba54c76be1eb96a7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5d8865e9d533ce4e2e454a4f48fade1a", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Engineer Fremont, CA, US Position Description Legrand has an exciting opportunity for a Hardware Engineer to join the ZPE Systems Team in Fremont, CA. Key Responsibilities: Design and Development: · Design and develop hardware devices for infrastructure management, including routers, serial consoles, and edge network components. · Review circuit designs, PCB layout, mechanical designs, and assist on component selection for high-performance, reliable, and energy-efficient hardware. · Collaborate with contract manufacturers and vendors to ensure designs are manufacturable and cost-effective. · Collaborate with product management to define and refine product requirements. · Coordinate with firmware and software teams to ensure seamless integration of hardware components. Firmware Development: · Maintain a cross-compiler environment for embedded systems. · Write and review code for boot loader, BIOS, device drivers, firmware installation, and hardware tests. · Maintain source control management with git. · Follow agile development strategies and practices. Prototyping and Testing: · Build and test hardware prototypes, refining designs based on test results. · Conduct measurements and analyses to verify design integrity and compliance with industry standards. · Collaborate with contract manufacturers to review prototype and production testing results. Manufacturing and Production Support: · Work closely with contract manufacturers to resolve technical issues during production, ensuring products meet quali", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d2ebcb9e815221482f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5d8865e9d533ce4e2e454a4f48fade1a", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Engineer Fremont, CA, US Position Description Legrand has an exciting opportunity for a Hardware Engineer to join the ZPE Systems Team in Fremont, CA. Key Responsibilities: Design and Development: · Design and develop hardware devices for infrastructure management, including routers, serial consoles, and edge network components. · Review circuit designs, PCB layout, mechanical designs, and assist on component selection for high-performance, reliable, and energy-efficient hardware. · Collaborate with contract manufacturers and vendors to ensure designs are manufacturable and cost-effective. · Collaborate with product management to define and refine product requirements. · Coordinate with firmware and software teams to ensure seamless integration of hardware components. Firmware Development: · Maintain a cross-compiler environment for embedded systems. · Write and review code for boot loader, BIOS, device drivers, firmware installation, and hardware tests. · Maintain source control management with git. · Follow agile development strategies and practices. Prototyping and Testing: · Build and test hardware prototypes, refining designs based on test results. · Conduct measurements and analyses to verify design integrity and compliance with industry standards. · Collaborate with contract manufacturers to review prototype and production testing results. Manufacturing and Production Support: · Work closely with contract manufacturers to resolve technical issues during production, ensuring products meet quali", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.c75640520889fa53ec", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5d8865e9d533ce4e2e454a4f48fade1a", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:5d8865e9d533ce4e2e454a4f48fade1a:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs-legrand.icims.com/jobs/10071/hardware-engineer/job", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "64f830a528849cbfe1d247a4c5556c4e", "title": "mmWave IC Design Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Sunnyvale, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 181100, "salary_max": 318400, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 181100, "base_salary_max": 318400, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T21:28:31.557Z", "apply_url": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.350917c8d7ffefbf86", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:64f830a528849cbfe1d247a4c5556c4e:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d4c1fffb858dc42c68", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:64f830a528849cbfe1d247a4c5556c4e:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.de0ea270bf05aaccab", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:64f830a528849cbfe1d247a4c5556c4e:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.a3521f00af6f909818", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "mmWave IC Design Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:64f830a528849cbfe1d247a4c5556c4e:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b8b7d879b4fa688fa0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.bc667216f5df1a4d08", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "mmWave IC Design Engineer Sunnyvale, United States of America Would you like to be a part of Apple's fast-growing mmWave and cellular wireless design team? We are responsible for all aspects of mmWave/cellular silicon development with a particular emphasis on highly integrated and efficient designs and technologies that transform the user experience at the product level! As a millimeter-wave IC design engineer, you will be the owner of providing circuit and system solutions for multi-gigabit wireless chips! We have multiple needs and are open to multiple experience levels. Please apply to be considered for our growing team. As a mmWave Design Engineer at Apple, you will utilize your vast background in circuit design and be responsible for providing mmW design solutions for wireless chips. Responsibilities include collaborating with platform architects, system engineers, and digital design groups to define the requirements for mmWave phased-array front-end and baseband blocks based on the product requirements. Working with the technology team and foundries on process evaluation/selection for the target device. Designing various transceiver blocks in TX, RX, and LO chains. Partnering with the design, layout, and chip integration teams to integrate the IP's and verify the top-level functionality and performance. Working with mmWave test engineers to bring up and characterize chips. Design and optimize mmWave transceiver blocks in TX, RX, or LO chain for multi-gigabit wireless systems. Perform simulation, integration, and verification at mega block, chain, or chip level, work cross-functionally to ensure design integrity through tapeout. Oversee layout design, guide floorplanning, review layout,", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.334e62d6f26b3eca0a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "64f830a528849cbfe1d247a4c5556c4e", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "mmWave IC Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658563/mmwave-ic-design-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "b0f7d81fab905832b384da238c2870c6", "title": "Solutions Developer, Prototyping and Customer Engineering (PACE)", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Arlington, Virginia, USA", "country": "US", "employment_type": "part_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 131300, "salary_max": 177600, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 131300, "base_salary_max": 177600, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-28T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Solutions Developer, Prototyping and Customer Engineering (PACE) Arlington, Virginia, USA Job Summary Do you have a builder's mentality where \"show me\" means more than \"tell me\"? Are you passionate about technology and AI, understand cloud architectures and platforms, and quick to adopt emerging technologies? Are you adept at working with customers to experiment with innovative approaches and validate technical feasibility? As trusted customer advocates, the Prototyping and Customer Engineering (PACE) team helps customers create early iterations of products and solutions, often exploring new technical grounds. We're seeking experienced technologists who possess a unique balance of technical depth, business acumen, and strong interpersonal skills. Role Overview As a Solutions Developer, you will partner with customers and AWS account and service teams to craft highly scalable, flexible, and resilient solutions that address customer business problems and accelerate AWS adoption. You'll shape and build prototypes across domains including Machine Learning, Agentic Design, Serverless Architecture, and multi-modal Generative AI-with most projects exploring the art of the possible using the latest methods, frameworks, services, and models. You'll work across industry verticals including automotive, energy, healthcare, telecommunications, manufacturing, and media and entertainment. The ability to connect technology with measurable business value is critical-you will help drive revenue growth and strategic outcomes for customers, influencing adoption decisions and accelerating customer success with AWS. Key Expectations Profile: You're a consistently strong contributor on small teams build customer prototypes. You must be hands-on with technical software engineering skills, support direct customer communication, and capable of learning new technologies and", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1dcb5dfb2b23d80283", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b0f7d81fab905832b384da238c2870c6", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Solutions Developer, Prototyping and Customer Engineering (PACE) Arlington, Virginia, USA Job Summary Do you have a builder's mentality where \"show me\" means more than \"tell me\"? Are you passionate about technology and AI, understand cloud architectures and platforms, and quick to adopt emerging technologies? Are you adept at working with customers to experiment with innovative approaches and validate technical feasibility? As trusted customer advocates, the Prototyping and Customer Engineering (PACE) team helps customers create early iterations of products and solutions, often exploring new technical grounds. We're seeking experienced technologists who possess a unique balance of technical depth, business acumen, and strong interpersonal skills. Role Overview As a Solutions Developer, you will partner with customers and AWS account and service teams to craft highly scalable, flexible, and resilient solutions that address customer business problems and accelerate AWS adoption. You'll shape and build prototypes across domains including Machine Learning, Agentic Design, Serverless Architecture, and multi-modal Generative AI-with most projects exploring the art of the possible using the latest methods, frameworks, services, and models. You'll work across industry verticals including automotive, energy, healthcare, telecommunications, manufacturing, and media and entertainment. The ability to connect technology with measurable business value is critical-you will help drive revenue growth and strategic outcomes for customers, influencing adoption decisions and accelerating customer success with AWS. Key Expectations Profile: You're a consistently strong contributor on small teams build customer prototypes. You must be hands-on with technical software engineering skills, support direct customer communication, and capable of learning new technologies and", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6321bc243003abb576", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b0f7d81fab905832b384da238c2870c6", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Solutions Developer, Prototyping and Customer Engineering (PACE) Arlington, Virginia, USA Job Summary Do you have a builder's mentality where \"show me\" means more than \"tell me\"? Are you passionate about technology and AI, understand cloud architectures and platforms, and quick to adopt emerging technologies? Are you adept at working with customers to experiment with innovative approaches and validate technical feasibility? As trusted customer advocates, the Prototyping and Customer Engineering (PACE) team helps customers create early iterations of products and solutions, often exploring new technical grounds. We're seeking experienced technologists who possess a unique balance of technical depth, business acumen, and strong interpersonal skills. Role Overview As a Solutions Developer, you will partner with customers and AWS account and service teams to craft highly scalable, flexible, and resilient solutions that address customer business problems and accelerate AWS adoption. You'll shape and build prototypes across domains including Machine Learning, Agentic Design, Serverless Architecture, and multi-modal Generative AI-with most projects exploring the art of the possible using the latest methods, frameworks, services, and models. You'll work across industry verticals including automotive, energy, healthcare, telecommunications, manufacturing, and media and entertainment. The ability to connect technology with measurable business value is critical-you will help drive revenue growth and strategic outcomes for customers, influencing adoption decisions and accelerating customer success with AWS. Key Expectations Profile: You're a consistently strong contributor on small teams build customer prototypes. You must be hands-on with technical software engineering skills, support direct customer communication, and capable of learning new technologies and", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.a99aa7c5ac6673c5c1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b0f7d81fab905832b384da238c2870c6", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b0f7d81fab905832b384da238c2870c6:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10406021/solutions-developer-prototyping-and-customer-engineering-pace", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "39b0b5c2347227ce66519ea70ef53a1b", "title": "HW Electronic Engineer", "employer_name": "AST SpaceMobile", "employer_slug": "ast-spacemobile", "location_text": "Barcelona, Spain", "country": "ES", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-19T15:52:56.000Z", "apply_url": "https://ast-science.com/company/careers/?gh_jid=4696961005", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "HW Electronic Engineer Barcelona, Spain AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an Electronic Hardware Engineer to design, develop, validate and document onboard electronic systems for satellites, ensuring their reliability, performance and compliance with aerospace industry standards. Key Responsibilities: • Design schematics and PCBs for satellite electronic systems (power subsystems, communications, control, etc.) • Perform simulations, signal analysis, electrical and thermal integrity • Participate in component selection in accordance with space standards (ECSS, MIL-STD, etc.) • Collaborate in HW-SW system integration with other departments (software, systems, integration and testing) • Prepare technical documentation in compliance with aerospace standards • Support environmental test campaigns (EMC, vibration, thermal-vacuum, etc.) • Collaborate with suppliers for the manufacturing and assembly of electronic boards • Participate in design reviews (PDR, CDR) with clients or agencies (ESA, NASA, etc.) Qualifications Education : University degree in Electronic Engineering, Telecommunications Engineering, Aerospace Engineering or similar Experience : A minimum of 8 years in electronic hardware design, preferably in high-reliability environments (aerospace, defense, automotive) Experience in multilayer PCB design, high-speed design, and environments with thermal or electromagnetic constraints Preferred Qualifications : •", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1780312/000178031226000006/asts-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1780312/000178031226000006/asts-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0a5bdcdc69a57b44bd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "39b0b5c2347227ce66519ea70ef53a1b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "HW Electronic Engineer Barcelona, Spain AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an Electronic Hardware Engineer to design, develop, validate and document onboard electronic systems for satellites, ensuring their reliability, performance and compliance with aerospace industry standards. Key Responsibilities: • Design schematics and PCBs for satellite electronic systems (power subsystems, communications, control, etc.) • Perform simulations, signal analysis, electrical and thermal integrity • Participate in component selection in accordance with space standards (ECSS, MIL-STD, etc.) • Collaborate in HW-SW system integration with other departments (software, systems, integration and testing) • Prepare technical documentation in compliance with aerospace standards • Support environmental test campaigns (EMC, vibration, thermal-vacuum, etc.) • Collaborate with suppliers for the manufacturing and assembly of electronic boards • Participate in design reviews (PDR, CDR) with clients or agencies (ESA, NASA, etc.) Qualifications Education : University degree in Electronic Engineering, Telecommunications Engineering, Aerospace Engineering or similar Experience : A minimum of 8 years in electronic hardware design, preferably in high-reliability environments (aerospace, defense, automotive) Experience in multilayer PCB design, high-speed design, and environments with thermal or electromagnetic constraints Preferred Qualifications : •", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:39b0b5c2347227ce66519ea70ef53a1b:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1b7f53739f37452665", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "39b0b5c2347227ce66519ea70ef53a1b", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "HW Electronic Engineer Barcelona, Spain AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an Electronic Hardware Engineer to design, develop, validate and document onboard electronic systems for satellites, ensuring their reliability, performance and compliance with aerospace industry standards. Key Responsibilities: • Design schematics and PCBs for satellite electronic systems (power subsystems, communications, control, etc.) • Perform simulations, signal analysis, electrical and thermal integrity • Participate in component selection in accordance with space standards (ECSS, MIL-STD, etc.) • Collaborate in HW-SW system integration with other departments (software, systems, integration and testing) • Prepare technical documentation in compliance with aerospace standards • Support environmental test campaigns (EMC, vibration, thermal-vacuum, etc.) • Collaborate with suppliers for the manufacturing and assembly of electronic boards • Participate in design reviews (PDR, CDR) with clients or agencies (ESA, NASA, etc.) Qualifications Education : University degree in Electronic Engineering, Telecommunications Engineering, Aerospace Engineering or similar Experience : A minimum of 8 years in electronic hardware design, preferably in high-reliability environments (aerospace, defense, automotive) Experience in multilayer PCB design, high-speed design, and environments with thermal or electromagnetic constraints Preferred Qualifications : •", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:39b0b5c2347227ce66519ea70ef53a1b:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.292b6472157f61e56a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "39b0b5c2347227ce66519ea70ef53a1b", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "HW Electronic Engineer Barcelona, Spain AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an Electronic Hardware Engineer to design, develop, validate and document onboard electronic systems for satellites, ensuring their reliability, performance and compliance with aerospace industry standards. Key Responsibilities: • Design schematics and PCBs for satellite electronic systems (power subsystems, communications, control, etc.) • Perform simulations, signal analysis, electrical and thermal integrity • Participate in component selection in accordance with space standards (ECSS, MIL-STD, etc.) • Collaborate in HW-SW system integration with other departments (software, systems, integration and testing) • Prepare technical documentation in compliance with aerospace standards • Support environmental test campaigns (EMC, vibration, thermal-vacuum, etc.) • Collaborate with suppliers for the manufacturing and assembly of electronic boards • Participate in design reviews (PDR, CDR) with clients or agencies (ESA, NASA, etc.) Qualifications Education : University degree in Electronic Engineering, Telecommunications Engineering, Aerospace Engineering or similar Experience : A minimum of 8 years in electronic hardware design, preferably in high-reliability environments (aerospace, defense, automotive) Experience in multilayer PCB design, high-speed design, and environments with thermal or electromagnetic constraints Preferred Qualifications : •", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8866eab74f7475b128", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "39b0b5c2347227ce66519ea70ef53a1b", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "HW Electronic Engineer Barcelona, Spain AST SpaceMobile is building the first and only global cellular broadband network in space to operate directly with standard, unmodified mobile devices based on our extensive IP and patent portfolio and designed for both commercial and government applications. Our engineers and space scientists are on a mission to eliminate the connectivity gaps faced by today's five billion mobile subscribers and finally bring broadband to the billions who remain unconnected. Position Overview We are seeking an Electronic Hardware Engineer to design, develop, validate and document onboard electronic systems for satellites, ensuring their reliability, performance and compliance with aerospace industry standards. Key Responsibilities: • Design schematics and PCBs for satellite electronic systems (power subsystems, communications, control, etc.) • Perform simulations, signal analysis, electrical and thermal integrity • Participate in component selection in accordance with space standards (ECSS, MIL-STD, etc.) • Collaborate in HW-SW system integration with other departments (software, systems, integration and testing) • Prepare technical documentation in compliance with aerospace standards • Support environmental test campaigns (EMC, vibration, thermal-vacuum, etc.) • Collaborate with suppliers for the manufacturing and assembly of electronic boards • Participate in design reviews (PDR, CDR) with clients or agencies (ESA, NASA, etc.) Qualifications Education : University degree in Electronic Engineering, Telecommunications Engineering, Aerospace Engineering or similar Experience : A minimum of 8 years in electronic hardware design, preferably in high-reliability environments (aerospace, defense, automotive) Experience in multilayer PCB design, high-speed design, and environments with thermal or electromagnetic constraints Preferred Qualifications : •", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1780312/000178031226000006/asts-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1780312/000178031226000006/asts-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://ast-science.com/company/careers/?gh_jid=4696961005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://ast-science.com/company/careers/?gh_jid=4696961005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://ast-science.com/company/careers/?gh_jid=4696961005", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "4c612bc052f0fe4e0383a49610343f7b", "title": "Senior Platform Engineer", "employer_name": "Clutch", "employer_slug": "clutch", "location_text": "Toronto, ON", "country": "CA", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "a16z" ], "posted_at": "2026-02-05T22:09:18.000Z", "apply_url": "https://job-boards.greenhouse.io/clutch/jobs/5795257004", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Platform Engineer Toronto, ON About Clutch: We're on a mission to reinvent the way people buy, sell, and own cars. Are you game? Clutch is Canada's largest online used car retailer, delivering a seamless, hassle-free car-buying experience to drivers everywhere. Customers can browse hundreds of cars from the comfort of their home, get the right one delivered to their door, and enjoy peace of mind with our 10-Day Money-Back Guarantee… and that's just the beginning. Named five years in a row to the Globe & Mail's list of the Top Growing Companies in Canada and also awarded spots on Deloitte's Technology Fast 50™ and Fast 500™ lists, we're looking to add curious, hard-working, and driven individuals to our growing team. Headquartered in Toronto, Clutch was founded in 2017 and currently services Ontario, New Brunswick, Nova Scotia, British Columbia, and Prince Edward Island. Clutch is backed by a number of world-class investors, including D1 Capital, Canaan, Real Ventures, BrandProject, and Upper90. To learn more, visit clutch.ca . About the Role Clutch is growing, and our DevOps practices need to grow with us. We're looking for a Senior Platform Engineer to help lead that evolution-someone who knows how to build a great product shipping pipeline and can help us develop great devops practices as we scale. Our engineering team ships frequently, and we're facing real challenges: managing the volume of changes moving through our pipeline each day while ensuring our quality checks keep pace. You'll work on a mature microservices monorepo,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "growth-stage", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7737d32034c7c44d29", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4c612bc052f0fe4e0383a49610343f7b", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Platform Engineer Toronto, ON About Clutch: We're on a mission to reinvent the way people buy, sell, and own cars. Are you game? Clutch is Canada's largest online used car retailer, delivering a seamless, hassle-free car-buying experience to drivers everywhere. Customers can browse hundreds of cars from the comfort of their home, get the right one delivered to their door, and enjoy peace of mind with our 10-Day Money-Back Guarantee… and that's just the beginning. Named five years in a row to the Globe & Mail's list of the Top Growing Companies in Canada and also awarded spots on Deloitte's Technology Fast 50™ and Fast 500™ lists, we're looking to add curious, hard-working, and driven individuals to our growing team. Headquartered in Toronto, Clutch was founded in 2017 and currently services Ontario, New Brunswick, Nova Scotia, British Columbia, and Prince Edward Island. Clutch is backed by a number of world-class investors, including D1 Capital, Canaan, Real Ventures, BrandProject, and Upper90. To learn more, visit clutch.ca . About the Role Clutch is growing, and our DevOps practices need to grow with us. We're looking for a Senior Platform Engineer to help lead that evolution-someone who knows how to build a great product shipping pipeline and can help us develop great devops practices as we scale. Our engineering team ships frequently, and we're facing real challenges: managing the volume of changes moving through our pipeline each day while ensuring our quality checks keep pace. You'll work on a mature microservices monorepo,", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.205b306fedc52e7b22", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "4c612bc052f0fe4e0383a49610343f7b", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:4c612bc052f0fe4e0383a49610343f7b:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/clutch/jobs/5795257004", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/clutch/jobs/5795257004", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/clutch/jobs/5795257004", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/clutch/jobs/5795257004", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "857c18f61fb9e35864e04248b72dcdfc", "title": "Senior Hardware Systems Engineer, Watches", "employer_name": "Google", "employer_slug": "google", "location_text": "Mountain View, CA, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 159000, "salary_max": 231000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 159000, "base_salary_max": 231000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T08:40:18.000Z", "apply_url": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "apply_url_verified": false, "ats": "google_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "parental_leave_weeks": 18, "non_birth_parent_leave_weeks": 18, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 94, "benefit_verified": true, "benefit_last_verified": "2026-05-07", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "parental_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/", "db_column": "non_birth_parent_leave_weeks", "source_url": "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 4, "years_experience_max": 8, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.42ded615c4f454060b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:857c18f61fb9e35864e04248b72dcdfc:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8fe7f5922f17442c1a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:857c18f61fb9e35864e04248b72dcdfc:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f461da7a6e877bca63", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:857c18f61fb9e35864e04248b72dcdfc:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.0fd8b31cfa3d30d680", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Senior Hardware Systems Engineer, Watches", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:857c18f61fb9e35864e04248b72dcdfc:title:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.16f3fc7aa432fe35c3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ab84c8c94e817ae1ea", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Hardware Systems Engineer, Watches Mountain View, CA, USA The Pixel Watch Electrical Engineering (EE) team is responsible for the end-to-end hardware development of Google's first-party Watch products. We work with product managers during initial concept and design phases, advocate new technology investigations, and manage the entire hardware lifecycle, from board integration and comprehensive validation to overseeing manufacturing to deliver products with a user experience and state-of-the-art health sensing capabilities. As an Electrical Engineer on the Watch product team, you will be responsible for key design activities throughout the Watch product development phase. This includes focusing on technical design development and optimization, collaborating with cross-functional teams, and working closely with external suppliers and partners for design and manufacturing. You will also work on some hardware related issues Failure Analysis (FA) that feedback from users, EFFA, RMA. Individual pay is determined by factors including job-related skills, experience, and relevant education or training. US: $159000 - $231000 (USD) + 15% bonus target + bonus + equity + benefits Learn more about benefits at Google . Be responsible for the electrical design integration and the validation of Google's Watch products. Deliver the boards (PCBA or FPCA) by performing all the design tasks including schematic and layout, collaboration with product design, Signal Integrity and Power Integrity (SIPI), power and sub-system teams for the design optimization. Bring up the system, plan the validation, trouble shooting and conduct the measurements. Debug the issue discovered from the factory production, reliability, user trial, RMA, etc. Collaborate with Google", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.70ddba66ee43faba59", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "857c18f61fb9e35864e04248b72dcdfc", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Hardware Systems Engineer, Watches", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1652044/000165204426000018/goog-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "https://blog.google/company-news/outreach-and-initiatives/diversity/international-womens-day-2022/" ], "checked_at": "2026-05-07" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-05-07" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.google.com/about/careers/applications/signin?jobId=CiUAL2FckVo-T3YVEIFDG8WLH1yX1a_F7cI71uqT5-9uo5EbjguXEjsACxwdTAaX25PsD0YfFrGOz0UGjbRPh03GzkyezYd-Hf6WxrOm6ACOWHkhPhsbsKjBQNPw4l2odMydcA%3D%3D_V2&loc=US&title=Senior+Hardware+Systems+Engineer", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "237687a15733503c39cbfab76968c8c2", "title": "Designer, Hardware Outlet", "employer_name": "Tapestry, Inc.", "employer_slug": "tapestry", "location_text": "New York, New York, USA (Corporate Headquarters)", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://tapestry.wd108.myworkdayjobs.com/Tapestry_Careers/job/New-York-New-York-USA-Corporate-Headquarters/Designer--Hardware-Outlet_JR1924", "apply_url_verified": false, "ats": "workday", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Designer, Hardware Outlet New York, New York, USA (Corporate Headquarters) posted: Posted 30+ Days Ago", "parental_leave_weeks": 8, "non_birth_parent_leave_weeks": 8, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 81, "benefit_verified": true, "benefit_last_verified": "2026-05-07", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1116132/000111613225000019/tpr-20250628.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1116132/000111613225000019/tpr-20250628.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/", "db_column": "parental_leave_weeks", "source_url": "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/", "db_column": "non_birth_parent_leave_weeks", "source_url": "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "design", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Retail", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 35, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.83707ef40b9fa9c76c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "237687a15733503c39cbfab76968c8c2", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Tapestry, Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.fe17fde055bc543f91", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "237687a15733503c39cbfab76968c8c2", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Designer, Hardware Outlet", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.5547296abe83636da0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "237687a15733503c39cbfab76968c8c2", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:237687a15733503c39cbfab76968c8c2:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1116132/000111613225000019/tpr-20250628.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1116132/000111613225000019/tpr-20250628.htm" ], "checked_at": null }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://tapestry.wd108.myworkdayjobs.com/Tapestry_Careers/job/New-York-New-York-USA-Corporate-Headquarters/Designer--Hardware-Outlet_JR1924", "source_values": [ "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/" ], "checked_at": "2026-05-07" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://tapestry.wd108.myworkdayjobs.com/Tapestry_Careers/job/New-York-New-York-USA-Corporate-Headquarters/Designer--Hardware-Outlet_JR1924", "source_values": [ "https://www.tapestry.com/company-news/tapestry-enhances-parental-and-family-care-offerings-to-foster-work-and-personal-life-balance/" ], "checked_at": "2026-05-07" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-05-07" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://tapestry.wd108.myworkdayjobs.com/Tapestry_Careers/job/New-York-New-York-USA-Corporate-Headquarters/Designer--Hardware-Outlet_JR1924", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://tapestry.wd108.myworkdayjobs.com/Tapestry_Careers/job/New-York-New-York-USA-Corporate-Headquarters/Designer--Hardware-Outlet_JR1924", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "89237a0be43b9b20049998f2d984e80d", "title": "Sr. IC Package Design Engineer (Silicon Engineering)", "employer_name": "SpaceX", "employer_slug": "spacex", "location_text": "Irvine, CA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 160000, "salary_max": 225000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 160000, "base_salary_max": 225000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn", "a16z", "sequoia", "foundersfund" ], "posted_at": "2026-03-12T18:15:37.000Z", "apply_url": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Sr. IC Package Design Engineer (Silicon Engineering) Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "field": "equity_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_type" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "weekend_work": { "field": "weekend_work", "source": "llm:greenfield:inv_371_postfix", "db_column": "weekend_work" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "us_citizenship_required": { "field": "us_citizenship_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "us_citizenship_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": true, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.553b3ebdd273f5d33e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "89237a0be43b9b20049998f2d984e80d", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. IC Package Design Engineer (Silicon Engineering) Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:89237a0be43b9b20049998f2d984e80d:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6f971df7ee2ad03306", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "89237a0be43b9b20049998f2d984e80d", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Sr. IC Package Design Engineer (Silicon Engineering) Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:89237a0be43b9b20049998f2d984e80d:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.558df42ce06592405a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "89237a0be43b9b20049998f2d984e80d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Sr. IC Package Design Engineer (Silicon Engineering)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:89237a0be43b9b20049998f2d984e80d:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.75089bd511e75991c9", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "89237a0be43b9b20049998f2d984e80d", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Sr. IC Package Design Engineer (Silicon Engineering) Irvine, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. SR. IC PACKAGE DESIGN ENGINEER (SILICON ENGINEERING) At SpaceX we're leveraging our experience in building rockets and spacecraft to deploy Starlink, the world's most advanced broadband internet system. Starlink is the world's largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system - thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We've only begun to scratch the surface of Starlink's potential global impact and are looking for best-in-class engineers to help maximize Starlink's utility for communities and businesses around the globe. We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. As an IC Package Design Engineer, you will be an integral part of the IC design team and lead packaging for custom", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.aa06eed8c0a4324522", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "89237a0be43b9b20049998f2d984e80d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Sr. IC Package Design Engineer (Silicon Engineering)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8460765002?gh_jid=8460765002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "a888d04c74f92939319cd2aa0deb85ef", "title": "Systems Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Cupertino, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 126800, "salary_max": 220900, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 126800, "base_salary_max": 220900, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-04T12:39:04.978Z", "apply_url": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Systems Engineer Cupertino, United States of America Apple's Compositing, Color, and Display Software organization provides the graphics software foundation for all of Apple's innovative products, including iPhone, iPad, Apple TV, Mac, Apple Watch and Vision Pro. Our goal is to enable developers and UI designers to create exceptional visual experiences by efficiently utilizing hardware acceleration and color technologies through compositing and display. We're a highly technical team working on critical compositing and windowing system components across Apple's platforms. Our mission is to maintain and evolve the compositing infrastructure that powers billions of devices. We tackle challenging problems in scheduler architecture, event processing, security rendering, hardware integration, and legacy system support while maintaining the high-quality standards our users expect. If you are passionate about building efficient compositing systems, optimizing for new hardware capabilities, and great battery life for millions of users worldwide, we want to hear from you. If you're excited about working across the full spectrum of compositing challenges-from scheduler design to event handling to security features-this role is for you. We're seeking a talented software engineer to join our UI Compositing team and grow into a key contributor to the core compositing infrastructure that powers all Apple devices. You'll have the opportunity to learn and work across different technical domains-from low-level system optimization to cross-platform feature development-while being mentored by experienced engineers. This role is ideal for someone early in their career who is eager to tackle diverse technical challenges and develop both depth and breadth in their engineering", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.46af058782da91e173", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a888d04c74f92939319cd2aa0deb85ef", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Systems Engineer Cupertino, United States of America Apple's Compositing, Color, and Display Software organization provides the graphics software foundation for all of Apple's innovative products, including iPhone, iPad, Apple TV, Mac, Apple Watch and Vision Pro. Our goal is to enable developers and UI designers to create exceptional visual experiences by efficiently utilizing hardware acceleration and color technologies through compositing and display. We're a highly technical team working on critical compositing and windowing system components across Apple's platforms. Our mission is to maintain and evolve the compositing infrastructure that powers billions of devices. We tackle challenging problems in scheduler architecture, event processing, security rendering, hardware integration, and legacy system support while maintaining the high-quality standards our users expect. If you are passionate about building efficient compositing systems, optimizing for new hardware capabilities, and great battery life for millions of users worldwide, we want to hear from you. If you're excited about working across the full spectrum of compositing challenges-from scheduler design to event handling to security features-this role is for you. We're seeking a talented software engineer to join our UI Compositing team and grow into a key contributor to the core compositing infrastructure that powers all Apple devices. You'll have the opportunity to learn and work across different technical domains-from low-level system optimization to cross-platform feature development-while being mentored by experienced engineers. This role is ideal for someone early in their career who is eager to tackle diverse technical challenges and develop both depth and breadth in their engineering", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d246332d2f08260bc2", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a888d04c74f92939319cd2aa0deb85ef", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Systems Engineer Cupertino, United States of America Apple's Compositing, Color, and Display Software organization provides the graphics software foundation for all of Apple's innovative products, including iPhone, iPad, Apple TV, Mac, Apple Watch and Vision Pro. Our goal is to enable developers and UI designers to create exceptional visual experiences by efficiently utilizing hardware acceleration and color technologies through compositing and display. We're a highly technical team working on critical compositing and windowing system components across Apple's platforms. Our mission is to maintain and evolve the compositing infrastructure that powers billions of devices. We tackle challenging problems in scheduler architecture, event processing, security rendering, hardware integration, and legacy system support while maintaining the high-quality standards our users expect. If you are passionate about building efficient compositing systems, optimizing for new hardware capabilities, and great battery life for millions of users worldwide, we want to hear from you. If you're excited about working across the full spectrum of compositing challenges-from scheduler design to event handling to security features-this role is for you. We're seeking a talented software engineer to join our UI Compositing team and grow into a key contributor to the core compositing infrastructure that powers all Apple devices. You'll have the opportunity to learn and work across different technical domains-from low-level system optimization to cross-platform feature development-while being mentored by experienced engineers. This role is ideal for someone early in their career who is eager to tackle diverse technical challenges and develop both depth and breadth in their engineering", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.cf1634bba852f94548", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a888d04c74f92939319cd2aa0deb85ef", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Systems Engineer", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.bea854663863f6004f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a888d04c74f92939319cd2aa0deb85ef", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a888d04c74f92939319cd2aa0deb85ef:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200636915/systems-engineer?team=SFTWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "b72bd726c0d161cd164b00bb2414c882", "title": "Power System Design and Integration Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Diego, United States of America", "country": "US", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 139500, "salary_max": 258100, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 139500, "base_salary_max": 258100, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-03-09T21:43:19.605Z", "apply_url": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 20, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "doctorate", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7b1e30e67a92a6d343", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b72bd726c0d161cd164b00bb2414c882:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.caca05ae09c1bcd12e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b72bd726c0d161cd164b00bb2414c882:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ed2d76aca653ed491d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b72bd726c0d161cd164b00bb2414c882:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.4ac850e15b8e669f95", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Power System Design and Integration Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:b72bd726c0d161cd164b00bb2414c882:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.00c7a2f10190c9d6e3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.75234b5d4e88377d2f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Power System Design and Integration Engineer San Diego, United States of America Imagine what you could do here. At Apple, new ideas have a way of becoming phenomenal products, services, and customer experiences very quickly. Bring passion and dedication to your job and there's no telling what you could accomplish. The success we are striving will be the result of very skilled people working in an environment which cultivates creativity, partnership, and thinking of old problems in new ways. We believe the future is Wireless! The mission of the Wireless Power Technology team: Create the world's best Wireless Charging user experience by inventing state-of-the-art technologies. We develop effortless and safe Wireless Charging designs that are central to Apple's products, the iPad, iPhone, Apple Watch, AirPods and more! New challenges arise every day that require the sharp problem-solving skills of individuals. Are you in for the challenges? We are looking for a power design engineer that leads the integration of the inductive technology into products in the partnership with multiple discipline teams including but not limited to architecture, FW, system EE, silicon, noise and vibration, safety, thermal, reliability, operations, regulatory teams and more. Join us. Pioneer best-in-class Wireless charging, for a new Wireless world. You will develop and design wireless power systems. You will be expected to maintain a high standard of analysis and manufacturing discipline while working with cross-functional teams to meet all specifications and requirements necessary to ship a product. You will collaborate closely with cross-functional partners to resolve", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.fc849075b97a1464c8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "b72bd726c0d161cd164b00bb2414c882", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Power System Design and Integration Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200649845/power-system-design-and-integration-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "57bdc0768d63948d5f0de7c9a35f08d7", "title": "Design For Test Engineer (Einfochips Inc)", "employer_name": "Arrow Financial CORP", "employer_slug": "arrow-financial", "location_text": "US-CA-Mountain View, California (Google)", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": true, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-31T00:00:00.000Z", "apply_url": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-03T05:42:19.741Z", "removed_at": null, "description_excerpt": "Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "field": "k401_match", "source": "llm:greenfield:inv_371_postfix", "db_column": "k401_match" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/717538/000071753826000037/arow-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "contractor_type": { "field": "contractor_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "contractor_type" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/717538/000071753826000037/arow-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "learning_budget_offered": { "field": "learning_budget_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "learning_budget_offered" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 11, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Finance", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8a7754b193cfe076fa", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:57bdc0768d63948d5f0de7c9a35f08d7:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b9777b4edb9e0c4ed1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:57bdc0768d63948d5f0de7c9a35f08d7:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fb71db0919bb100041", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:57bdc0768d63948d5f0de7c9a35f08d7:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.90af441adcfb231d15", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Title: \"inc\"", "tooltip": "Title matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Design For Test Engineer (Einfochips Inc)", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:57bdc0768d63948d5f0de7c9a35f08d7:title:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.b36314a17b0cd2fa16", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Design For Test Engineer (Einfochips Inc)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:57bdc0768d63948d5f0de7c9a35f08d7:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.73825ca4cc5921112e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Design For Test Engineer (Einfochips Inc) US-CA-Mountain View, California (Google) Position: Design For Test Engineer (Einfochips Inc) Job Description: Job Description What You'll Be Doing: DFT implementation for 3nm and 5nm Networking chips, IP DFT work RTL checks for scan-insertion compatibility using Synopsys Spyglass Scan-Insertion using Tessent TestKompress ATPG pattern generation: Compressed and Uncompressed Mode Tools: Mentor Tessent, Cadence Modus & Synopsys Tetramax Pattern Simulation: Without timing, With timing for different corners Tools: VCS Mismatch debug using Verdi Scripting with Perl, Shell, TCL: DAeRT - DFT flow enhancement/automation in project Makefile enhancement using extended scripts and targets for flow enhancement MBIST Insertion and Verification: MBIST Insertion and Verification done on block on top Silicon debug and bring-up done for block and top IEEE 1149.1 JTAG Insertion and verification What We Are Looking For : 5 - 7 Years of experience in DFT Scan-Insertion, ATPG, GLS, Pattern Simulations (with and w/o timing) MBIST Insertion and Verification Experience in IEEE 1149.1 JTAG Insertion and verification Scripting languages like Perl, Shell, TCL Worked on multi-million gate count SoCs in the area of Networking, Consumer, and various IPs like PLL, Serdes Tools: Mentor Tessent B. Tech, M.Tech in Microelectronics/Electronics Excellent communicator Low power DFT What's In It for You: At Arrow, we recognize that financial rewards and great benefits are important aspects of an ideal job. That's why we offer competitive financial compensation, including various compensation plans and a solid benefits package. Medical, Dental, Vision Insurance 401k, With Matching Contributions Short-Term/Long-Term Disability Insurance Health", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.afc1ea4a76e5eda135", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Title: \"inc\"", "tooltip": "Title contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design For Test Engineer (Einfochips Inc)", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c2adb422a9005554a4", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design For Test Engineer (Einfochips Inc)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.54241b7cf5e21c2c9d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "57bdc0768d63948d5f0de7c9a35f08d7", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_label": "Apply link", "source_date": "2026-08-03T05:42:19.741Z" } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": "2026-08-03T05:42:19.741Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-03T05:42:19.741Z", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/717538/000071753826000037/arow-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/717538/000071753826000037/arow-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "learning_budget_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-CA-Mountain-View-California-Google/Design-Verification-Engineer_R233497", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "7a4c46cb137b12aaa937d9580af1c99f", "title": "Senior Mechanical Design Engineer | Production Tooling", "employer_name": "BETA Technologies INC", "employer_slug": "beta-technologies", "location_text": "South Burlington, Vermont, United States", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 100000, "salary_max": 140000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "total_comp", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": null, "base_salary_max": null, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-04T16:41:40.000Z", "apply_url": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Mechanical Design Engineer | Production Tooling South Burlington, Vermont, United States At BETA Technologies, we apply our intellectual curiosity, passion for aviation, and commitment to sustainability toward a shared mission of revolutionizing electric aviation. Regardless of the position one holds, each team member brings their talent and desire to positively impact the environment and lives of others in a refreshing, vibrant, and inclusive culture. The Senior Mechanical Design Engineer is responsible for driving the development of innovative tooling, equipment, and processes for the manufacture of our eVTOL and eCTOL products. You will be expected to leverage your past industry experience and supplement with new knowledge gained through research and experimentation as you design, build, and validate tooling and equipment for our manufacturing processes. You will have CAD modeling and structural, thermal, and CFD analysis tools at your disposal to help you ensure that your designs are meeting or exceeding all design, safety, and regulatory requirements. You will be challenged every day and probably have a lot of fun. How you will contribute to revolutionizing electric aviation: Design tools, jigs, fixtures and machines to support manufacturing processes Develop solutions for efficiency, rate, quality, ergonomics, safety, or other target areas of improvement Evaluate existing manufacturing processes to enable optimization with improved tooling/equipment Work with the product design team to improve the design of parts and assemblies for manufacturability - datums, handling features, requirements, etc. Lead process ideation, creation and development efforts Support commissioning and validation of tooling and equipment Prototype and", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Transportation", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.86665ec8340ac690ae", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7a4c46cb137b12aaa937d9580af1c99f", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "BETA Technologies INC", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c1cefeba20e5d4543f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7a4c46cb137b12aaa937d9580af1c99f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Mechanical Design Engineer | Production Tooling", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.d05f9f83ba74afcedc", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7a4c46cb137b12aaa937d9580af1c99f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "data", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7a4c46cb137b12aaa937d9580af1c99f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": null }, "k401_match": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/betatechnologiesinc/jobs/4211339009", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "982f073461e2c8e2a6608891dda99542", "title": "Staff Electrical Design Engineer", "employer_name": "Lightmatter", "employer_slug": "lightmatter", "location_text": "Mountain View, CA", "country": "US", "employment_type": "contract", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 186000, "salary_max": 250000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 186000, "base_salary_max": 250000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-05-21T21:05:26.000Z", "apply_url": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 8, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "series_d", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4d0b26926247e5d52a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:982f073461e2c8e2a6608891dda99542:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6aa3d2dec9236af87a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:982f073461e2c8e2a6608891dda99542:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a7ab622a1a9be262c6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:982f073461e2c8e2a6608891dda99542:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.57f7c3d07680c37f16", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Staff Electrical Design Engineer", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:982f073461e2c8e2a6608891dda99542:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b9770d7a10506a75f0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e176ac8c0205b06c0b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Staff Electrical Design Engineer Mountain View, CA Lightmatter is leading the revolution in AI data center infrastructure, enabling the next giant leaps in human progress. The company invented the world's first 3D-stacked photonics engine, Passage™, capable of connecting thousands to millions of processors at the speed of light in extreme-scale data centers for the most advanced AI and HPC workloads. Lightmatter raised $400 million in its Series D round, reaching a valuation of $4.4 billion. We will continue to accelerate the development of data center photonics and grow every department at Lightmatter! If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders. Lightmatter is (re)inventing the future of computing with light! Staff Electrical Design Engineer About this Role We are looking for a Senior Electrical Design Engineer to contribute to the development of the next generation of silicon photonics based artificial intelligence accelerators and interconnect products. In this role, you will lead board and system solutions that leverage Lightmatter's technology to enable advanced machine learning, artificial intelligence, and large-scale interconnect platforms. You will lead and own HW systems efforts, collaborate closely with teams across hardware and software, including mechanical, packaging, and IC engineering, to design, integrate, troubleshoot and release system-level products at the leading edge of innovation. Responsibilities - Collaborate with the system architect and technical leads to define system-level hardware requirements and spec - Electrical design of power, memory, and interconnect", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.d37eda724f35ace96a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "982f073461e2c8e2a6608891dda99542", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Staff Electrical Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/lightmatter/jobs/5224869008?gh_jid=5224869008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "ffbb8756f25e23de9c3b94dc5cd7e783", "title": "Senior Electrical Engineer, Amazon Robotics", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "North Reading, Massachusetts, USA", "country": "US", "employment_type": "temporary", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 137300, "salary_max": 185700, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 137300, "base_salary_max": 185700, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": true, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2025-12-23T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "surrogacy_assistance_offered": { "field": "surrogacy_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "surrogacy_assistance_offered" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "contractor", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5739def21a94c66d83", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ffbb8756f25e23de9c3b94dc5cd7e783:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6dcd19e52e15eac8b1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ffbb8756f25e23de9c3b94dc5cd7e783:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f6b2a9a8dd943affa6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ffbb8756f25e23de9c3b94dc5cd7e783:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.05e3fc5f113e521637", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.16da7cefe951b946d3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.48d1aadebd1883e5b8", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Amazon Robotics North Reading, Massachusetts, USA Are you inspired by invention? Is problem solving through teamwork in your DNA? Do you like the idea of seeing how your work impacts the bigger picture? Answer yes to any of these and you'll fit right in here at Amazon Robotics. We are a smart team of doers that work passionately to apply pioneering advances in robotics and software to solve real-world problems that will transform our customers' experiences in ways we can't even imagine yet. We invent new improvements every day. We are Amazon Robotics and we will give you the tools and support you need to invent with us in ways that are rewarding, fulfilling and fun. Amazon Robotics is seeking a talented and motivated Senior Electrical Engineer to work on system design, implementation, and release to manufacturing for the next generation of industrial robotic systems and components. The ideal candidate will have extensive experience in vision sensors, optics, complex analog and digital circuit design, possess strong communication skills, have the ability to own a large component of a system and guide a team of Electrical Engineers. This candidate must have the ability to work well both independently and in team settings. This position reports directly to the Electrical Engineering Manager. Key job responsibilities - Working with an interdisciplinary team to execute product designs from concept to production including design, prototyping, validation, testing and certification - Leading and supporting a technical team on multiple projects in parallel -", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "surrogacy_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/3148640/senior-electrical-engineer-amazon-robotics", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "9e8770af1e49f3774050f2d79523cb71", "title": "Design Support Systems Engineer", "employer_name": "Viavi Solutions INC", "employer_slug": "viavi-solutions", "location_text": "5 Locations", "country": "unknown", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base_plus_commission", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Design Support Systems Engineer 5 Locations Summary: VIAVI (NASDAQ: VIAV) is a global provider of network test, monitoring and assurance solutions for telecommunications, cloud, enterprises, first responders, military, aerospace, and railway. VIAVI is also a leader in light management technologies for 3D sensing, anti-counterfeiting, consumer electronics, industrial, automotive, government and aerospace applications. We are the people behind the products that help keep the world connected at home, school, work, at play, and everywhere in between. VIAVI employees are passionate about supporting customer success and we welcome people who bring their best every day to the company - to question, to collaborate and to push for solutions that will delight our customers. VIAVI Solutions has an exciting opportunity for a Design Support/System Engineer in Morrisville, NC. Join our global DevOps and Common Tools Team within R&D, where you'll have direct impact on the development infrastructure supporting VIAVI's Assurance Product portfolio-solutions that ensure telecommunication networks worldwide operate at peak performance. In this role, you'll architect and manage cutting-edge DevSecOps toolchains, automate infrastructure workflows, and drive platform innovations that directly enhance developer productivity across our global engineering organization. Duties & Responsibilities: Key Responsibilities : Strategic Responsibilities Research and evaluate emerging DevOps tools, technologies, and best practices Manage R&D tools budget for Software Engineering and Network Engineering groups Define and implement comprehensive backup and disaster recovery strategies Drive process improvements and automation initiatives to enhance developer workflows Manage software licenses and track costs across the tools portfolio Tool Administration & Management Administer enterprise DevOps", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/912093/000091209325000096/viav-20250628.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/912093/000091209325000096/viav-20250628.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.c74a0b86c38e545880", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "9e8770af1e49f3774050f2d79523cb71", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Viavi Solutions INC", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.250f0eca4167fd18c7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "9e8770af1e49f3774050f2d79523cb71", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design Support Systems Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.e20520060cbce80462", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "9e8770af1e49f3774050f2d79523cb71", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design Support Systems Engineer", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.c415eb05ebb7c8a446", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "9e8770af1e49f3774050f2d79523cb71", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:9e8770af1e49f3774050f2d79523cb71:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.e2a8efc0364c2f08f3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "9e8770af1e49f3774050f2d79523cb71", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/912093/000091209325000096/viav-20250628.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/912093/000091209325000096/viav-20250628.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://viavisolutions.wd1.myworkdayjobs.com/careers/job/Home-Office-USA/Design-Support-Systems-Engineer_250004072-1", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "1d8095f577528b5a1fe7a692288ce6d8", "title": "Senior Analog Engineer (f/m/d)", "employer_name": "Renesas Electronics", "employer_slug": "renesas-electronics", "location_text": "Edinburgh, , United Kingdom", "country": "GB", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-10T03:52:15.000Z", "apply_url": "https://jobs.smartrecruiters.com/RenesasElectronics/744000129112571-senior-analog-engineer-f-m-d-", "apply_url_verified": false, "ats": "smartrecruiters", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0421d54828a27efdfe", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1d8095f577528b5a1fe7a692288ce6d8:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1b5d7085d8188a664d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1d8095f577528b5a1fe7a692288ce6d8:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a3773cd29a4fc38391", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1d8095f577528b5a1fe7a692288ce6d8:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f2af0091543b2883b7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1d8095f577528b5a1fe7a692288ce6d8:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.20594d884fdc945751", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4682306b697fd9bcf3", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.dc2ead920cc881b04f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1d8095f577528b5a1fe7a692288ce6d8", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Analog Engineer (f/m/d) Edinburgh, , United Kingdom Company Description: Job Description: Design and verify CMOS analog blocks for custom ASICs to meet performance, area, power and timescale constraints. Blocks include amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Take technical leadership for sub-systems and drive them from specification to production ramp. Collaborate with project leads to achieve system and design strategy for custom ASICs. Guide layout team to ensure quality of layout of own designs. Produce high quality documentation for designed circuits. Work closely with DFT engineers to ensure alignment to DFT strategy and implementation. Drive silicon debugging and design characterization. Support and participate in lab evaluation for own designs. Work with test and product engineers to support test development and ramp to production. Coach and mentor less experienced team members. Take a proactive approach to driving own development plan, utilizing team members and internal development opportunities. Qualifications: Degree level qualification in Electronics/Microelectronics Engineering or a related discipline is required 5-8 years of relevant analog circuit design experience. Hands-on experience in the design and verification of blocks such as amplifiers, oscillators, LDOs, comparators and reference/biasing circuits. Expertise in the design of filters and PLLs and/or RF circuits such as LNAs and mixers is an advantage. Experience of sub-system and chip-level verification including AMS verification. Strong competence with EDA design tools and the Cadence design environment. Ability to work with minimal instruction - either independently or collaboratively. Ability to make good judgement in selecting methods and techniques for obtaining solutions. Able", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000129112571-senior-analog-engineer-f-m-d-", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.smartrecruiters.com/RenesasElectronics/744000129112571-senior-analog-engineer-f-m-d-", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "23608718d9172df911b7892161cd5ada", "title": "Hardware Design Engineer(Einfochips Inc.)", "employer_name": "Arrow Electronics", "employer_slug": "arrow-electronics", "location_text": "Bedford, Massachusetts, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-02-02T00:00:00.000Z", "apply_url": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-MA-Bedford-Massachusetts-Werfen/Hardware-Design-Engineer-Einfochips-Inc-_R241108/apply", "apply_url_verified": false, "ats": "phenom_people", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Hardware Design Engineer(Einfochips Inc.) Bedford, Massachusetts, United States of America Embrace the role of a Hardware Design Engineer and drive innovation in hardware architecture for cutting-edge products. Collaborate with cross-functional teams, design and validate analog and mixed-signal circuits, and ensure compliance with industry standards. Grow your career with a global leader in semiconductor design and product engineering.", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/7536/000110465926012765/arw-20251231x10k.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/7536/000110465926012765/arw-20251231x10k.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.8ec3158cc8c1674b0c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "23608718d9172df911b7892161cd5ada", "signal_type": "query_match", "display_text": "Title: \"inc\"", "tooltip": "Title contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Hardware Design Engineer(Einfochips Inc.)", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.c7c203823dc7f78f35", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "23608718d9172df911b7892161cd5ada", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Hardware Design Engineer(Einfochips Inc.)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.ef6e09a8aba77cb6bf", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "23608718d9172df911b7892161cd5ada", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:23608718d9172df911b7892161cd5ada:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/7536/000110465926012765/arw-20251231x10k.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/7536/000110465926012765/arw-20251231x10k.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-MA-Bedford-Massachusetts-Werfen/Hardware-Design-Engineer-Einfochips-Inc-_R241108/apply", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://arrow.wd1.myworkdayjobs.com/AC/job/US-MA-Bedford-Massachusetts-Werfen/Hardware-Design-Engineer-Einfochips-Inc-_R241108/apply", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "e08dda8b604700b9cc805f913f3ea832", "title": "Senior Manager, Hardware Design Engineering CAD", "employer_name": "Celestica Inc.", "employer_slug": "celestica", "location_text": "City Austin | State/Province Texas | Country USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-12T10:25:24.000Z", "apply_url": "https://careers.celestica.com/job/Austin-Senior-Manager%2C-Hardware-Design-Engineering-CAD-TX-73301/1367519733/", "apply_url_verified": false, "ats": "successfactors", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Manager, Hardware Design Engineering CAD City Austin | State/Province Texas | Country USA Req ID: 132756 Region: Country USA State/Province: State/Province Texas City Austin Summary As the Senior Manager of Hardware Design Engineering (CAD), you will lead a specialized team within the Hardware Platform Solutions group to deliver high-performance networking, compute, and storage products for the rapidly expanding Connectivity and Cloud Solutions (CCS) market. Reporting to the Design Engineering Director, you will drive the strategic direction and execution of our CAD systems, overseeing everything from initial design layouts to NPI (New Product Introduction) and sustaining support for our global organization. You will act as a key technical liaison, interfacing with executive leadership, global design teams, and external customers to align CAD methodologies with broader business goals. By fostering a culture of excellence in design automation and data integrity, you will ensure our highly skilled hardware engineers have the tools and processes necessary to deliver robust, scalable, and market-leading technology solutions. Detailed Description Performs tasks such as, but not limited to, the following: Manage a team of CAD hardware engineers to and provide technical expertise throughout the design cycle Work with key component suppliers and eco-system partners to new business opportunities in Enterprise and Service Provider markets. Coordinate resources between competencies (engineering, manufacturing, Sourcing/SCM and other departments) to drive the implementation o", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1030894/000103089426000011/cls-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1030894/000103089426000011/cls-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9ff079260059232d73", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e08dda8b604700b9cc805f913f3ea832", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Manager, Hardware Design Engineering CAD City Austin | State/Province Texas | Country USA Req ID: 132756 Region: Country USA State/Province: State/Province Texas City Austin Summary As the Senior Manager of Hardware Design Engineering (CAD), you will lead a specialized team within the Hardware Platform Solutions group to deliver high-performance networking, compute, and storage products for the rapidly expanding Connectivity and Cloud Solutions (CCS) market. Reporting to the Design Engineering Director, you will drive the strategic direction and execution of our CAD systems, overseeing everything from initial design layouts to NPI (New Product Introduction) and sustaining support for our global organization. You will act as a key technical liaison, interfacing with executive leadership, global design teams, and external customers to align CAD methodologies with broader business goals. By fostering a culture of excellence in design automation and data integrity, you will ensure our highly skilled hardware engineers have the tools and processes necessary to deliver robust, scalable, and market-leading technology solutions. Detailed Description Performs tasks such as, but not limited to, the following: Manage a team of CAD hardware engineers to and provide technical expertise throughout the design cycle Work with key component suppliers and eco-system partners to new business opportunities in Enterprise and Service Provider markets. Coordinate resources between competencies (engineering, manufacturing, Sourcing/SCM and other departments) to drive the implementation o", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.a7e6dbbfb64e086936", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e08dda8b604700b9cc805f913f3ea832", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Celestica Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.9d53de88a4727bef95", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e08dda8b604700b9cc805f913f3ea832", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Senior Manager, Hardware Design Engineering CAD", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.10a38b3538bea1dcbf", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e08dda8b604700b9cc805f913f3ea832", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e08dda8b604700b9cc805f913f3ea832:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1030894/000103089426000011/cls-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1030894/000103089426000011/cls-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.celestica.com/job/Austin-Senior-Manager%2C-Hardware-Design-Engineering-CAD-TX-73301/1367519733/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.celestica.com/job/Austin-Senior-Manager%2C-Hardware-Design-Engineering-CAD-TX-73301/1367519733/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://careers.celestica.com/job/Austin-Senior-Manager%2C-Hardware-Design-Engineering-CAD-TX-73301/1367519733/", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "e182e4832295e8c2eafc0fcb9d1431c0", "title": "Design Criteria Engineer (Starshield)", "employer_name": "SpaceX", "employer_slug": "spacex", "location_text": "Hawthorne, CA", "country": "US", "employment_type": "internship", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 100000, "salary_max": 115000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 100000, "base_salary_max": 115000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn", "a16z", "sequoia", "foundersfund" ], "posted_at": "2026-04-03T00:32:43.000Z", "apply_url": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "field": "equity_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_type" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "weekend_work": { "field": "weekend_work", "source": "llm:greenfield:inv_371_postfix", "db_column": "weekend_work" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "security_clearance": { "field": "security_clearance", "source": "llm:greenfield:inv_371_postfix", "db_column": "security_clearance" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 1, "years_experience_max": 5, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": 10, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "top_secret", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.932cae3871a7373f8a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e182e4832295e8c2eafc0fcb9d1431c0:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b287d743a37f486704", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e182e4832295e8c2eafc0fcb9d1431c0:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.fa50e8d4ffe46121a0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e182e4832295e8c2eafc0fcb9d1431c0:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.role_function.51a1f3687869b2ae9b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Role: \"design\"", "tooltip": "Role matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e182e4832295e8c2eafc0fcb9d1431c0:role-function:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.f2bad4c7244062cb8e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Design Criteria Engineer (Starshield)", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e182e4832295e8c2eafc0fcb9d1431c0:title:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.5026d49f39ec8f6735", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.9eb1a8051e6c61882f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Design Criteria Engineer (Starshield) Hawthorne, CA SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars. DESIGN CRITERIA ENGINEER (STARSHIELD) Starshield leverages SpaceX's Starlink technology and launch capability to support national security efforts. While Starlink is designed for consumer and commercial use, Starshield is designed for government use, with an initial focus on earth observation, communications, and hosted payloads. On the Starshield Design Criteria Engineering team, you will ensure that our satellites achieve mission success with high reliability. This team draws from diverse engineering backgrounds to become deeply familiar with hardware from the vehicle system to individual components. These skills will be applied across the two roles we are hiring for: - As a design-focused member of this team, you will apply your technical expertise from initial conception of major design revisions and define the path through design maturation, validation, safe launch, and initial operation in orbit. This high-impact phase rewards creativity and innovation but demands foresight and mitigation of risks along the way. - As a change-focused member of this team, you will lead identifying and rolling out improvements to the design and processing of satellites, while sustaining our industry-leading design iteration and manufacturing cadence. You will be rewarded by seeing these systems acting in concert to materialize innovative ideas on real", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.6c28fe22021d6b4016", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e182e4832295e8c2eafc0fcb9d1431c0", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Design Criteria Engineer (Starshield)", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/spacex/jobs/8492189002?gh_jid=8492189002", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "58a33c3ac0aa55bf384260747f73fc5a", "title": "Mechanical / BIM Designer", "employer_name": "Armada Hoffler Pptys Inc", "employer_slug": "armada-hoffler-pptys", "location_text": "United States (Remote)", "country": "US", "employment_type": "unknown", "remote_status": "remote", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 0, "timezone_overlap_hours": 6, "salary_min": 70400, "salary_max": 88000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 70400, "base_salary_max": 88000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-05T17:57:57.000Z", "apply_url": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Mechanical / BIM Designer United States (Remote) About the Company Armada is the hyperscaler for the edge, delivering modular AI infrastructure from first deployment to AI factory with speed, scale and sovereignty. Named one of Fast Company's Most Innovative Companies and to the CNBC Disruptor 50, Armada's solutions are deployed in over 60 countries globally for organizations ranging from energy to defense. With nearly half a billion dollars in funding, Armada is backed by top investors such as Microsoft (M12), Founders Fund, and BlackRock, and has collaborations and partnerships including NVIDIA, Palantir and Dell Technologies. We are looking for the most brilliant minds in the world to join us. Working at Armada means taking ownership, driving autonomy, and delivering impact. You'll tackle challenges that haven't been solved before and help build something transformative from the ground up. What you do here will not only define your career but help further Armada's mission to bridge the digital divide for customers around the world. About the role We are seeking a Mechanical / BIM Designer with 3-5+ years of experience producing mechanical drawings in AutoCAD and Revit . This role is focused on drafting, model production, and drawing package development for modular infrastructure and data center projects. This is not intended to be a senior mechanical engineering role. The ideal candidate is strong in drafting execution, can work from engineering markups and design direction, and is able to turn concepts into clean, accurate, and organized drawing sets. The right person will be", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": true, "sabbatical_eligible": false, "family_friendly_score": 52, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "unlimited_pto": { "field": "unlimited_pto", "source": "llm:greenfield:inv_371_postfix", "db_column": "unlimited_pto" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.65c01a9ad87cb44808", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "58a33c3ac0aa55bf384260747f73fc5a", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "Armada Hoffler Pptys Inc", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.98940b5539a8767b10", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "58a33c3ac0aa55bf384260747f73fc5a", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Mechanical / BIM Designer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.e70064332d421acd26", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "58a33c3ac0aa55bf384260747f73fc5a", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:58a33c3ac0aa55bf384260747f73fc5a:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "unlimited_pto": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/armada/jobs/5194009008", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "1b08c8711b4fc798db50c08f69bda604", "title": "Senior Electrical Engineer", "employer_name": "Mach Industries", "employer_slug": "mach-industries", "location_text": "Huntington Beach, CA, Huntington Beach, California, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "CAD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-23T16:11:30.048Z", "apply_url": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Electrical Engineer Huntington Beach, CA, Huntington Beach, California, United States About Mach Industries Founded in 2022, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms . At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 220 employees , we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role As a Senior Electrical Engineer, you will be at the forefront of creating next-generation military technologies. Your expertise will directly contribute to the electrical design, development, and testing of sophisticated defense systems. This role is perfect for a driven individual who thrives in a fast-paced, high-stakes environment and is eager to apply their electrical engineering skills to high-impact projects. Key Responsibilities - Embedded Electronics Design: Design electronic circuit boards consisting of MCUs, low and high-speed communication busses such as USB, Ethernet, MIPI, digital and analog interfaces, power distribution, EMI, and ESD circuits. - Schematic and Layout PCB Design: Design PCB, Altium Designer preferred, for flight avionics, guidance systems, communication systems, and power distribution. - Rapid Prototype Design and Testing: Rapidly construct prototypes using standard and application specific lab tools. Test", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "growth-stage", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.2c0caff36ba19fcb5c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1b08c8711b4fc798db50c08f69bda604", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer Huntington Beach, CA, Huntington Beach, California, United States About Mach Industries Founded in 2022, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms . At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 220 employees , we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role As a Senior Electrical Engineer, you will be at the forefront of creating next-generation military technologies. Your expertise will directly contribute to the electrical design, development, and testing of sophisticated defense systems. This role is perfect for a driven individual who thrives in a fast-paced, high-stakes environment and is eager to apply their electrical engineering skills to high-impact projects. Key Responsibilities - Embedded Electronics Design: Design electronic circuit boards consisting of MCUs, low and high-speed communication busses such as USB, Ethernet, MIPI, digital and analog interfaces, power distribution, EMI, and ESD circuits. - Schematic and Layout PCB Design: Design PCB, Altium Designer preferred, for flight avionics, guidance systems, communication systems, and power distribution. - Rapid Prototype Design and Testing: Rapidly construct prototypes using standard and application specific lab tools. Test", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1b08c8711b4fc798db50c08f69bda604:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.84f70eef0f5a0f9006", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1b08c8711b4fc798db50c08f69bda604", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer Huntington Beach, CA, Huntington Beach, California, United States About Mach Industries Founded in 2022, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms . At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 220 employees , we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role As a Senior Electrical Engineer, you will be at the forefront of creating next-generation military technologies. Your expertise will directly contribute to the electrical design, development, and testing of sophisticated defense systems. This role is perfect for a driven individual who thrives in a fast-paced, high-stakes environment and is eager to apply their electrical engineering skills to high-impact projects. Key Responsibilities - Embedded Electronics Design: Design electronic circuit boards consisting of MCUs, low and high-speed communication busses such as USB, Ethernet, MIPI, digital and analog interfaces, power distribution, EMI, and ESD circuits. - Schematic and Layout PCB Design: Design PCB, Altium Designer preferred, for flight avionics, guidance systems, communication systems, and power distribution. - Rapid Prototype Design and Testing: Rapidly construct prototypes using standard and application specific lab tools. Test", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:1b08c8711b4fc798db50c08f69bda604:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.16a5c32d3dc33eec28", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1b08c8711b4fc798db50c08f69bda604", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer Huntington Beach, CA, Huntington Beach, California, United States About Mach Industries Founded in 2022, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms . At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 220 employees , we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role As a Senior Electrical Engineer, you will be at the forefront of creating next-generation military technologies. Your expertise will directly contribute to the electrical design, development, and testing of sophisticated defense systems. This role is perfect for a driven individual who thrives in a fast-paced, high-stakes environment and is eager to apply their electrical engineering skills to high-impact projects. Key Responsibilities - Embedded Electronics Design: Design electronic circuit boards consisting of MCUs, low and high-speed communication busses such as USB, Ethernet, MIPI, digital and analog interfaces, power distribution, EMI, and ESD circuits. - Schematic and Layout PCB Design: Design PCB, Altium Designer preferred, for flight avionics, guidance systems, communication systems, and power distribution. - Rapid Prototype Design and Testing: Rapidly construct prototypes using standard and application specific lab tools. Test", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c33f3d7a79f37d652b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "1b08c8711b4fc798db50c08f69bda604", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer Huntington Beach, CA, Huntington Beach, California, United States About Mach Industries Founded in 2022, Mach Industries is a rapidly growing defense technology company focused on developing next-generation autonomous defense platforms . At the core of our mission is the commitment to delivering scalable, decentralized defense systems that enhance the strategic capabilities of the United States and its allies. With a workforce of approximately 220 employees , we operate with startup agility and ambition. Our vision is to redefine the future of warfare through cutting-edge manufacturing, innovation at speed, and unwavering focus on national security. We are dedicated to solving the next generation of warfare with lethal systems that deter kinetic conflict and protect global security. The Role As a Senior Electrical Engineer, you will be at the forefront of creating next-generation military technologies. Your expertise will directly contribute to the electrical design, development, and testing of sophisticated defense systems. This role is perfect for a driven individual who thrives in a fast-paced, high-stakes environment and is eager to apply their electrical engineering skills to high-impact projects. Key Responsibilities - Embedded Electronics Design: Design electronic circuit boards consisting of MCUs, low and high-speed communication busses such as USB, Ethernet, MIPI, digital and analog interfaces, power distribution, EMI, and ESD circuits. - Schematic and Layout PCB Design: Design PCB, Altium Designer preferred, for flight avionics, guidance systems, communication systems, and power distribution. - Rapid Prototype Design and Testing: Rapidly construct prototypes using standard and application specific lab tools. Test", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/mach/2104c395-0f4c-4466-9e60-acd79f323f28", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "title": "SOC Top Level Physical Design Engineer, Annapurna Labs", "employer_name": "Amazon", "employer_slug": "amazon", "location_text": "Cupertino, California, USA", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 183000, "salary_max": 247600, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 183000, "base_salary_max": 247600, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": true, "childcare_subsidy": true, "fertility_family_building_benefits": true, "adoption_assistance_offered": true, "surrogacy_assistance_offered": true, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-11T00:00:00.000Z", "apply_url": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "apply_url_verified": false, "ats": "amazon_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SOC Top Level Physical Design Engineer, Annapurna Labs Cupertino, California, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities - Drive full chip floorplan, placement, integration, PV signoff and tapeout - Collaborate with FE team to understand RTL and drive physical aspects early in design cycle - Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification - Debug and resolve physical verification issues in collaboration with layout and design teams - Interface with foundries for MT", "parental_leave_weeks": 6, "non_birth_parent_leave_weeks": 6, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 56, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "childcare_subsidy": { "field": "childcare_subsidy", "source": "llm:greenfield:inv_371_postfix", "db_column": "childcare_subsidy" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" }, "parental_leave_weeks": { "field": "parental_leave_weeks", "source": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families", "db_column": "parental_leave_weeks", "source_url": "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" }, "mental_health_support": { "field": "mental_health_support", "source": "llm:greenfield:inv_371_postfix", "db_column": "mental_health_support" }, "adoption_assistance_offered": { "field": "adoption_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "adoption_assistance_offered" }, "non_birth_parent_leave_weeks": { "field": "non_birth_parent_leave_weeks", "source": "llm:greenfield:inv_371_postfix", "db_column": "non_birth_parent_leave_weeks" }, "surrogacy_assistance_offered": { "field": "surrogacy_assistance_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "surrogacy_assistance_offered" }, "fertility_family_building_benefits": { "field": "fertility_family_building_benefits", "source": "llm:greenfield:inv_371_postfix", "db_column": "fertility_family_building_benefits" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Industrial", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.43d7a3418b9948e9be", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SOC Top Level Physical Design Engineer, Annapurna Labs Cupertino, California, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities - Drive full chip floorplan, placement, integration, PV signoff and tapeout - Collaborate with FE team to understand RTL and drive physical aspects early in design cycle - Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification - Debug and resolve physical verification issues in collaboration with layout and design teams - Interface with foundries for MT", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c4e3c7074b15fbdf90", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SOC Top Level Physical Design Engineer, Annapurna Labs Cupertino, California, USA Annapurna Labs designs silicon and software that accelerates innovation. Customers choose us to create cloud solutions that solve challenges that were unimaginable a short time ago-even yesterday. Our custom chips, accelerators, and software stacks enable us to take on technical challenges that have never been seen before, and deliver results that help our customers change the world. Custom SoCs (System on Chip) live at the heart of AWS Machine Learning servers. As a member of the Cloud-Scale Machine Learning Acceleration team you'll be responsible for the design and optimization of hardware in our data centers including AWS Inferentia, Trainium Systems (our custom designed machine learning inference and training datacenter servers). Our success depends on our world-class server infrastructure; we're handling massive scale and rapid integration of emergent technologies. We're looking for an ASIC Physical Design Engineer to help us trail-blaze new technologies and architectures, while ensuring high design quality and making the right trade-offs. Key job responsibilities - Drive full chip floorplan, placement, integration, PV signoff and tapeout - Collaborate with FE team to understand RTL and drive physical aspects early in design cycle - Define, execute and optimize next-generation physical verification and integration methodologies using industry-standard EDA tools (FC, Calibre, IC Validator) - Perform DRC (Design Rule Checking), LVS (Layout vs. Schematic), PERC (Programmable Electrical Rule Check) verification - Debug and resolve physical verification issues in collaboration with layout and design teams - Interface with foundries for MT", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.a23e6242abe59c3095", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "SOC Top Level Physical Design Engineer, Annapurna Labs", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.dc98120e8af44b0295", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:2ad0ac4a1d1ec99c7b460a4cc405aaca:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": "Employer benefits source", "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1018724/000101872426000004/amzn-20251231.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "parental_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "https://www.aboutamazon.com/news/workplace/what-20-weeks-of-fully-paid-leave-does-for-Amazon-families" ], "checked_at": "2026-06-07T00:00:00Z" }, "non_birth_parent_leave_weeks": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "fertility_family_building_benefits": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "mental_health_support": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "adoption_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "childcare_subsidy": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" }, "surrogacy_assistance_offered": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.amazon.jobs/en/jobs/10416604/soc-top-level-physical-design-engineer-annapurna-labs", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-07T00:00:00Z" } } }, { "id": "e4ff60f1cd808040164024f0d64afa61", "title": "Electronics Hardware Engineer", "employer_name": "Ubiquiti", "employer_slug": "ubiquiti", "location_text": "Riga, Latvia", "country": "unknown", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": 3000, "salary_max": 5000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "EUR", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "month", "base_salary_min": 3000, "base_salary_max": 5000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-03-03T14:02:49.000Z", "apply_url": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Electronics Hardware Engineer Riga, Latvia About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role description: Ubiquiti Riga office is looking for an Electronics Hardware Engineer who shares our passion for innovation and technology and desire to do something extraordinary. You will participate in hardware design and hardware design audits/validations for UniFi products, like Ethernet Switches, Gateway routers, Access Points and Cameras with worldwide impact. Working closely with our R&D labs from different countries around the globe. We expect you to bring your experience, enthusiasm, and creativity wherever you go and put them into your work. You should think out of the box when finding solutions to new problems and make things work. Responsibilities: - Design and verify electronic PCBs (considering HW, SW, FW, ME, SI, thermal, and acoustic possible issues) ensuring they meet high standards of performance and reliability, and work closely with BSP and FW team to figure out issues and system bring up. - Be involved into product", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-07T00:00:00Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4785abe78634315c61", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e4ff60f1cd808040164024f0d64afa61", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Hardware Engineer Riga, Latvia About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role description: Ubiquiti Riga office is looking for an Electronics Hardware Engineer who shares our passion for innovation and technology and desire to do something extraordinary. You will participate in hardware design and hardware design audits/validations for UniFi products, like Ethernet Switches, Gateway routers, Access Points and Cameras with worldwide impact. Working closely with our R&D labs from different countries around the globe. We expect you to bring your experience, enthusiasm, and creativity wherever you go and put them into your work. You should think out of the box when finding solutions to new problems and make things work. Responsibilities: - Design and verify electronic PCBs (considering HW, SW, FW, ME, SI, thermal, and acoustic possible issues) ensuring they meet high standards of performance and reliability, and work closely with BSP and FW team to figure out issues and system bring up. - Be involved into product", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e4ff60f1cd808040164024f0d64afa61:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8f76d13e863d6223c5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e4ff60f1cd808040164024f0d64afa61", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Electronics Hardware Engineer Riga, Latvia About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role description: Ubiquiti Riga office is looking for an Electronics Hardware Engineer who shares our passion for innovation and technology and desire to do something extraordinary. You will participate in hardware design and hardware design audits/validations for UniFi products, like Ethernet Switches, Gateway routers, Access Points and Cameras with worldwide impact. Working closely with our R&D labs from different countries around the globe. We expect you to bring your experience, enthusiasm, and creativity wherever you go and put them into your work. You should think out of the box when finding solutions to new problems and make things work. Responsibilities: - Design and verify electronic PCBs (considering HW, SW, FW, ME, SI, thermal, and acoustic possible issues) ensuring they meet high standards of performance and reliability, and work closely with BSP and FW team to figure out issues and system bring up. - Be involved into product", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:e4ff60f1cd808040164024f0d64afa61:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d7a913d401fd0a0211", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e4ff60f1cd808040164024f0d64afa61", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electronics Hardware Engineer Riga, Latvia About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role description: Ubiquiti Riga office is looking for an Electronics Hardware Engineer who shares our passion for innovation and technology and desire to do something extraordinary. You will participate in hardware design and hardware design audits/validations for UniFi products, like Ethernet Switches, Gateway routers, Access Points and Cameras with worldwide impact. Working closely with our R&D labs from different countries around the globe. We expect you to bring your experience, enthusiasm, and creativity wherever you go and put them into your work. You should think out of the box when finding solutions to new problems and make things work. Responsibilities: - Design and verify electronic PCBs (considering HW, SW, FW, ME, SI, thermal, and acoustic possible issues) ensuring they meet high standards of performance and reliability, and work closely with BSP and FW team to figure out issues and system bring up. - Be involved into product", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e8e033a2e7016b2c47", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "e4ff60f1cd808040164024f0d64afa61", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Electronics Hardware Engineer Riga, Latvia About Ubiquiti At Ubiquiti Inc., we create technology platforms for Businesses, Smart Homes, and Internet Service Providers, driven by our goal to connect everyone, everywhere. To date, Ubiquiti has shipped over 100 million devices worldwide, from ISP networking products to next generation of IT solutions. Our growth is made possible by the dedicated team of hundreds behind the scenes. From software developers and product managers to designers and strategists, Team UI is driven to achieve our common goal: Rethinking IT. At Ubiquiti, you'll heighten your potential and broaden your horizons - all while shaping the future of connectivity. Role description: Ubiquiti Riga office is looking for an Electronics Hardware Engineer who shares our passion for innovation and technology and desire to do something extraordinary. You will participate in hardware design and hardware design audits/validations for UniFi products, like Ethernet Switches, Gateway routers, Access Points and Cameras with worldwide impact. Working closely with our R&D labs from different countries around the globe. We expect you to bring your experience, enthusiasm, and creativity wherever you go and put them into your work. You should think out of the box when finding solutions to new problems and make things work. Responsibilities: - Design and verify electronic PCBs (considering HW, SW, FW, ME, SI, thermal, and acoustic possible issues) ensuring they meet high standards of performance and reliability, and work closely with BSP and FW team to figure out issues and system bring up. - Be involved into product", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1511737/000151173725000053/ubnt-20250630.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-07T00:00:00Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/ubiquiti/jobs/4077630009", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "c014696f5bca3ed621323f30b43cc92d", "title": "HW board design Team Leader", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "San Jose, California, US", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 165000, "salary_max": 241400, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 165000, "base_salary_max": 241400, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "HW board design Team Leader San Jose, California, US The application window is expected to close on: 04/30/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . Meet the team: The Hardware Team Lead is responsible for leading the hardware development team through all phases of product design, from concept and architecture to production and support. This role combines strong technical expertise with leadership, planning, and cross-functional collaboration. Key Responsibilities: Lead and mentor the hardware engineering team Define hardware architecture and design strategy Oversee schematic design, PCB layout, and component selection Review designs for quality, reliability, cost, and manufacturability (DFM/DFT) Manage schedules, task prioritization, and resource allocation Work closely with FW, SW, mechanical, QA, and manufacturing teams Support prototype bring-up, debugging, and validation Drive design reviews, risk analysis, and technical decision-making Ensure compliance with relevant standards and regulations Minimum Qualifications: Bachelor's degree in Electrical Engineering with 7+ years of experience in hardware design and development. Prior experience with digital, analog, and power circuit design Prior experience with PCB design tools and review of complex layouts Prior experience with signal integrity, power integrity Hands-on experience with lab equipment (scope, logic analyzer, etc.) Preferred Experience: Prior experience supporting manufacturing and working with suppliers Why Cisco? At Cisco, we're revolutionizing how data and infrastructure connect and protect organizations in the AI era - and beyond. We've been innovating fearlessly for 40 years to create solutions that power how humans and technology", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 7, "years_experience_max": 11, "role_function": "design", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 50, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.58a268805c400bd780", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c014696f5bca3ed621323f30b43cc92d", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "HW board design Team Leader", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.7fda067e1375813d04", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c014696f5bca3ed621323f30b43cc92d", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "design", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:c014696f5bca3ed621323f30b43cc92d:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.05df0e665e2685507a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "c014696f5bca3ed621323f30b43cc92d", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/HW-board-design-Team-Leader_2005958", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "786d3df6553ca8b4948757a40b0936d2", "title": "Application Analyst Certified - EPIC Cadence", "employer_name": "Houston Methodist", "employer_slug": "houston-methodist", "location_text": "Corporate - Holly Hall", "country": "unknown", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-12T00:00:00.000Z", "apply_url": "https://houstonmethodist.wd12.myworkdayjobs.com/GTI/job/Corporate---Holly-Hall/Application-Analyst-Certified_JR-8141-2", "apply_url_verified": false, "ats": "workday", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Application Analyst Certified - EPIC Cadence Corporate - Holly Hall posted: Posted 30+ Days Ago", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "other", "role_function_source": "unknown", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": null, "quality_score": 35, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f657a572e6df4d131d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "786d3df6553ca8b4948757a40b0936d2", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Application Analyst Certified - EPIC Cadence Corporate - Holly Hall posted: Posted 30+ Days Ago", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:786d3df6553ca8b4948757a40b0936d2:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.7ce226ddcaed44a3c7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "786d3df6553ca8b4948757a40b0936d2", "signal_type": "query_match", "display_text": "Title: \"cadence\"", "tooltip": "Title matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "title", "source_value": "Application Analyst Certified - EPIC Cadence", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:786d3df6553ca8b4948757a40b0936d2:title:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.638abac56aa4a251e6", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "786d3df6553ca8b4948757a40b0936d2", "signal_type": "query_match", "display_text": "Title: \"cadence\"", "tooltip": "Title contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Application Analyst Certified - EPIC Cadence", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": null }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://houstonmethodist.wd12.myworkdayjobs.com/GTI/job/Corporate---Holly-Hall/Application-Analyst-Certified_JR-8141-2", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null } } }, { "id": "7fa1d757753f4efb49f141e26b626b4f", "title": "SoC Design Engineer", "employer_name": "Intel", "employer_slug": "intel", "location_text": "US, Texas, Austin", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-15T00:00:00.000Z", "apply_url": "https://intel.wd1.myworkdayjobs.com/External/job/US-Texas-Austin/SoC-Design-Engineer_JR0284059", "apply_url_verified": false, "ats": "workday", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SoC Design Engineer US, Texas, Austin posted: Posted 28 Days Ago", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/50863/000005086326000011/intc-20251227.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/50863/000005086326000011/intc-20251227.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "data", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "wikidata_sparql_industry", "employer_size": "5000+", "quality_score": 35, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.576db59a5712703655", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7fa1d757753f4efb49f141e26b626b4f", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "SoC Design Engineer", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.7e3e61370544df531b", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "7fa1d757753f4efb49f141e26b626b4f", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "data", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:7fa1d757753f4efb49f141e26b626b4f:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/50863/000005086326000011/intc-20251227.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/50863/000005086326000011/intc-20251227.htm" ], "checked_at": null }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://intel.wd1.myworkdayjobs.com/External/job/US-Texas-Austin/SoC-Design-Engineer_JR0284059", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://intel.wd1.myworkdayjobs.com/External/job/US-Texas-Austin/SoC-Design-Engineer_JR0284059", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - Wikidata", "source_label": "Wikidata", "href": null, "source_values": [ "wikidata_sparql_industry" ], "checked_at": null } } }, { "id": "5aa231a58b6328449379acf79557fa15", "title": "Chief of Staff - Marketing", "employer_name": "MongoDB, Inc.", "employer_slug": "mongodb", "location_text": "New York City; Palo Alto; San Francisco", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 140000, "salary_max": 275000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "total_comp", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 140000, "base_salary_max": 275000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-11T17:01:51.000Z", "apply_url": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Chief of Staff - Marketing New York City; Palo Alto; San Francisco The Chief of Staff to the Chief Marketing Officer (CMO) is a senior operator who oversees the operations of a 300+-person global marketing organization. You will design and own the operating system that enables MongoDB's marketing function to scale and move with speed, alignment, and discipline. You will represent the CMO across the org and resolve cross-functional friction without escalation. This role can be based out of our New York City, Palo Alto, or San Francisco office. What you will own - Operating system - design and run the operating cadence for the marketing organization. Marketing Leadership Team meetings, QBRs, offsites, board prep, and executive readouts, ensuring milestones and key deliverables are met. Decisions happen on schedule. Alignment is built in, not chased - Workback planning and risk management - for every major moment (board prep, earnings, QBRs, offsites, executive reviews), build the schedule working back to account for the milestones that ensure all stakeholders and owners are aligned on what needs to happen and when. You know when to surface risk early enough to allow for course correction - Leverage and representation - This role operates as an extension of the CMO in key settings. Attend leadership and cross-functional forums, provide direction, and make decisions with the core goals in mind; Close the loop on commitments across a complex matrixed environment - Cross-functional resolution - broker alignment between marketing functions and between marketing and the Sales, Product,", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": null, "llm_extraction_run_id": null, "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "rule", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 8, "years_experience_max": 12, "role_function": "marketing", "role_function_source": "rule", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "1001-5000", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.65b9f5b6bf5c3c89cf", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Chief of Staff - Marketing New York City; Palo Alto; San Francisco The Chief of Staff to the Chief Marketing Officer (CMO) is a senior operator who oversees the operations of a 300+-person global marketing organization. You will design and own the operating system that enables MongoDB's marketing function to scale and move with speed, alignment, and discipline. You will represent the CMO across the org and resolve cross-functional friction without escalation. This role can be based out of our New York City, Palo Alto, or San Francisco office. What you will own - Operating system - design and run the operating cadence for the marketing organization. Marketing Leadership Team meetings, QBRs, offsites, board prep, and executive readouts, ensuring milestones and key deliverables are met. Decisions happen on schedule. Alignment is built in, not chased - Workback planning and risk management - for every major moment (board prep, earnings, QBRs, offsites, executive reviews), build the schedule working back to account for the milestones that ensure all stakeholders and owners are aligned on what needs to happen and when. You know when to surface risk early enough to allow for course correction - Leverage and representation - This role operates as an extension of the CMO in key settings. Attend leadership and cross-functional forums, provide direction, and make decisions with the core goals in mind; Close the loop on commitments across a complex matrixed environment - Cross-functional resolution - broker alignment between marketing functions and between marketing and the Sales, Product,", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:5aa231a58b6328449379acf79557fa15:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.66e8a373a3c611bc0e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Chief of Staff - Marketing New York City; Palo Alto; San Francisco The Chief of Staff to the Chief Marketing Officer (CMO) is a senior operator who oversees the operations of a 300+-person global marketing organization. You will design and own the operating system that enables MongoDB's marketing function to scale and move with speed, alignment, and discipline. You will represent the CMO across the org and resolve cross-functional friction without escalation. This role can be based out of our New York City, Palo Alto, or San Francisco office. What you will own - Operating system - design and run the operating cadence for the marketing organization. Marketing Leadership Team meetings, QBRs, offsites, board prep, and executive readouts, ensuring milestones and key deliverables are met. Decisions happen on schedule. Alignment is built in, not chased - Workback planning and risk management - for every major moment (board prep, earnings, QBRs, offsites, executive reviews), build the schedule working back to account for the milestones that ensure all stakeholders and owners are aligned on what needs to happen and when. You know when to surface risk early enough to allow for course correction - Leverage and representation - This role operates as an extension of the CMO in key settings. Attend leadership and cross-functional forums, provide direction, and make decisions with the core goals in mind; Close the loop on commitments across a complex matrixed environment - Cross-functional resolution - broker alignment between marketing functions and between marketing and the Sales, Product,", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:5aa231a58b6328449379acf79557fa15:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.a3eefed0e3fb593e8d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "employer_name", "source_value": "MongoDB, Inc.", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:5aa231a58b6328449379acf79557fa15:employer:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.1742503da9e11679ed", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Chief of Staff - Marketing New York City; Palo Alto; San Francisco The Chief of Staff to the Chief Marketing Officer (CMO) is a senior operator who oversees the operations of a 300+-person global marketing organization. You will design and own the operating system that enables MongoDB's marketing function to scale and move with speed, alignment, and discipline. You will represent the CMO across the org and resolve cross-functional friction without escalation. This role can be based out of our New York City, Palo Alto, or San Francisco office. What you will own - Operating system - design and run the operating cadence for the marketing organization. Marketing Leadership Team meetings, QBRs, offsites, board prep, and executive readouts, ensuring milestones and key deliverables are met. Decisions happen on schedule. Alignment is built in, not chased - Workback planning and risk management - for every major moment (board prep, earnings, QBRs, offsites, executive reviews), build the schedule working back to account for the milestones that ensure all stakeholders and owners are aligned on what needs to happen and when. You know when to surface risk early enough to allow for course correction - Leverage and representation - This role operates as an extension of the CMO in key settings. Attend leadership and cross-functional forums, provide direction, and make decisions with the core goals in mind; Close the loop on commitments across a complex matrixed environment - Cross-functional resolution - broker alignment between marketing functions and between marketing and the Sales, Product,", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.50322d78515777eeca", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Chief of Staff - Marketing New York City; Palo Alto; San Francisco The Chief of Staff to the Chief Marketing Officer (CMO) is a senior operator who oversees the operations of a 300+-person global marketing organization. You will design and own the operating system that enables MongoDB's marketing function to scale and move with speed, alignment, and discipline. You will represent the CMO across the org and resolve cross-functional friction without escalation. This role can be based out of our New York City, Palo Alto, or San Francisco office. What you will own - Operating system - design and run the operating cadence for the marketing organization. Marketing Leadership Team meetings, QBRs, offsites, board prep, and executive readouts, ensuring milestones and key deliverables are met. Decisions happen on schedule. Alignment is built in, not chased - Workback planning and risk management - for every major moment (board prep, earnings, QBRs, offsites, executive reviews), build the schedule working back to account for the milestones that ensure all stakeholders and owners are aligned on what needs to happen and when. You know when to surface risk early enough to allow for course correction - Leverage and representation - This role operates as an extension of the CMO in key settings. Attend leadership and cross-functional forums, provide direction, and make decisions with the core goals in mind; Close the loop on commitments across a complex matrixed environment - Cross-functional resolution - broker alignment between marketing functions and between marketing and the Sales, Product,", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.employer_name.1707cee98feb3b2db1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5aa231a58b6328449379acf79557fa15", "signal_type": "query_match", "display_text": "Employer: \"inc\"", "tooltip": "Employer contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "employer_name", "source_value": "MongoDB, Inc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/1441816/000162828026016799/mdb-20260131.htm" ], "checked_at": null }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": null }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://www.mongodb.com/careers/job/?gh_jid=7997775", "source_values": [ "rule" ], "checked_at": null }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": null } } }, { "id": "3918dbf47b4a7e5c4c162728ff531c57", "title": "Hardware Systems Design Engineer - iPad", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-28T18:51:52.644Z", "apply_url": "https://jobs.apple.com/en-us/details/200660416/hardware-systems-design-engineer-ipad?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Hardware Systems Design Engineer - iPad Austin, United States of America The iPad Hardware Team in Austin, TX is looking for engineers who are motivated by the opportunity to take on big challenges. Apply your skills in electrical engineering, system integration, and collaboration with cross-functional teams to make design decisions that will benefit millions of iPad users worldwide! Our team of System Electrical Engineers own entire products from concept definition through shipping to customers. We sit at the center of Apple's wider engineering team, working collaboratively with mechanical engineering, software, silicon engineering and other module teams such as wireless, battery, camera, sensing, display, and factory test. Our team is collaborative, creative and passionate about what we do and the products we make. Come join us! This is a unique hardware design position that starts at product concept and continues all the way through to mass production.You will be at the center of iPad product development with a critical impact on overall design. Day to day tasks involve electrical design, simulation, bringup, debug, and validation for iPads. Routine responsibilities also include factory build support, and working with multi-functional technology teams in a fast-paced environment. There will be opportunities for international travel. Minimum Qualifications: Bachelors or Masters degree in Electrical / Computer Engineering or equivalent 3+ years of relevant industry experience designing consumer electronics and/or embedded systems; working with dynamic multi-functional teams Strong EE fundamentals (analog and digital design, signal/power integrity, etc) Comfortable in a lab environment using oscilloscopes, spectrum analyzers, etc.", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 40, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.18c52104ce48ca354c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3918dbf47b4a7e5c4c162728ff531c57", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Systems Design Engineer - iPad Austin, United States of America The iPad Hardware Team in Austin, TX is looking for engineers who are motivated by the opportunity to take on big challenges. Apply your skills in electrical engineering, system integration, and collaboration with cross-functional teams to make design decisions that will benefit millions of iPad users worldwide! Our team of System Electrical Engineers own entire products from concept definition through shipping to customers. We sit at the center of Apple's wider engineering team, working collaboratively with mechanical engineering, software, silicon engineering and other module teams such as wireless, battery, camera, sensing, display, and factory test. Our team is collaborative, creative and passionate about what we do and the products we make. Come join us! This is a unique hardware design position that starts at product concept and continues all the way through to mass production.You will be at the center of iPad product development with a critical impact on overall design. Day to day tasks involve electrical design, simulation, bringup, debug, and validation for iPads. Routine responsibilities also include factory build support, and working with multi-functional technology teams in a fast-paced environment. There will be opportunities for international travel. Minimum Qualifications: Bachelors or Masters degree in Electrical / Computer Engineering or equivalent 3+ years of relevant industry experience designing consumer electronics and/or embedded systems; working with dynamic multi-functional teams Strong EE fundamentals (analog and digital design, signal/power integrity, etc) Comfortable in a lab environment using oscilloscopes, spectrum analyzers, etc.", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.54a1aa33e42d86d223", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3918dbf47b4a7e5c4c162728ff531c57", "signal_type": "query_match", "display_text": "Title: \"design\"", "tooltip": "Title contains \"design\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Hardware Systems Design Engineer - iPad", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.title.ef28e9ecd838c74d28", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3918dbf47b4a7e5c4c162728ff531c57", "signal_type": "query_match", "display_text": "Title: \"systems\"", "tooltip": "Title contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "title", "source_value": "Hardware Systems Design Engineer - iPad", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.d2f6697f4141887a74", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "3918dbf47b4a7e5c4c162728ff531c57", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:3918dbf47b4a7e5c4c162728ff531c57:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200660416/hardware-systems-design-engineer-ipad?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200660416/hardware-systems-design-engineer-ipad?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200660416/hardware-systems-design-engineer-ipad?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "8eb87d93fb4076ed48eb2504a313089c", "title": "Analog Layout Automation Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "San Diego, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 163300, "salary_max": 290100, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 163300, "base_salary_max": 290100, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-04-20T22:06:00.526Z", "apply_url": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 10, "years_experience_max": 14, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.3840ab053351f1f690", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8eb87d93fb4076ed48eb2504a313089c:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.a5e821abc4172fd95f", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8eb87d93fb4076ed48eb2504a313089c:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.ce372ae7d034fc1481", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8eb87d93fb4076ed48eb2504a313089c:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.539c3058919d278734", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.e70b99e6dfb9d1d988", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f20266fd215b60ed95", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8eb87d93fb4076ed48eb2504a313089c", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Analog Layout Automation Engineer San Diego, United States of America Join Apple's Silicon Engineering Group (SEG) and be at the forefront of shaping the next generation of Apple's systems-on-chip (SOCs)! Our SOCs, featuring multi-billion transistors, are the heart of iconic devices like iPhones, iPads, and Macs. We're seeking a highly skilled Analog Layout Automation Engineer to contribute to the evolution of Analog/Mixed-Signal (AMS) circuits, covering SerDes, PLLs, and sensors, with a focus on automation and leveraging AI/ML techniques for improved design and efficiency. As an Analog Layout Automation Engineer, you'll convert design concepts into silicon by collaborating with circuit designers and using advanced, including AI-powered, CAD tools to create high-performance analog and mixed-signal layouts. You will review floor plans, analyze circuits, run verification suites, and resolve LVS/DRC/ERC issues to deliver next-generation SOCs. You'll also drive automation by developing scripts, improving workflows, and applying AI/ML for layout optimization, verification acceleration, advanced modeling, intelligent quality metrics, reduced manual effort, and data-driven design insights. Minimum Qualifications: BS degree in technical discipline with minimum 10 years of relevant experience. Preferred Qualifications: Experience designing analog and mixed-signal layouts in deep-submicron CMOS and FinFET technologies. Strong programming/scripting skills in SKILL, Perl, TCL, Shell, and/or Python, with emphasis on layout automation, productivity tooling, and data analysis. Solid understanding of supervised and self-supervised learning, convolutional neural networks (CNNs), and core training concepts such as loss functions, backpropagation, and optimization. Hands-on experience with PyTorch for model development and experimentation. Demonstrated ability to automate layout tasks, flows, and quality checks", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200658213/analog-layout-automation-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "8f8f8199a492a513db8e2b80199ab828", "title": "Senior Electrical Engineer, Generalist", "employer_name": "Anduril", "employer_slug": "anduril", "location_text": "Costa Mesa, California, United States", "country": "US", "employment_type": "full_time", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 146000, "salary_max": 194000, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "total_comp", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 146000, "base_salary_max": 194000, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "options" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cnbc_disruptor50", "cbinsights_unicorn", "a16z", "foundersfund", "generalcatalyst" ], "posted_at": "2026-06-10T18:21:34.000Z", "apply_url": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Senior Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop &", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 47, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "field": "equity_included", "source": "derived:greenfield:inv_371_postfix", "db_column": "equity_included" }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "security_clearance": { "field": "security_clearance", "source": "llm:greenfield:inv_371_postfix", "db_column": "security_clearance" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "senior", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 9, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "top_secret", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.b305d0d22ea3402d30", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8f8f8199a492a513db8e2b80199ab828", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop &", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8f8f8199a492a513db8e2b80199ab828:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.de544f248df1109be5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8f8f8199a492a513db8e2b80199ab828", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop &", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:8f8f8199a492a513db8e2b80199ab828:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.71297fe90d7db8c5b7", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8f8f8199a492a513db8e2b80199ab828", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop &", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.7768aae83624f315c5", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "8f8f8199a492a513db8e2b80199ab828", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Senior Electrical Engineer, Generalist Costa Mesa, California, United States Anduril Industries is a defense technology company with a mission to transform U.S. and allied military capabilities with advanced technology. By bringing the expertise, technology, and business model of the 21st century's most innovative companies to the defense industry, Anduril is changing how military systems are designed, built and sold. Anduril's family of systems is powered by Lattice OS, an AI-powered operating system that turns thousands of data streams into a realtime, 3D command and control center. As the world enters an era of strategic competition, Anduril is committed to bringing cutting-edge autonomy, AI, computer vision, sensor fusion, and networking technology to the military in months, not years. ABOUT THE JOB At Anduril, our Electrical Engineers are at the forefront of defense technology, crafting high-impact, cutting-edge hardware solutions that redefine innovation. You'll dive into a diverse range of projects, partnering with brilliant minds across disciplines to engineer robust electrical systems and architectures that empower our mission-critical operations. We're seeking talented Electrical Engineering Generalists on several teams, leveraging their broad expertise in PCB/CCA/PCBA design, to contribute to projects that are shaping the future of defense. WHAT YOU'LL DO - Lead Full-Lifecycle PCB/CCA/PCBA Design: Drive board-level designs from architectural definition, component selection, and schematic capture through layout, fabrication, and integration for mission-critical hardware. - Validate & Debug Complex Systems: Perform rigorous simulations (e.g., SI/PI, thermal), hands-on prototyping, and comprehensive debugging of new hardware designs at the board and system level. - Develop &", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "derived:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://boards.greenhouse.io/andurilindustries/jobs/5067195007?gh_jid=5067195007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "ac23146aa64a2151e09c7fb0842dc431", "title": "Staff Engineer, SoC RTL Engineer", "employer_name": "TensTorrent", "employer_slug": "tenstorrent", "location_text": "Tokyo, Japan", "country": "JP", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 3, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "UNSPECIFIED", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "cbinsights_unicorn" ], "posted_at": "2026-04-21T05:52:32.000Z", "apply_url": "https://job-boards.greenhouse.io/tenstorrent/jobs/5108816007", "apply_url_verified": false, "ats": "greenhouse", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Staff Engineer, SoC RTL Engineer Tokyo, Japan Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design. This role is hybrid, based out of Tokyo. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - A digital design expert with a deep understanding of computer architecture and IP microarchitecture. - Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows. - Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals. - A naturally collaborative and technical engineer - you thrive in spec definition, peer reviews, and team-wide planning. - Strong synthesis", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "staff_plus", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.eab278fcfa5860c899", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac23146aa64a2151e09c7fb0842dc431", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Staff Engineer, SoC RTL Engineer Tokyo, Japan Tenstorrent is leading the industry on cutting-edge AI technology, revolutionizing performance expectations, ease of use, and cost efficiency. With AI redefining the computing paradigm, solutions must evolve to unify innovations in software models, compilers, platforms, networking, and semiconductors. Our diverse team of technologists have developed a high performance RISC-V CPU from scratch, and share a passion for AI and a deep desire to build the best AI platform possible. We value collaboration, curiosity, and a commitment to solving hard problems. We are growing our team and looking for contributors of all seniorities. We are looking for a Staff Digital Design Engineer to help define, build, and optimize high-performance chiplet based SoC architectures. This role is ideal for engineers who thrive at the intersection of microarchitecture, RTL implementation, and performance and power aware design. This role is hybrid, based out of Tokyo. We welcome candidates at various experience levels for this role. During the interview process, candidates will be assessed for the appropriate level, and offers will align with that level, which may differ from the one in this posting. Who You Are - A digital design expert with a deep understanding of computer architecture and IP microarchitecture. - Skilled in RTL development (Verilog/VHDL) and familiar with full ASIC flows. - Comfortable optimizing for power, performance, and area (PPA) under aggressive design goals. - A naturally collaborative and technical engineer - you thrive in spec definition, peer reviews, and team-wide planning. - Strong synthesis", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.c84922339da2490ac1", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "ac23146aa64a2151e09c7fb0842dc431", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:ac23146aa64a2151e09c7fb0842dc431:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5108816007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5108816007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://job-boards.greenhouse.io/tenstorrent/jobs/5108816007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "5ad6642a87fc4a8d03196324c5fc4a9d", "title": "Hardware Engineer (High-speed IO/Testing) (Onsite)", "employer_name": "Cisco", "employer_slug": "cisco", "location_text": "San Jose, California, US", "country": "US", "employment_type": "full_time", "remote_status": "onsite", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": 5, "timezone_overlap_hours": 6, "salary_min": 152400, "salary_max": 221800, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 152400, "base_salary_max": 221800, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp", "profit_share" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": true, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-06-08T00:00:00.000Z", "apply_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "apply_url_verified": true, "ats": "workday", "url_last_checked_alive": "2026-08-10T03:54:55.257Z", "removed_at": null, "description_excerpt": "Hardware Engineer (High-speed IO/Testing) (Onsite) San Jose, California, US The application window is expected to close on: 06/26/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you commute to the San Jose, CA office 5 days a week. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches through web-scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry. Your Impact In this role, you will be developing cutting-edge next-generation high-speed interconnect for deployment in data centers around the world. You will lead the activities of supporting internal and external customers with all requests related to Silicon One high-speed interfaces, including the development of new features and bug fixes. Other responsibilities include: Develop and execute electrical characterization testing for high-speed interconnect devices Support characterization, validation, compliance, and system integration of Silicon One devices Work with", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "base_salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "bonus_offered": { "field": "bonus_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "bonus_offered" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "remote_status": { "field": "remote_status", "source": "rule:remote_status", "db_column": "remote_status" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "salary_period": { "field": "salary_period", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_period" }, "days_in_office": { "field": "days_in_office", "source": "rule:remote_status", "db_column": "days_in_office" }, "equity_offered": { "field": "equity_offered", "source": "llm:greenfield:inv_371_postfix", "db_column": "equity_offered" }, "employment_type": { "field": "employment_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "employment_type" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "salary_currency": { "field": "salary_currency", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_currency" }, "salary_disclosed": { "field": "salary_disclosed", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_disclosed" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" }, "visible_salary_max": { "field": "visible_salary_max", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_max" }, "visible_salary_min": { "field": "visible_salary_min", "source": "derived:greenfield:inv_371_postfix", "db_column": "salary_min" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 5, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": 50, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.0574e9e41904f13a58", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5ad6642a87fc4a8d03196324c5fc4a9d", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Engineer (High-speed IO/Testing) (Onsite) San Jose, California, US The application window is expected to close on: 06/26/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you commute to the San Jose, CA office 5 days a week. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches through web-scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry. Your Impact In this role, you will be developing cutting-edge next-generation high-speed interconnect for deployment in data centers around the world. You will lead the activities of supporting internal and external customers with all requests related to Silicon One high-speed interfaces, including the development of new features and bug fixes. Other responsibilities include: Develop and execute electrical characterization testing for high-speed interconnect devices Support characterization, validation, compliance, and system integration of Silicon One devices Work with", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.c1792215c45812b2da", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5ad6642a87fc4a8d03196324c5fc4a9d", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description contains \"inc\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Hardware Engineer (High-speed IO/Testing) (Onsite) San Jose, California, US The application window is expected to close on: 06/26/2026 Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received . This position requires that you commute to the San Jose, CA office 5 days a week. Meet the Team The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. We design the networking hardware for Enterprises and Service Providers of various sizes, the Public Sector, and Non-Profit Organizations across the world. Cisco Silicon One is the only unifying silicon architecture in the market that enables customers to deploy the best-of-breed silicon from Top of Rack (TOR) switches through web-scale data centers and across service providers, enterprise networks, and data centers with a fully unified routing and switching portfolio. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing, and testing some of the most complex ASICs being developed in the industry. Your Impact In this role, you will be developing cutting-edge next-generation high-speed interconnect for deployment in data centers around the world. You will lead the activities of supporting internal and external customers with all requests related to Silicon One high-speed interfaces, including the development of new features and bug fixes. Other responsibilities include: Develop and execute electrical characterization testing for high-speed interconnect devices Support characterization, validation, compliance, and system integration of Silicon One devices Work with", "matched_input": "inc", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.cf981050977c2ed29a", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5ad6642a87fc4a8d03196324c5fc4a9d", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:5ad6642a87fc4a8d03196324c5fc4a9d:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.trust.apply.ab7481e72b9f7cbf7d", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "5ad6642a87fc4a8d03196324c5fc4a9d", "signal_type": "trust_signal", "display_text": "Apply link reachable when checked", "tooltip": "The apply URL was reachable during the last recorded crawl-time liveness check; this is not a live guarantee.", "source_binding": "row_trust_evidence", "source_field": "apply_url_verified", "source_value": true, "matched_input": true, "derivation_source": "verified_source_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "trust_source_exists", "counts_for_non_trivial_query": false, "truth_verified": true, "exact": true, "priority": 10, "mobile_priority": 11, "ui": { "icon": "ExternalLink", "tone": "verified", "href": null }, "evidence_source": { "source_url": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_label": "Apply link", "source_date": "2026-08-10T03:54:55.257Z" } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": "2026-08-10T03:54:55.257Z", "apply_url_verification_status": "reachable_when_last_checked", "apply_url_verification_label": "Reachable when checked at 2026-08-10T03:54:55.257Z", "field_source_signals": { "remote_status": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "rule:remote_status" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/858877/000085887725000111/csco-20250726.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://cisco.wd5.myworkdayjobs.com/Cisco_Careers/job/San-Jose-California-US/Hardware-Engineer_2008444", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "a49c4d072dd53639931e1c25d72fe036", "title": "SoC Performance Analysis Engineer", "employer_name": "Apple", "employer_slug": "apple", "location_text": "Austin, United States of America", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": 126800, "salary_max": 190900, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "base", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": "year", "base_salary_min": 126800, "base_salary_max": 190900, "salary_disclosed": true, "equity_included": true, "equity_included_source": null, "equity_type": [ "rsu", "options", "espp" ], "k401_match": "yes", "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "k401_contribution_source_url": null, "k401_contribution_source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [], "posted_at": "2026-05-22T16:32:00.243Z", "apply_url": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "apply_url_verified": false, "ats": "apple_custom", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "SoC Performance Analysis Engineer Austin, United States of America Does making the next extraordinary technology product excite you? Imagine what you could do here! At Apple, our new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team thereʼs no telling what you could accomplish. The SoC Performance Verification is a critical job within Appleʼs Hardware Technology. Joining this group means you will be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices. Work closely with Architecture to understand performance goals of the design. Correlate RTL performance against model performance. Perform deep performance analysis in the design and report findings. Identify performance bottlenecks and coordinate with Design and Architecture teams to improve performance. Define performance statistics to help performance debug and standard methodologies to improve performance correlation effort. Have strong interpersonal skills, work independently & lead work you're doing to align with the project goals plus support multi-functional engineering efforts. Minimum Qualifications: Bachelors degree + 0 years of industry experience Preferred Qualifications: You are well-rounded in performance correlation and analysis and are an extraordinary teammate with excellent social skills. You have the desire to solve diverse challenges. Sophisticated knowledge of CPU & SOC architecture/design Familiarity with verification environments and Verilog, C/C++. Experience with SystemVerilog, Verilog and scripting in", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 44, "benefit_verified": true, "benefit_last_verified": "2026-06-13T01:18:42.546Z", "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "years_min": { "field": "years_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "years_experience_min" }, "k401_match": { "source": "dol_form_5500", "source_url": null, "source_fields": [ "EMPLR_CONTRIB_INCOME_AMT" ], "source_label": "DOL Form 5500 filing" }, "salary_max": { "field": "salary_max", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_max" }, "salary_min": { "field": "salary_min", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_min" }, "tech_stack": { "field": "tech_stack", "source": "llm:greenfield:inv_371_postfix", "db_column": "tech_stack" }, "equity_type": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "company_stage": { "field": "company_stage", "source": "llm:greenfield:inv_371_postfix", "db_column": "company_stage" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "equity_included": { "source": "sec_10k", "source_url": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_fields": [ "equity_offered", "equity_type" ] }, "visa_sponsorship": { "field": "visa_sponsorship", "source": "llm:greenfield:inv_371_postfix", "db_column": "visa_sponsorship" }, "industry_vertical": { "field": "industry_vertical", "source": "llm:greenfield:inv_371_postfix", "db_column": "industry_vertical" }, "naics_sector_code": { "field": "naics_sector_code", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_code" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" }, "naics_sector_title": { "field": "naics_sector_title", "source": "llm:greenfield:inv_371_postfix", "db_column": "naics_sector_title" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 0, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": "public-company", "company_stage_source": "llm:greenfield:inv_371_postfix", "employer_industry": "Technology", "employer_industry_source": "source_sector", "employer_size": "5000+", "quality_score": 55, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": true, "us_citizenship_required": false, "security_clearance": "none", "education_required": "bachelors", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.74b5206434968f9a91", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a49c4d072dd53639931e1c25d72fe036", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "SoC Performance Analysis Engineer Austin, United States of America Does making the next extraordinary technology product excite you? Imagine what you could do here! At Apple, our new insights have a way of becoming extraordinary products, services, and customer experiences very quickly. We bring passion and dedication to our job and when you are a part of our team thereʼs no telling what you could accomplish. The SoC Performance Verification is a critical job within Appleʼs Hardware Technology. Joining this group means you will be responsible for crafting and building the technology that fuels Appleʼs devices. Together, you and your team will enable our customers to do all the things they love with their devices. Work closely with Architecture to understand performance goals of the design. Correlate RTL performance against model performance. Perform deep performance analysis in the design and report findings. Identify performance bottlenecks and coordinate with Design and Architecture teams to improve performance. Define performance statistics to help performance debug and standard methodologies to improve performance correlation effort. Have strong interpersonal skills, work independently & lead work you're doing to align with the project goals plus support multi-functional engineering efforts. Minimum Qualifications: Bachelors degree + 0 years of industry experience Preferred Qualifications: You are well-rounded in performance correlation and analysis and are an extraordinary teammate with excellent social skills. You have the desire to solve diverse challenges. Sophisticated knowledge of CPU & SOC architecture/design Familiarity with verification environments and Verilog, C/C++. Experience with SystemVerilog, Verilog and scripting in", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.semantic.role_function.d28a6b111cfb104e40", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "a49c4d072dd53639931e1c25d72fe036", "signal_type": "query_match", "display_text": "Role: semantic match", "tooltip": "Role provided semantic evidence for your search intent.", "source_binding": "vector_semantic_evidence", "source_field": "role_function", "source_value": "engineering", "matched_input": "cadence design systems inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:a49c4d072dd53639931e1c25d72fe036:vector", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": false, "priority": 74, "mobile_priority": 2, "ui": { "icon": "Sparkles", "tone": "match", "href": null } } ], "source_label": "DOL Form 5500 filing", "parental_leave_source_label": null, "k401_match_source_label": "DOL Form 5500 filing", "k401_contribution_source_label": "DOL Form 5500 filing", "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "salary_min": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_max": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "salary_type": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "equity_included": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm", "source_values": [ "sec_10k", "https://www.sec.gov/Archives/edgar/data/320193/000032019325000079/aapl-20250927.htm" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "k401_match": { "tier": "government", "verified": true, "label": "Verified - DOL Form 5500", "source_label": "DOL Form 5500", "href": null, "source_values": [ "dol_form_5500", "EMPLR_CONTRIB_INCOME_AMT" ], "checked_at": "2026-06-13T01:18:42.546Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "company_stage": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.apple.com/en-us/details/200664332/soc-performance-analysis-engineer?team=HRDWR", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "employer_industry": { "tier": "government", "verified": true, "label": "Verified - SEC 10-K", "source_label": "SEC 10-K", "href": null, "source_values": [ "source_sector" ], "checked_at": "2026-06-20T05:42:05.724Z" } } }, { "id": "0df1e0bdcf52ee53ad233ddac23a1022", "title": "Product Engineer", "employer_name": "Swerve", "employer_slug": "swerve", "location_text": "Sapien HQ — NYC, New York, United States", "country": "US", "employment_type": "unknown", "remote_status": "unspecified", "remote_status_source": null, "remote_status_enriched_at": null, "days_in_office": null, "timezone_overlap_hours": 6, "salary_min": null, "salary_max": null, "salary_min_source": null, "salary_max_source": null, "salary_currency": "USD", "salary_type": "unknown", "salary_type_source": null, "salary_type_enriched_at": null, "salary_period": null, "base_salary_min": null, "base_salary_max": null, "salary_disclosed": false, "equity_included": false, "equity_included_source": null, "equity_type": [ "none" ], "k401_match": null, "match_401k_pct": null, "match_401k_pct_source": null, "k401_match_source_url": null, "k401_match_source_fields": [], "k401_contribution_source_url": null, "k401_contribution_source_fields": [], "profit_sharing": false, "bonus_offered": false, "mental_health_support": null, "childcare_subsidy": null, "fertility_family_building_benefits": null, "adoption_assistance_offered": null, "surrogacy_assistance_offered": null, "student_loan_repayment_offered": null, "learning_budget_offered": null, "relocation_assistance": null, "top_startup_sources": [ "yc" ], "posted_at": "2026-02-04T20:22:55.936Z", "apply_url": "https://jobs.ashbyhq.com/sapien/e1a51be9-6d18-468f-9aed-6d58a6481007", "apply_url_verified": false, "ats": "ashby", "url_last_checked_alive": null, "removed_at": null, "description_excerpt": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "parental_leave_weeks": null, "non_birth_parent_leave_weeks": null, "parental_leave_weeks_source": null, "non_birth_parent_leave_weeks_source": null, "parental_leave_source_url": null, "pto_days": null, "unlimited_pto": false, "sabbatical_eligible": false, "family_friendly_score": 43, "benefit_verified": false, "benefit_last_verified": null, "hire_states_allowed": [], "state_eligibility_source": null, "state_eligibility_enriched_at": null, "llm_quality_pass_at": null, "llm_signals_at": "2026-06-20T05:42:05.724Z", "llm_extraction_run_id": "postfix_final_004037", "llm_extraction_extracted_at": null, "llm_extraction_field_sources": { "seniority": { "field": "seniority", "source": "llm:greenfield:inv_371_postfix", "db_column": "seniority" }, "role_family": { "field": "role_family", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_family" }, "salary_type": { "field": "salary_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "salary_type" }, "customer_type": { "field": "customer_type", "source": "llm:greenfield:inv_371_postfix", "db_column": "customer_type" }, "role_function": { "field": "role_function", "source": "llm:greenfield:inv_371_postfix", "db_column": "role_function" }, "education_required": { "field": "education_required", "source": "llm:greenfield:inv_371_postfix", "db_column": "education_required" } }, "seniority": "mid", "seniority_source": "llm:greenfield:inv_371_postfix", "years_experience_min": 3, "years_experience_max": 7, "role_function": "engineering", "role_function_source": "llm:greenfield:inv_371_postfix", "company_stage": null, "company_stage_source": null, "employer_industry": null, "employer_industry_source": null, "employer_size": "51-200", "quality_score": 45, "travel_pct": null, "requires_shift": null, "shift_type": "unknown", "shift_type_source": null, "weekend_work": "unknown", "weekend_work_source": null, "relocation_assistance_source": null, "contractor_w2": "unknown", "required_timezone": null, "fertility_family_building_benefits_source": null, "mental_health_support_source": null, "adoption_assistance_offered_source": null, "childcare_subsidy_source": null, "learning_budget_offered_source": null, "surrogacy_assistance_offered_source": null, "cover_letter_required": null, "cover_letter_required_source": null, "assessment_required": null, "assessment_required_source": null, "application_deadline": null, "application_deadline_source": null, "visa_sponsorship": false, "us_citizenship_required": false, "security_clearance": "none", "education_required": "none", "roll_up_count": null, "roll_up_total_locations": null, "explanations": [ { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.520548702dfeea18cd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description matched \"systems\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "systems", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0df1e0bdcf52ee53ad233ddac23a1022:description:systems", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.6337dcbc1dd367270c", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description matched \"cadence\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "cadence", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0df1e0bdcf52ee53ad233ddac23a1022:description:cadence", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.8cf26ffd3d34834afd", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"inc\"", "tooltip": "Description matched \"inc\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "inc", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0df1e0bdcf52ee53ad233ddac23a1022:description:inc", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.d997e88ff8bf449471", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description matched \"design\" from your search.", "source_binding": "bm25_field_evidence", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "design", "derivation_source": "candidate_result.raw_match_evidence", "candidate_evidence_id": "ev:gq_a0e3b4dfe5b7502c1f21:0df1e0bdcf52ee53ad233ddac23a1022:description:design", "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "candidate_evidence_exists", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 90, "mobile_priority": 1, "ui": { "icon": "Search", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.183de95f848275c703", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"systems\"", "tooltip": "Description contains \"systems\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "systems", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.4fdaac5604af0b7e7e", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"cadence\"", "tooltip": "Description contains \"cadence\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "cadence", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } }, { "schema_version": "inv382.match_signal.v1", "signal_id": "sig.query.description_excerpt.f50156d407e8d00bb0", "query_id": "gq_a0e3b4dfe5b7502c1f21", "job_id": "0df1e0bdcf52ee53ad233ddac23a1022", "signal_type": "query_match", "display_text": "Description: \"design\"", "tooltip": "Description contains \"design\" from your search.", "source_binding": "token_match", "source_field": "description_excerpt", "source_value": "Product Engineer Sapien HQ — NYC, New York, United States Who we are Sapien is rethinking how finance teams operate in the age of AI. We're building toward an autonomous CFO -systems that run company financials end-to-end. Our platform analyzes complex financial data in real time to increase decision cadence, prevent costly mistakes, and surface value. Sapien has caught multi-million-dollar errors, saved thousands of jobs, and returned significant dollars to customers' bottom lines. We partner with traditional businesses-manufacturing, healthcare, restaurants, and large enterprises-to deeply understand and automate their financial workflows. We're HQ'd by Madison Square Park in NYC and backed by General Catalyst, Neo , and top operators from Google, OpenAI, Microsoft, Ramp, and Stripe (over $9M raised). The role You'll design and build the interfaces that make AI agents usable for finance teams. This means creating new interaction patterns for how humans work with autonomous systems, building the design systems that scale across our platform, and obsessing over the details that make complex workflows feel simple. This is a design-focused frontend role where craft and user experience matter deeply. You'll own the visual and interaction design of features while implementing them in production. What you'll do - Design and build interfaces that make agent operations transparent and controllable. Create new interaction patterns for real-time AI workflows, verification systems, and human-in-the-loop feedback that don't exist yet. - Prototype and iterate rapidly on new interface concepts. Work directly with customers to test designs, watch how they interact with features, and refine", "matched_input": "design", "derivation_source": "row_field", "candidate_evidence_id": null, "rerank_evidence_id": null, "taxonomy_alias_id": null, "oracle_verification_method": "row_field_contains", "counts_for_non_trivial_query": true, "truth_verified": true, "exact": true, "priority": 80, "mobile_priority": 2, "ui": { "icon": "SearchCheck", "tone": "match", "href": null } } ], "parental_leave_source_label": null, "k401_match_source_label": null, "k401_contribution_source_label": null, "apply_url_checked_at": null, "apply_url_verification_status": "not_reachable_or_not_checked", "apply_url_verification_label": "Not checked or not reachable at last crawl", "field_source_signals": { "equity_included": { "tier": "inferred", "verified": false, "label": "Inferred - source not recorded", "source_label": "source not recorded", "href": null, "source_values": [], "checked_at": "2026-06-20T05:42:05.724Z" }, "seniority": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/sapien/e1a51be9-6d18-468f-9aed-6d58a6481007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" }, "role_function": { "tier": "posting", "verified": true, "label": "From the posting", "source_label": "the posting", "href": "https://jobs.ashbyhq.com/sapien/e1a51be9-6d18-468f-9aed-6d58a6481007", "source_values": [ "llm:greenfield:inv_371_postfix" ], "checked_at": "2026-06-20T05:42:05.724Z" } } } ], "total": 394, "page": 6, "per_page": 100, "applied_filters": { "q": "Cadence Design Systems, Inc." }, "hidden_unknown_benefits_count": 0, "hidden_quality_floor_count": 0, "quality_floor": "default", "search_profile": { "profile_id": "inv382.d6.pg_textsearch_bge_small_rrf.v1", "bm25_extension": "pg_textsearch", "vector_model": "BAAI/bge-small-en-v1.5", "vector_model_version": "v1.5", "fusion_method": "rrf" }, "explanation_context": { "non_trivial_query": true, "query_terms": [ "cadence", "design", "systems", "inc" ], "active_filter_keys": [], "visible_signal_limit": 3, "visible_trust_limit": 2 }, "event_context": { "query_context": { "query_id": "6dfa513c-b4ae-4673-a5f6-f04b273b767c", "issued_at": "2026-08-13T15:00:09.522Z", "route": "/jobs", "page": 6, "per_page": 100, "total_results": 394, "sort": "relevance", "ranking_policy": "hybrid_rrf_rerank", "ranking_policy_version": "inv382.jobs.search.v2", "query_hash": "hmac_sha256:wyYDz3wCxiouHluuLRWb72IXJPcorunyj8hnu3Bspt0", "filter_hash": "hmac_sha256:6CBErDPXOFVCSNkSGbTmuw6GxoMjwSLro0KqZMtxL_0", "query_features": { "has_q": true, "q_term_count": 4, "q_length_bucket": "16_40", "q_pii_redacted": false, "state_count": 0, "benefit_filters": [], "quality_floor": "default" }, "exposures": [ { "result_id": "d168458ff5aa34fbf7ff497a638d1b35", "position": 501, "page_position": 1, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3158303687471359, "rrf_score": 0.0022222222222222222, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 82, "quality_score": 55 } }, { "result_id": "c5c92b4c4a293354df1db5f522d37f44", "position": 502, "page_position": 2, "retrieval_features": { "bm25_score": -11.138260841369629, "vector_score": 0, "rrf_score": 0.0022222222222222222, "text_match_title": true, "text_match_employer": true, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 161, "quality_score": 45 } }, { "result_id": "563ff30110f8dfcfa201700a7201889f", "position": 503, "page_position": 3, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31583213806152344, "rrf_score": 0.0022172949002217295, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "b4abcbf45dbe47dd9f0ff595639e42f9", "position": 504, "page_position": 4, "retrieval_features": { "bm25_score": -10.909364581108093, "vector_score": 0, "rrf_score": 0.0022172949002217295, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 449, "quality_score": 45 } }, { "result_id": "ac7833fe5b4966c777aeb72fa13ec4f4", "position": 505, "page_position": 5, "retrieval_features": { "bm25_score": -10.867087602615356, "vector_score": 0, "rrf_score": 0.0022123893805309734, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "54221bec3abf57734b510639725bc3df", "position": 506, "page_position": 6, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3158975055278822, "rrf_score": 0.0022123893805309734, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 188, "quality_score": 55 } }, { "result_id": "c883e76f487d7b9479723b14b8b5dfef", "position": 507, "page_position": 7, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3159487059146925, "rrf_score": 0.002207505518763797, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 125, "quality_score": 55 } }, { "result_id": "dd5de0249310b4162aea8924bb9fb377", "position": 508, "page_position": 8, "retrieval_features": { "bm25_score": -10.805089473724365, "vector_score": 0, "rrf_score": 0.0022026431718061676, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 107, "quality_score": 45 } }, { "result_id": "c0ef1f8d705f20dc98eaf7cc4060855f", "position": 509, "page_position": 9, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31601405143737793, "rrf_score": 0.0022026431718061676, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 243, "quality_score": 45 } }, { "result_id": "78666d4d186f7ce1040ceff1dff2837f", "position": 510, "page_position": 10, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31602356934406817, "rrf_score": 0.002197802197802198, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 67, "quality_score": 45 } }, { "result_id": "0367b1b872a7b991ea529bb2a2584fdb", "position": 511, "page_position": 11, "retrieval_features": { "bm25_score": -10.768564581871033, "vector_score": 0, "rrf_score": 0.002197802197802198, "text_match_title": false, "text_match_employer": true, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "f4f09d26ed43309b193eeb3ed5091fa4", "position": 512, "page_position": 12, "retrieval_features": { "bm25_score": -10.768564581871033, "vector_score": 0, "rrf_score": 0.0021929824561403508, "text_match_title": true, "text_match_employer": true, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "455cde8db36a923ddd68f1be6ccdcc86", "position": 513, "page_position": 13, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3161621501349109, "rrf_score": 0.0021929824561403508, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 216, "quality_score": 45 } }, { "result_id": "0ac4c9d6ffeae41504193872246dbf32", "position": 514, "page_position": 14, "retrieval_features": { "bm25_score": 0, "vector_score": 0.316267192363739, "rrf_score": 0.002188183807439825, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "2f2362ada29748499707c97e58b29c4b", "position": 515, "page_position": 15, "retrieval_features": { "bm25_score": -10.747098088264465, "vector_score": 0, "rrf_score": 0.002188183807439825, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "513fa84462597ce5546de071f4ef061b", "position": 516, "page_position": 16, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3162946105003357, "rrf_score": 0.002183406113537118, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 62, "quality_score": 35 } }, { "result_id": "6ab336b3e87370b96bd785af6a7c4d92", "position": 517, "page_position": 17, "retrieval_features": { "bm25_score": -10.747098088264465, "vector_score": 0, "rrf_score": 0.002183406113537118, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "e604fd6cffcec03ab464b0e5b3e876d2", "position": 518, "page_position": 18, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31631743907928467, "rrf_score": 0.002178649237472767, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 65, "quality_score": 55 } }, { "result_id": "8759d18332bcb5169a708fc984d3d7e4", "position": 519, "page_position": 19, "retrieval_features": { "bm25_score": -10.72600543498993, "vector_score": 0, "rrf_score": 0.002178649237472767, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 64, "quality_score": 45 } }, { "result_id": "a3f11edc0a1843409a7d10f554016141", "position": 520, "page_position": 20, "retrieval_features": { "bm25_score": -10.716707468032837, "vector_score": 0, "rrf_score": 0.002173913043478261, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 190, "quality_score": 45 } }, { "result_id": "c655354d3134d053c93413b59a062b4c", "position": 521, "page_position": 21, "retrieval_features": { "bm25_score": -10.716707468032837, "vector_score": 0, "rrf_score": 0.0021691973969631237, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 79, "quality_score": 45 } }, { "result_id": "3b061c5d927b2d8b327233813b3b48d1", "position": 522, "page_position": 22, "retrieval_features": { "bm25_score": -10.716371655464172, "vector_score": 0, "rrf_score": 0.0021645021645021645, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 93, "quality_score": 55 } }, { "result_id": "af18b14c4cef11a0d60aac8cb6da8326", "position": 523, "page_position": 23, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31639758846774046, "rrf_score": 0.0021645021645021645, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 236, "quality_score": 55 } }, { "result_id": "7ae089708c568d3ea745cc9a53b8329f", "position": 524, "page_position": 24, "retrieval_features": { "bm25_score": -10.716371655464172, "vector_score": 0, "rrf_score": 0.0021598272138228943, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "82594b95317916562dc5ec7572270a2e", "position": 525, "page_position": 25, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3164268732070923, "rrf_score": 0.0021551724137931034, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 166, "quality_score": 55 } }, { "result_id": "948c1b428a6e03db8bfc708f45aac4f7", "position": 526, "page_position": 26, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31648755073547363, "rrf_score": 0.002145922746781116, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 68, "quality_score": 55 } }, { "result_id": "3b22083ac89d716f4ee7a159ad7bccbd", "position": 527, "page_position": 27, "retrieval_features": { "bm25_score": -10.558871150016785, "vector_score": 0, "rrf_score": 0.002145922746781116, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 265, "quality_score": 55 } }, { "result_id": "6673af001de5fa108be007dd2ef71dd4", "position": 528, "page_position": 28, "retrieval_features": { "bm25_score": -10.542627453804016, "vector_score": 0, "rrf_score": 0.0021413276231263384, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 146, "quality_score": 45 } }, { "result_id": "46a8e8346409c975908198bb140566d0", "position": 529, "page_position": 29, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31657564640045166, "rrf_score": 0.002136752136752137, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 272, "quality_score": 55 } }, { "result_id": "a259b004cbd6f721effd72cd05fc0030", "position": 530, "page_position": 30, "retrieval_features": { "bm25_score": -10.527463793754578, "vector_score": 0, "rrf_score": 0.002136752136752137, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 133, "quality_score": 45 } }, { "result_id": "ce39f7bf2e9b2a01877e8ed993ec1bae", "position": 531, "page_position": 31, "retrieval_features": { "bm25_score": -10.526838183403015, "vector_score": 0, "rrf_score": 0.0021321961620469083, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 126, "quality_score": 55 } }, { "result_id": "33b8e542f5c81757f3ad0315c0fbcd3d", "position": 532, "page_position": 32, "retrieval_features": { "bm25_score": -10.52565610408783, "vector_score": 0, "rrf_score": 0.002127659574468085, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 171, "quality_score": 55 } }, { "result_id": "07d2a63b9adc8f26aa5dc500a362d548", "position": 533, "page_position": 33, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31680840253829956, "rrf_score": 0.002127659574468085, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 64, "quality_score": 45 } }, { "result_id": "302fe92d31fb3ee214ed6c0848f80d03", "position": 534, "page_position": 34, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31690482396454545, "rrf_score": 0.0021231422505307855, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 118, "quality_score": 55 } }, { "result_id": "b1c74eadba8cd0fe30b9aa664f60ac88", "position": 535, "page_position": 35, "retrieval_features": { "bm25_score": -10.407671689987183, "vector_score": 0, "rrf_score": 0.00211864406779661, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 90, "quality_score": 55 } }, { "result_id": "f9d3267c5393c0125181c203ab0deb49", "position": 536, "page_position": 36, "retrieval_features": { "bm25_score": -10.407671689987183, "vector_score": 0, "rrf_score": 0.0021141649048625794, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 93, "quality_score": 55 } }, { "result_id": "bdacc30d2605ce3d2d7e4739a5960bb6", "position": 537, "page_position": 37, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31696319580078125, "rrf_score": 0.0021141649048625794, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 229, "quality_score": 55 } }, { "result_id": "8ec9eb4c637a41a4c0ce0fa951cf3789", "position": 538, "page_position": 38, "retrieval_features": { "bm25_score": -10.387116312980652, "vector_score": 0, "rrf_score": 0.002109704641350211, "text_match_title": true, "text_match_employer": true, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 139, "quality_score": 45 } }, { "result_id": "4bd195f65b04314533d6d13ac5d3994c", "position": 539, "page_position": 39, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31706154346466064, "rrf_score": 0.002105263157894737, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 103, "quality_score": 55 } }, { "result_id": "0d028fae7bab8214e421c5996f506a36", "position": 540, "page_position": 40, "retrieval_features": { "bm25_score": -10.3446946144104, "vector_score": 0, "rrf_score": 0.002105263157894737, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 104, "quality_score": 45 } }, { "result_id": "a7b866cb0f84dbbf978e80e810407ccd", "position": 541, "page_position": 41, "retrieval_features": { "bm25_score": -10.311951518058777, "vector_score": 0, "rrf_score": 0.0021008403361344537, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 62, "quality_score": 45 } }, { "result_id": "c3027fb964fbdf21aa1d20808addfe8d", "position": 542, "page_position": 42, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3171170949935913, "rrf_score": 0.0021008403361344537, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 64, "quality_score": 45 } }, { "result_id": "71d303448fcdc1e0e00c3479d83c61b5", "position": 543, "page_position": 43, "retrieval_features": { "bm25_score": -10.304445385932922, "vector_score": 0, "rrf_score": 0.0020964360587002098, "text_match_title": false, "text_match_employer": true, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 62, "quality_score": 45 } }, { "result_id": "78bdd5261dc30ee66aad6da68fe239a9", "position": 544, "page_position": 44, "retrieval_features": { "bm25_score": -10.28814160823822, "vector_score": 0, "rrf_score": 0.0020920502092050207, "text_match_title": false, "text_match_employer": true, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 85, "quality_score": 55 } }, { "result_id": "3884b7fcc85ccb85c0366921667c76e7", "position": 545, "page_position": 45, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3175400495529175, "rrf_score": 0.0020876826722338203, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 120, "quality_score": 45 } }, { "result_id": "2381d96ab5a63519067dc70ed02c7fd5", "position": 546, "page_position": 46, "retrieval_features": { "bm25_score": -10.247586607933044, "vector_score": 0, "rrf_score": 0.0020876826722338203, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 197, "quality_score": 45 } }, { "result_id": "991af5db2ccb724217120cf229a185b0", "position": 547, "page_position": 47, "retrieval_features": { "bm25_score": -10.197032570838928, "vector_score": 0, "rrf_score": 0.002079002079002079, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 65, "quality_score": 55 } }, { "result_id": "e14c17dba55cdf850028a4a0d0b756b3", "position": 548, "page_position": 48, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3176760673522949, "rrf_score": 0.002074688796680498, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 75, "quality_score": 55 } }, { "result_id": "7d8de16c4d3c952750ab7a9db1c95536", "position": 549, "page_position": 49, "retrieval_features": { "bm25_score": -10.16431474685669, "vector_score": 0, "rrf_score": 0.002074688796680498, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 69, "quality_score": 45 } }, { "result_id": "ec7980703903401dcbf8263ec3f3021c", "position": 550, "page_position": 50, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31771008127063727, "rrf_score": 0.002070393374741201, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 66, "quality_score": 55 } }, { "result_id": "cd7186948e2d85a070ef8331f5dd7d68", "position": 551, "page_position": 51, "retrieval_features": { "bm25_score": -10.16431474685669, "vector_score": 0, "rrf_score": 0.002070393374741201, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 66, "quality_score": 55 } }, { "result_id": "b8990488ddb55fe225be596102addc44", "position": 552, "page_position": 52, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31771359934129595, "rrf_score": 0.002066115702479339, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 65, "quality_score": 55 } }, { "result_id": "c24709a748633087351902129c2423c2", "position": 553, "page_position": 53, "retrieval_features": { "bm25_score": -10.134289026260376, "vector_score": 0, "rrf_score": 0.002066115702479339, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 268, "quality_score": 55 } }, { "result_id": "6652916bfca99a61ba43e3467014a90e", "position": 554, "page_position": 54, "retrieval_features": { "bm25_score": -10.066415309906006, "vector_score": 0, "rrf_score": 0.002061855670103093, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 139, "quality_score": 55 } }, { "result_id": "db83c58d918450908df9a1a9285df234", "position": 555, "page_position": 55, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3177698850631714, "rrf_score": 0.002061855670103093, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 148, "quality_score": 55 } }, { "result_id": "11e11377008b3cd6233af7b07ce3e454", "position": 556, "page_position": 56, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3177868127822876, "rrf_score": 0.00205761316872428, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 99, "quality_score": 45 } }, { "result_id": "2eba1d8e0f098555621d2111c6498814", "position": 557, "page_position": 57, "retrieval_features": { "bm25_score": -10.065877914428711, "vector_score": 0, "rrf_score": 0.00205761316872428, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 229, "quality_score": 45 } }, { "result_id": "c322b1e39fe2746e13cd5105556fa2e6", "position": 558, "page_position": 58, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3177915432701607, "rrf_score": 0.002053388090349076, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 73, "quality_score": 45 } }, { "result_id": "fc843570a00b1063d9f54eceadd6fd93", "position": 559, "page_position": 59, "retrieval_features": { "bm25_score": -10.049688220024109, "vector_score": 0, "rrf_score": 0.0020491803278688526, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 71, "quality_score": 55 } }, { "result_id": "2717b2b1b8ec99607f8ff1b2d5b80afa", "position": 560, "page_position": 60, "retrieval_features": { "bm25_score": -10.047093152999878, "vector_score": 0, "rrf_score": 0.002044989775051125, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 330, "quality_score": 55 } }, { "result_id": "d85da07c3db5d1fa1099fe10562d85ac", "position": 561, "page_position": 61, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3178420066833496, "rrf_score": 0.002044989775051125, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "2833bbb49fa922ecf18ee35aaf9bc765", "position": 562, "page_position": 62, "retrieval_features": { "bm25_score": -10.032623529434204, "vector_score": 0, "rrf_score": 0.0020408163265306124, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 70, "quality_score": 45 } }, { "result_id": "0236c06eb6b8d180d073d4c6eb82b521", "position": 563, "page_position": 63, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3179764747619629, "rrf_score": 0.0020408163265306124, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 254, "quality_score": 55 } }, { "result_id": "f7bb8584c3414fd14f80a228f2afc65f", "position": 564, "page_position": 64, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3180535246101889, "rrf_score": 0.002036659877800407, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 64, "quality_score": 45 } }, { "result_id": "f9de76671576f5e64f71bc0df81f409b", "position": 565, "page_position": 65, "retrieval_features": { "bm25_score": -10.02357268333435, "vector_score": 0, "rrf_score": 0.002036659877800407, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 63, "quality_score": 55 } }, { "result_id": "1724fefa0c39fad29a3153587e114f79", "position": 566, "page_position": 66, "retrieval_features": { "bm25_score": -10.003099918365479, "vector_score": 0, "rrf_score": 0.0020325203252032522, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 175, "quality_score": 45 } }, { "result_id": "5d8865e9d533ce4e2e454a4f48fade1a", "position": 567, "page_position": 67, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3180732727050781, "rrf_score": 0.0020325203252032522, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "64f830a528849cbfe1d247a4c5556c4e", "position": 568, "page_position": 68, "retrieval_features": { "bm25_score": -9.967719316482544, "vector_score": 0, "rrf_score": 0.002028397565922921, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 63, "quality_score": 55 } }, { "result_id": "b0f7d81fab905832b384da238c2870c6", "position": 569, "page_position": 69, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31817370653152466, "rrf_score": 0.002028397565922921, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 107, "quality_score": 55 } }, { "result_id": "39b0b5c2347227ce66519ea70ef53a1b", "position": 570, "page_position": 70, "retrieval_features": { "bm25_score": -9.91622805595398, "vector_score": 0, "rrf_score": 0.0020242914979757085, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 85, "quality_score": 45 } }, { "result_id": "4c612bc052f0fe4e0383a49610343f7b", "position": 571, "page_position": 71, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3182381201840555, "rrf_score": 0.0020242914979757085, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 188, "quality_score": 45 } }, { "result_id": "857c18f61fb9e35864e04248b72dcdfc", "position": 572, "page_position": 72, "retrieval_features": { "bm25_score": -9.91622805595398, "vector_score": 0, "rrf_score": 0.00202020202020202, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 64, "quality_score": 55 } }, { "result_id": "237687a15733503c39cbfab76968c8c2", "position": 573, "page_position": 73, "retrieval_features": { "bm25_score": 0, "vector_score": 0.318276047706604, "rrf_score": 0.0020161290322580645, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 35 } }, { "result_id": "89237a0be43b9b20049998f2d984e80d", "position": 574, "page_position": 74, "retrieval_features": { "bm25_score": -9.912536144256592, "vector_score": 0, "rrf_score": 0.0020161290322580645, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 153, "quality_score": 55 } }, { "result_id": "a888d04c74f92939319cd2aa0deb85ef", "position": 575, "page_position": 75, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3183743574172976, "rrf_score": 0.002012072434607646, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 101, "quality_score": 55 } }, { "result_id": "b72bd726c0d161cd164b00bb2414c882", "position": 576, "page_position": 76, "retrieval_features": { "bm25_score": -9.909729480743408, "vector_score": 0, "rrf_score": 0.002012072434607646, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 156, "quality_score": 55 } }, { "result_id": "57bdc0768d63948d5f0de7c9a35f08d7", "position": 577, "page_position": 77, "retrieval_features": { "bm25_score": -9.905516624450684, "vector_score": 0, "rrf_score": 0.002008032128514056, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 74, "quality_score": 45 } }, { "result_id": "7a4c46cb137b12aaa937d9580af1c99f", "position": 578, "page_position": 78, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3185175657272339, "rrf_score": 0.002004008016032064, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 69, "quality_score": 55 } }, { "result_id": "982f073461e2c8e2a6608891dda99542", "position": 579, "page_position": 79, "retrieval_features": { "bm25_score": -9.892383575439453, "vector_score": 0, "rrf_score": 0.002004008016032064, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 83, "quality_score": 55 } }, { "result_id": "ffbb8756f25e23de9c3b94dc5cd7e783", "position": 580, "page_position": 80, "retrieval_features": { "bm25_score": -9.861317873001099, "vector_score": 0, "rrf_score": 0.002, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 233, "quality_score": 55 } }, { "result_id": "9e8770af1e49f3774050f2d79523cb71", "position": 581, "page_position": 81, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31854718923568726, "rrf_score": 0.002, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 45 } }, { "result_id": "1d8095f577528b5a1fe7a692288ce6d8", "position": 582, "page_position": 82, "retrieval_features": { "bm25_score": -9.85335659980774, "vector_score": 0, "rrf_score": 0.001996007984031936, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 64, "quality_score": 45 } }, { "result_id": "23608718d9172df911b7892161cd5ada", "position": 583, "page_position": 83, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31869212873624864, "rrf_score": 0.001996007984031936, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 192, "quality_score": 45 } }, { "result_id": "e08dda8b604700b9cc805f913f3ea832", "position": 584, "page_position": 84, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31875181198120117, "rrf_score": 0.00199203187250996, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 62, "quality_score": 45 } }, { "result_id": "e182e4832295e8c2eafc0fcb9d1431c0", "position": 585, "page_position": 85, "retrieval_features": { "bm25_score": -9.845234990119934, "vector_score": 0, "rrf_score": 0.00199203187250996, "text_match_title": true, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 132, "quality_score": 55 } }, { "result_id": "58a33c3ac0aa55bf384260747f73fc5a", "position": 586, "page_position": 86, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31882540471402254, "rrf_score": 0.0019880715705765406, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 99, "quality_score": 55 } }, { "result_id": "1b08c8711b4fc798db50c08f69bda604", "position": 587, "page_position": 87, "retrieval_features": { "bm25_score": -9.798718214035034, "vector_score": 0, "rrf_score": 0.0019880715705765406, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 111, "quality_score": 45 } }, { "result_id": "2ad0ac4a1d1ec99c7b460a4cc405aaca", "position": 588, "page_position": 88, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3188265372022058, "rrf_score": 0.001984126984126984, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 94, "quality_score": 55 } }, { "result_id": "e4ff60f1cd808040164024f0d64afa61", "position": 589, "page_position": 89, "retrieval_features": { "bm25_score": -9.796941637992859, "vector_score": 0, "rrf_score": 0.001984126984126984, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 163, "quality_score": 45 } }, { "result_id": "c014696f5bca3ed621323f30b43cc92d", "position": 590, "page_position": 90, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31886255741119385, "rrf_score": 0.0019801980198019802, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 93, "quality_score": 55 } }, { "result_id": "786d3df6553ca8b4948757a40b0936d2", "position": 591, "page_position": 91, "retrieval_features": { "bm25_score": -9.774736404418945, "vector_score": 0, "rrf_score": 0.0019801980198019802, "text_match_title": true, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 93, "quality_score": 35 } }, { "result_id": "7fa1d757753f4efb49f141e26b626b4f", "position": 592, "page_position": 92, "retrieval_features": { "bm25_score": 0, "vector_score": 0.3189006447792053, "rrf_score": 0.001976284584980237, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 90, "quality_score": 35 } }, { "result_id": "5aa231a58b6328449379acf79557fa15", "position": 593, "page_position": 93, "retrieval_features": { "bm25_score": -9.765534281730652, "vector_score": 0, "rrf_score": 0.001976284584980237, "text_match_title": false, "text_match_employer": true, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 62, "quality_score": 55 } }, { "result_id": "3918dbf47b4a7e5c4c162728ff531c57", "position": 594, "page_position": 94, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31897401809692383, "rrf_score": 0.0019723865877712033, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": false, "posted_age_days": 106, "quality_score": 45 } }, { "result_id": "8eb87d93fb4076ed48eb2504a313089c", "position": 595, "page_position": 95, "retrieval_features": { "bm25_score": -9.737335801124573, "vector_score": 0, "rrf_score": 0.001968503937007874, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 114, "quality_score": 55 } }, { "result_id": "8f8f8199a492a513db8e2b80199ab828", "position": 596, "page_position": 96, "retrieval_features": { "bm25_score": -9.727217674255371, "vector_score": 0, "rrf_score": 0.0019646365422396855, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": true, "posted_age_days": 63, "quality_score": 55 } }, { "result_id": "ac23146aa64a2151e09c7fb0842dc431", "position": 597, "page_position": 97, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31905126571655273, "rrf_score": 0.0019646365422396855, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 114, "quality_score": 45 } }, { "result_id": "5ad6642a87fc4a8d03196324c5fc4a9d", "position": 598, "page_position": 98, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31913256645202637, "rrf_score": 0.00196078431372549, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 66, "quality_score": 55 } }, { "result_id": "a49c4d072dd53639931e1c25d72fe036", "position": 599, "page_position": 99, "retrieval_features": { "bm25_score": 0, "vector_score": 0.31918899302548087, "rrf_score": 0.0019569471624266144, "text_match_title": false, "text_match_employer": false, "role_match": true, "benefit_verified": true, "salary_disclosed": true, "posted_age_days": 82, "quality_score": 55 } }, { "result_id": "0df1e0bdcf52ee53ad233ddac23a1022", "position": 600, "page_position": 100, "retrieval_features": { "bm25_score": -9.717060804367065, "vector_score": 0, "rrf_score": 0.0019569471624266144, "text_match_title": false, "text_match_employer": false, "role_match": false, "benefit_verified": false, "salary_disclosed": false, "posted_age_days": 189, "quality_score": 45 } } ] }, "context_signature": "jcBiKT6KWzc-xfv3wFRuqHRTnvDUHg4LqnBzsdg4Drg", "event_token": "jcBiKT6KWzc-xfv3wFRuqHRTnvDUHg4LqnBzsdg4Drg" } }